Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems Marcus T. Schmitz and Bashir M. Al-Hashimi University of Southampton,

Energy-Efficient Mapping and Scheduling for DVS Enabled

Distributed Embedded Systems

Marcus T. Schmitz and Bashir M. Al-HashimiUniversity of Southampton, United Kingdom

Petru ElesLinköping University, Sweden

2Marcus T. SchmitzUniversity of Southampton

Contents• Motivation & Introduction

• Dynamic Voltage Scaling

• Co-Synthesis with DVS Consideration

• DVS optimised Scheduling

• DVS optimised Mapping

• Experimental Results

• Conclusions


MotivationLow Energy:

• Portable Applications

• Autonomous Systems

• Feasibilty Issues (SoC - heat)

• Operational Cost and Environmental Reasons

System Level Co-Design:

• Shrinking Time-To-Market Windows

• Reducing Production Cost

• High Degree of Optimisation Freedom


Introduction

Dynamic Voltage Scaling

System Level Co-Synthesis

Energy-Efficient Co-Synthesis for

DVS Sytems


Dynamic Voltage Scaling (DVS)

f Reg.

DVS Processor

0

0.2

0.4

0.6

0.8

1

1.2

1 1.5 2 2.5 3 3.5 4 4.5 5

Energy vs. Speed

Voltage/Frequency

Frequency

VR

Available from: Transmeta, AMD, Intel

1/Speed

En

erg

y

2ddVkE


Co-Synthesis for DVS Systems

Allocation

Mapping

Scheduling

Voltage Scaling

Evaluation

EE

-GL

SA

EE

-GM

A

De

sig

ne

r d

riv

en

System Specification, Technology Lib.


DVS in Distributed Systems [23]

PE0

PE1

CL0

P

td

PE0

PE1

CL0

P

td

@ Vmax @ dyn. V

Input:Scheduling (mapping)Power profile

Output:scaled voltage for each DVS task

Emax Esc < Emax

Slack

2.3V 2.4V3.3V

Voltage Scaling


Energy-Efficient Scheduling

Two objectives:

• Timing feasibility

• Garantee deadlines

• Low energy dissipation

• Optimisation DVS usability – Slack time

Problem due to power variations:

• Simply increase deadline slack leads to sub-optimal solutions!

Traditional scheduling technique focus mainly on timing feasibility!


Energy-Efficient Scheduling

0

4 5

12

36

E=71J

4 5

01 2

36

4 5

01 2

3 6

012

36

4 5

E=71J

E=53.9J

E=65.6J

Slack Savings

Slack Savings

S1:

S2:

DVS

DVS

Slack

Slack

PE0

PE1

PE2

PE0

PE1

PE2

P

t t

tt

P

P

P


Energy-Efficient Scheduling• Based on Genetic List Scheduling Algorithm [6,10]

• Task priorities are encoded into priorities strings

List Scheduler

4 3 9 7 2

PS

Duties of the Scheduler:1. Select ready task with highest

priority2. Schedule selected task3. Update schedule and ready list4. Repeat until no un-scheduled

task is left

Schedule


EE-GLSA

List Scheduler DVS

Assign fitness

Rank individuals

Selection

Mutation

Mating

InsertionIniti

al P

opul

atio

n

Opt

imis

ed P

opul

atio

n

GA

low high

Timing, Energy

3

7

8

1

2

3

2

1

3

2

No Hole Filling!No Mapping!


Advantages

• Optimisation can be based on an arbitrary complex

fitness function, including:

• Timing

• Energy (DVS technique)

• Enlarged search space (|T+C|! different schedules)

• Trade-off freedom: Synthesis time <-> quality

• Easily adaptable to computing clusters

• Multiple populations with immigration scheme


Hole Filling Problem

d2

d4

d3

7

6

4

4

1

d2 d3,4

Hole filling

Therefore, priorities decide solely upon execution order!

PE0

PE1


Task Mapping

Why seperation from the list scheduling?• Regardless of priorties, greedy mapping

LS

d2

7

4

5

d1

d1,2

PE0

PE1

P

t


Task Mapping

Make greedy mapping decision based on:• Timing• Energy

LS

d2

7

4

5

d1

d1,2

?

?PE0

PE1

P

t


Task Mapping

Make mapping decision based on:• Timing• Energy

LS

d2

7

4

5

d1

d1,2

PE0

PE1

P

t


Task Mapping


LS

d2

7

4

5

d1

d1,2

?

?

PE0

PE1

P

t


Task Mapping


LS

d2

7

4

5

d1

d1,2

PE0

PE1

P

t


Task Mapping


LS

d2

7

4

5

d1

d1,2

PE0

PE1

P

t


Task Mapping


LS

d2

7

4

5

d1

d1,2

PE0

PE1

P

t


Task Mapping


LS

d2

7

4

5

d1

d1,2

PE0

PE1

P

t


Genetic Mapping Algorithm [8]

CPU DVS-CPU

ASIC

01

2d

d

5

3

6

4

0

1 2

task PE

0 1

1 0

2 2

3 1

4 1

5 0

6 0

Chromosome

Task mapping are encoded into mapping strings


EE-GMA

EE-GLSA

Assign fitness

Rank individuals

Selection

Mutation

Mating

Insertion

Initi

al P

opul

atio

n

Opt

imis

ed P

opul

atio

n

GA

low high

Timing, Energy + Area

Including DVS


Experimental Results• 4 Benchmark Sets:

• 27 generated by TGFF [7]

– 8 to 100 tasks: Power variations 2.6

• 2 Hou examples taken from [13]

– 8 to 20 tasks: Power variations 11

• TG1 and TG2 taken from [11]

– 60 examples with 30 tasks, each: No power variations

• Measurement application taken from [3]

– 12 tasks: No power profile is provided

• Power and time overhead for DVS is neglected

• Average results of 5 optimisation runs


Schedule Optimisation

0

10

20

30

40

50

60

70

80

Tgff1 Tgff2 Tgff3 Tgff4 Tgff5 Tgff6 Tgff7 Tgff8 Tgff9 Tgff10

Example

Red

uct

ion

(%

)

EVEN-DVS[18]

GLSA+EVEN

EE-GLSA


Schedule Optimisation

0

5

10

15

20

25

30

35

40

TG1 TG2

Benchmark set

Re

du

cti

on

(%

)

LEneS [11]

EE-GLSA


Mapping Optimisation

0

10

20

30

40

50

60

70

80

90

Tgff1 Tgff2 Tgff3 Tgff4 Tgff5 Tgff6 Tgff7 Tgff8 Tgff9 Tgff10

Example

Red

uct

ion

(%

)

EVEN-DVS

EE-GMA


Conclusions

• DVS capability can achieve high energy savings in distributed embedded systems

• Proposed a new energy-efficient two-step mapping and scheduling approach

• Iterative improvement provides high savings / ad hoc constructive techniques are not suitable

• Optimisation times are reasonable

• Additional objectives can be easily included

• Consideration of power profile information leads to further energy reductions

Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems Marcus T. Schmitz and Bashir M. Al-Hashimi University of Southampton,

Documents

pe0 pe1 slide

mapping strings slide

energyefficient mapping

speed energy slide

pe0 pe1 p t

chromosome task mapping

schedule slide

dvs sytems slide