Encryption/Decryption system Midterm Presentation

Encryption/Decryption systemMidterm Presentation

By: Shay Amosi & Jasmin Amitai

Mentor: Mony Orbach

Spring 2013

Our project Our project goal is to create a hardware system that encrypts the data quickly and efficiently. The system will simulate real-time encryption between a PC and USB using FPGA.

Twofish

The Twofish is a symmetric key 128-bit Block Feistel network. Twofish can work with variable key length from 128 to 256

bits. Twofish exhibits fast and versatile performance across most

platforms. The Twofish structure offers a great deal of flexibility in terms

of space versus speed tradeoffs.

The Twofish algorithn

The Twofish algorithn

The Twofish Consists of the following steps:The plaintext is split into 4 words Input Whitening16 rounds of the F functionOutput Whitening

Implementation methods

Pipeline: Good choice when it comes to performance, best for

pipes that contain pure logic flow without too many stalls resulting from control lines. Requires the use of many resources.

Iterative: Good choice when it comes to cost reduction, best when

we are not required to meet high performance.

Combining both: Good choice when we want to achieve the optimal

performance under resource constraints, yet the implementation is more complex.

f f f f

f

f f

Pipeline is our choice!

Since the goal of our project as we have defined

earlier is a high-performances, and the core of

our hardware performs many serial permutations and logic calculations,

the right choice is to pipe our computational

unit.

During the project we will have to match the

dimensions of our design to the FPGA’s size.

TOP LEVEL SCHEME

Fifo in

Twofish

Fifo out

SRAM

Twofish control

Keys ROM

TWOFISH ALGORITHEM

DATA I

N

f

H

H

PHT

f

H

H

PHT

DATA

OUT

X 16

Twofish top level

Twofish control

Twofish (Encoder/Decoder)

Twofish pipe

F-component

f-function

H-function

Interfacing with SRAM

Hardware environment

FPGA

TWOFISH

FIFOIN

FIFO OUT

CTRL

Hardware Test Phase #1: Defining a set of unique inputs as the test blocks to be

encrypted and save the plaintext in a separate file.

Phase #2: Encrypt the set of inputs (henceforth- Twofished blocks).

Phase #3: Save the ciphered text in a separate file and compare it with the

expected output. (This comparison is necessary to verify the correctness of the encryption and avoid possible double errors)

Phase #4: Decrypt the Twofished blocks and compare it to the initial test

blocks via automated script.

Hardware Test (Phase #1-3)

256KB

256KB

FPGA

TWOFISHFIFOIN

FIFO OUT

CTRL

PHASE #3

PHASE #1

PLAINTEXT

CIPHERTEXT

PHASE #2

Hardware Test (Phase #4)

256KB

256KB

FPGA

TWOFISHFIFOIN

FIFO OUT

CTRL

PLAINTEXT????????

CIPHERTEXT

PHASE #4

Project timeline

7-2013 • סיוםכתיבתקודההצפנה Twofish וכתיבתקודה - Controller8-2013 • תקופתמבחנים 9-2013 • קומפילציהוסימולציהכלליתב - Modelsim

9-2013 • בדיקתתאימותתכולהב - FPGA והוספתהשינוייםהמתאימים 9-2013 • סימולציההיקפיתב - Modelsim

10-2013 • סינתזהב - Quartus

10-2013 • הורדתהתכןל - FPGA

10-2013 • הרצתהמערכתבחומרהובניית Tests מוגדריםמראש

12-2013 • בדיקהוניתוחביצועים