Encryption Transaction with 3DES

Encryption Transaction with Encryption Transaction with 3DES3DES

Team W2Team W2Yervant Dermenjian Yervant Dermenjian (W21)(W21)Taewan Kim Taewan Kim (W22)(W22)Evan MengstabEvan Mengstab (W23)(W23)Xiaochun ZhuXiaochun Zhu (W24)(W24)Objective:Objective: To implement a To implement a

secure credit card transaction secure credit card transaction using 3DES encryption using using 3DES encryption using Kerberos-style authentication.Kerberos-style authentication.

Current Stage: Full Chip SPICE SimulationCurrent Stage: Full Chip SPICE Simulation 03/31/200403/31/2004

Design Manager: Rebecca MillerDesign Manager: Rebecca Miller

Current StatusCurrent Status Design Proposal (100% done)Design Proposal (100% done)

Architecture Proposal (100% done)Architecture Proposal (100% done)

Size Estimate and Floor Plan (100% done)Size Estimate and Floor Plan (100% done)

Full-chip Transistor-level Schematic (100% done)Full-chip Transistor-level Schematic (100% done)

Component Layout & Simulation (100% done)Component Layout & Simulation (100% done)

Top-Level Layout (100% done)Top-Level Layout (100% done)

Spice simulation of the entire chip (Successful)Spice simulation of the entire chip (Successful) Need to find maximum frequencyNeed to find maximum frequency

Simulation StrategySimulation Strategy Simulate Entire ChipSimulate Entire Chip

Use same inputs from C and Verilog verificationUse same inputs from C and Verilog verification Encryption ensures multiple vectors over critical pathEncryption ensures multiple vectors over critical path Each iteration tests different pattern over critical pathEach iteration tests different pattern over critical path

Each time an iteration is run, SBOX determines new values that will Each time an iteration is run, SBOX determines new values that will initiate critical pathinitiate critical path

Run simulation for 20 clock cyclesRun simulation for 20 clock cycles Will not produce final output but…Will not produce final output but… Values at each node should match VerilogValues at each node should match Verilog

Critical PathCritical Path

000000

00D8D8

DBBC

D8D8DB

BCE73A

ED4F

80FF82

8E80FF

C887

80FB84

8480FF

C68C

80FFC6

8C0905

717

Mux -> Expand -> XOR -> SBOX -> XOR -> Mux

Spice SimulationSpice Simulation

100 MHz simulation

Close UpsClose Ups

340ps 214ps

Problems SimulatingProblems Simulating No DC path to ground errorsNo DC path to ground errors

Loose wiresLoose wires

Quota exceeded errorsQuota exceeded errors Clear /tmpClear /tmp Increase quotaIncrease quota

Simulation file inputs do not increase piecewise linearlySimulation file inputs do not increase piecewise linearly Error in Java sim file generatorError in Java sim file generator

Degredation of Vdd! away from pinDegredation of Vdd! away from pin Modules near vdd! pin work correctlyModules near vdd! pin work correctly Modules further away have a lower vdd! Do not pass full 1.8 volts Modules further away have a lower vdd! Do not pass full 1.8 volts

when PMOS passes vdd signalwhen PMOS passes vdd signal

Vdd! ProblemsVdd! Problems

Simulation of Program Control and ROM using Simulation of Program Control and ROM using vdd! and gnd! wiring from top-levelvdd! and gnd! wiring from top-level

Outputs all very lowOutputs all very low

Actual lengths from top level design

400mV

Vdd! ProblemsVdd! Problems

Simulation of Program Control and ROM Simulation of Program Control and ROM using twice the wiringusing twice the wiring

Output correct with maximum value of 1.5 voltsOutput correct with maximum value of 1.5 volts

Doubling the wiring should halve the resistance

1.5 volts

Vdd! ProblemsVdd! Problems

Simulation of Program Control and ROM using very Simulation of Program Control and ROM using very wide vdd! and ground wireswide vdd! and ground wires

Output correct with maximum value of 1.8 voltsOutput correct with maximum value of 1.8 volts

Extremely low resistance

1.8 volts

Conclusions / SolutionsConclusions / Solutions ConclusionsConclusions

Vdd and Ground are not assumed to be infinite strengthVdd and Ground are not assumed to be infinite strength Vdd strength decreases as distance from pin increasesVdd strength decreases as distance from pin increases

SolutionsSolutions Increase thickness of Vdd and Ground railsIncrease thickness of Vdd and Ground rails Add more Vdd and Ground connectionsAdd more Vdd and Ground connections

StatusStatus Changes were madeChanges were made Simulation successful at 100MHzSimulation successful at 100MHz Need to test higher clock speeds to find maximumNeed to test higher clock speeds to find maximum

QuestionsQuestions

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