1 “Embedded” RAMP Workshop 8/23/06 bee2.eecs.berkeley.edu/wiki/ embedded
“Embedded” RAMP Workshop
Dec 31, 2015
“Embedded” RAMP Workshop. 8/23/06 bee2.eecs.berkeley.edu/wiki/embedded. 100-1000 Core CMPs. RAMP Project. 1-10 Core SoCs. 1M Processor SuperComputers. Schedule:. 10:00-10:15 Introductions, etc. 10:15-11:00 Wawrzynek, Asanovic (UCB) RAMP Vision and Infrastructure - PowerPoint PPT Presentation
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“Embedded” RAMP Workshop
8/23/06bee2.eecs.berkeley.edu/wiki/
embedded
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100-1000 Core100-1000 CoreCMPsCMPs
1M Processor1M ProcessorSuperComputersSuperComputers
1-10 Core1-10 CoreSoCsSoCs
RAMP ProjectRAMP Project
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Schedule:10:00-10:15 Introductions, etc.10:15-11:00 Wawrzynek, Asanovic (UCB)
RAMP Vision and Infrastructure11:00-11:30 Uli Ramacher (Infineon)
Mass Mark Applications Driving MPSoC and Design Challenges11:30-12:00 Ulrich Ruecker (HNI, Paderborn University)
High-level Desc. of Instructions Sets and Compi. Generation12:00-12:30 Wolfgang Raabs (Infineon)
Virtual Prototype and Design Flow12:30-1:30 Lunch1:30-2:00 Kurt Keutzer (UCB)
Mapping task graphs to processors in large multiprocessor systems2:00-2:30 Chen Chang (BEECube)
Hardware and Tools for Architecture Exploration2:30-3:30 Free Discussion
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RAMP Blue Prototype
8 BEE2 modules (32 “user” FPGAs)
8 100MHz. MicroBlaze cores / FPGA = 256 cores
Full star-connection between modules
Diagnostics running today, applications (UPC) this week
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RAMP Blue Prototype - Module in 2u Case
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