Embedded Peripherals IP User Guide · Intel FPGA Avalon Compact Flash Core Revision History.....198 18. EPCS/EPCQA Serial Flash Controller Core ...

Embedded Peripherals IP User Guide

Updated for Intel Quartus Prime Design Suite: 18.1

SubscribeSend Feedback

UG-01085 | 2018.09.24Latest document on the web: PDF | HTML

https://www.intel.com/content/www/us/en/programmable/bin/rssdoc?name=sfo1400787952932mailto:[email protected]?subject=Feedback%20on%20Embedded%20Peripherals%20IP%20User%20Guide%20(UG-01085%202018.09.24)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdfhttps://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html

Contents

1. Embedded Peripherals IP User Guide Introduction....................................................... 191.1. Tool Support....................................................................................................... 191.2. Device Support....................................................................................................201.3. Embedded Peripheral IP User Guide Introduction Revision History...............................20

2. Avalon-ST Multi-Channel Shared Memory FIFO Core..................................................... 222.1. Core Overview.....................................................................................................222.2. Performance and Resource Utilization..................................................................... 222.3. Functional Description.......................................................................................... 23

2.3.1. Interfaces............................................................................................... 242.3.2. Operation............................................................................................... 24

2.4. Parameters......................................................................................................... 252.5. Software Programming Model................................................................................ 26

2.5.1. HAL System Library Support......................................................................262.5.2. Register Map........................................................................................... 26

2.6. Avalon-ST Multi-Channel Shared Memory FIFO Core Revision History.......................... 27

3. Avalon-ST Single-Clock and Dual-Clock FIFO Cores.......................................................283.1. Core Overview.....................................................................................................283.2. Functional Description.......................................................................................... 28

3.2.1. Interfaces............................................................................................... 293.2.2. Operating Modes......................................................................................293.2.3. Fill Level................................................................................................. 303.2.4. Thresholds.............................................................................................. 30

3.3. Parameters......................................................................................................... 313.4. Register Description............................................................................................. 313.5. Avalon-ST Single-Clock and Dual-Clock FIFO Core Revision History............................32

4. Avalon-ST Serial Peripheral Interface Core................................................................... 344.1. Core Overview.....................................................................................................344.2. Functional Description.......................................................................................... 34

4.2.1. Interfaces............................................................................................... 344.2.2. Operation............................................................................................... 354.2.3. Timing....................................................................................................364.2.4. Limitations..............................................................................................36

4.3. Configuration...................................................................................................... 364.4. Avalon-ST Serial Peripheral Interface Core Revision History....................................... 36

5. SPI Core........................................................................................................................375.1. Core Overview.....................................................................................................375.2. Functional Description.......................................................................................... 37

5.2.1. Example Configurations............................................................................ 385.2.2. Transmitter Logic..................................................................................... 395.2.3. Receiver Logic......................................................................................... 395.2.4. Master and Slave Modes........................................................................... 39

5.3. Configuration...................................................................................................... 415.3.1. Master/Slave Settings...............................................................................415.3.2. Data Register Settings..............................................................................42

Contents

Embedded Peripherals IP User Guide Send Feedback

2

mailto:[email protected]?subject=Feedback%20on%20Embedded%20Peripherals%20IP%20User%20Guide%20(UG-01085%202018.09.24)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

5.3.3. Timing Settings....................................................................................... 425.4. Software Programming Model................................................................................ 43

5.4.1. Hardware Access Routines.........................................................................435.4.2. Software Files..........................................................................................445.4.3. Register Map........................................................................................... 45

5.5. SPI Core Revision History......................................................................................48

6. SPI Slave/JTAG to Avalon Master Bridge Cores.............................................................496.1. Core Overview.....................................................................................................496.2. Functional Description.......................................................................................... 496.3. Parameters......................................................................................................... 526.4. SPI Slave/JTAG to Avalon Master Bridge Cores Revision History..................................52

7. Intel eSPI Slave Core.................................................................................................... 537.1. Functional Description.......................................................................................... 54

7.1.1. Link Layer...............................................................................................547.1.2. Transaction Layer.....................................................................................567.1.3. Channel Specific Layer..............................................................................567.1.4. Port80 Implementation............................................................................. 597.1.5. VW message to Physical Port Implementation.............................................. 597.1.6. Avalon-MM Interface Settings.................................................................... 60

7.2. Resource Utilization..............................................................................................617.3. IP Parameters..................................................................................................... 617.4. Interface Signals..................................................................................................627.5. Registers............................................................................................................ 64

7.5.1. Avalon-MM Interface Accessible Registers....................................................647.5.2. eSPI Interface Accessible Registers............................................................ 66

7.6. Peripheral Channel Avalon Interface Use Model........................................................ 697.7. Intel eSPI Slave Core Revision History.................................................................... 70

8. eSPI to LPC Bridge Core................................................................................................718.1. Unsupported LPC Features.................................................................................... 718.2. IP Parameters..................................................................................................... 718.3. Supported IP Clock Frequency............................................................................... 728.4. Functional Description.......................................................................................... 73

8.4.1. FIFO Implementation................................................................................738.4.2. Transaction Ordering Rule......................................................................... 748.4.3. eSPI Command to LPC Cycle Type Conversion..............................................758.4.4. SERIRQ Interrupt Event............................................................................ 75

8.5. Interface Signals..................................................................................................778.6. Registers............................................................................................................ 79

8.6.1. Status Register........................................................................................798.6.2. Error Register..........................................................................................80

8.7. eSPI to LPC Bridge Core Revision History................................................................ 80

9. Ethernet MDIO Core...................................................................................................... 819.1. Core Overview.....................................................................................................819.2. Functional Description.......................................................................................... 81

9.2.1. MDIO Frame Format (Clause 45)................................................................829.2.2. MDIO Clock Generation.............................................................................839.2.3. Interfaces............................................................................................... 839.2.4. Operation............................................................................................... 83

Contents

Send Feedback Embedded Peripherals IP User Guide

3


9.3. Parameter...........................................................................................................849.4. Configuration Registers.........................................................................................849.5. Interface Signals..................................................................................................849.6. Ethernet MDIO Core Revision History......................................................................85

10. Intel FPGA 16550 Compatible UART Core....................................................................8610.1. Core Overview...................................................................................................8610.2. Feature Description............................................................................................ 86

10.2.1. Unsupported Features.............................................................................8710.2.2. Interface...............................................................................................8710.2.3. General Architecture...............................................................................8910.2.4. 16550 UART General Programming Flow Chart........................................... 8910.2.5. Configuration Parameters........................................................................ 9110.2.6. DMA Support......................................................................................... 9110.2.7. FPGA Resource Usage............................................................................. 9210.2.8. Timing and Fmax................................................................................... 9210.2.9. Avalon-MM Slave....................................................................................9310.2.10. Over-run/Under-run Conditions.............................................................. 9410.2.11. Hardware Auto Flow-Control.................................................................. 9510.2.12. Clock and Baud Rate Selection............................................................... 96

10.3. Software Programming Model.............................................................................. 9610.3.1. Overview.............................................................................................. 9610.3.2. Supported Features................................................................................ 9610.3.3. Unsupported Features.............................................................................9710.3.4. Configuration.........................................................................................9710.3.5. 16550 UART API.................................................................................... 9710.3.6. Driver Examples...................................................................................101

10.4. Address Map and Register Descriptions ...............................................................10510.4.1. rbr_thr_dll...........................................................................................10610.4.2. ier_dlh................................................................................................10710.4.3. iir.......................................................................................................10910.4.4. fcr......................................................................................................11010.4.5. lcr...................................................................................................... 11210.4.6. mcr.................................................................................................... 11310.4.7. lsr...................................................................................................... 11410.4.8. msr.................................................................................................... 11610.4.9. scr..................................................................................................... 11810.4.10. afr....................................................................................................11910.4.11. tx_low...............................................................................................120

10.5. Intel FPGA 16550 Compatible UART Core Revision History......................................120

11. UART Core.................................................................................................................12211.1. Core Overview................................................................................................. 12211.2. Functional Description.......................................................................................122

11.2.1. Avalon-MM Slave Interface and Registers.................................................12211.2.2. RS-232 Interface..................................................................................12311.2.3. Transmitter Logic..................................................................................12311.2.4. Receiver Logic......................................................................................12311.2.5. Baud Rate Generation........................................................................... 124

11.3. Instantiating the Core....................................................................................... 12411.3.1. Configuration Settings...........................................................................124

Contents


4


11.4. Software Programming Model.............................................................................12711.4.1. HAL System Library Support.................................................................. 12711.4.2. Software Files...................................................................................... 13111.4.3. Register Map........................................................................................13111.4.4. Interrupt Behavior................................................................................136

11.5. UART Core Revision History............................................................................... 136

12. JTAG UART Core........................................................................................................ 13812.1. Core Overview................................................................................................. 13812.2. Functional Description.......................................................................................138

12.2.1. Avalon Slave Interface and Registers.......................................................13912.2.2. Read and Write FIFOs........................................................................... 13912.2.3. JTAG Interface..................................................................................... 13912.2.4. Host-Target Connection......................................................................... 139

12.3. Configuration...................................................................................................14012.3.1. Configuration Page............................................................................... 140

12.4. Software Programming Model.............................................................................14112.4.1. HAL System Library Support.................................................................. 14112.4.2. Software Files...................................................................................... 14412.4.3. Accessing the JTAG UART Core via a Host PC............................................14412.4.4. Register Map........................................................................................14412.4.5. Interrupt Behavior................................................................................146

12.5. JTAG UART Core Revision History........................................................................147

13. Intel FPGA Avalon Mailbox Core................................................................................14813.1. Core Overview................................................................................................. 14813.2. Functional Description.......................................................................................148

13.2.1. Message Sending and Retrieval Process................................................... 14913.2.2. Component Register Map.......................................................................149

13.3. Interface.........................................................................................................15113.3.1. Component Interface............................................................................ 15113.3.2. Component Parameterization................................................................. 152

13.4. HAL Driver...................................................................................................... 15313.4.1. Feature Description...............................................................................153

13.5. Intel FPGA Avalon Mailbox Core Revision History...................................................158

14. Intel FPGA Avalon Mutex Core.................................................................................. 15914.1. Core Overview................................................................................................. 15914.2. Functional Description.......................................................................................15914.3. Configuration...................................................................................................16014.4. Software Programming Model.............................................................................160

14.4.1. Software Files...................................................................................... 16014.4.2. Hardware Access Routines..................................................................... 161

14.5. Mutex API....................................................................................................... 16114.5.1. altera_avalon_mutex_is_mine()............................................................. 16114.5.2. altera_avalon_mutex_first_lock()........................................................... 16214.5.3. altera_avalon_mutex_lock()...................................................................16214.5.4. altera_avalon_mutex_open()................................................................. 16214.5.5. altera_avalon_mutex_trylock()...............................................................16314.5.6. altera_avalon_mutex_unlock()............................................................... 163

14.6. Intel FPGA Avalon Mutex Core Revision History.....................................................163

Contents


5


15. Intel FPGA Avalon I2C (Master) Core........................................................................ 16415.1. Core Overview................................................................................................. 16415.2. Feature Description.......................................................................................... 164

15.2.1. Supported Features.............................................................................. 16415.2.2. Unsupported Features........................................................................... 164

15.3. Configuration Parameters.................................................................................. 16415.4. Interface.........................................................................................................16515.5. Registers.........................................................................................................166

15.5.1. Register Memory Map........................................................................... 16615.5.2. Register Descriptions............................................................................ 167

15.6. Reset and Clock Requirements........................................................................... 17115.7. Functional Description.......................................................................................171

15.7.1. Overview.............................................................................................17115.7.2. Configuring TFT_CMD Register Examples................................................. 17215.7.3. I2C Serial Interface Connection.............................................................. 17315.7.4. Avalon-MM Slave Interface.................................................................... 17415.7.5. Avalon-ST Interface.............................................................................. 17515.7.6. Programming Model..............................................................................175

15.8. Intel FPGA Avalon I2C (Master) Core API..............................................................17815.8.1. Optional Status Retrieval API................................................................. 181

15.9. Intel FPGA Avalon I2C (Master) Core Revision History............................................ 182

16. Intel FPGA I2C Slave to Avalon-MM Master Bridge Core............................................ 18416.1. Core Overview................................................................................................. 18416.2. Functional Description.......................................................................................184

16.2.1. Block Diagram..................................................................................... 18416.2.2. N-byte Addressing................................................................................ 18416.2.3. N-byte Addressing with N-bit Address Stealing......................................... 18516.2.4. Read Operation.................................................................................... 18616.2.5. Write Operation....................................................................................18716.2.6. Interacting with Multi-Master................................................................. 189

16.3. Platform Designer Parameters............................................................................ 19016.4. Signals........................................................................................................... 19016.5. How to Translate the Bridge's I2C Data and I2C I/O Ports to an I2C Interface............ 19216.6. Intel FPGA I2C Slave to Avalon-MM Master Bridge Core Revision History...................193

17. Intel FPGA Avalon Compact Flash Core..................................................................... 19417.1. Core Overview................................................................................................. 19417.2. Functional Description.......................................................................................19417.3. Required Connections....................................................................................... 19517.4. Software Programming Model.............................................................................196

17.4.1. HAL System Library Support.................................................................. 19617.4.2. Software Files...................................................................................... 19617.4.3. Register Maps...................................................................................... 197

17.5. Intel FPGA Avalon Compact Flash Core Revision History.........................................198

18. EPCS/EPCQA Serial Flash Controller Core................................................................. 19918.1. Core Overview................................................................................................. 19918.2. Functional Description.......................................................................................200

18.2.1. Avalon-MM Slave Interface and Registers.................................................20218.3. Configuration................................................................................................ 202

Contents


6


18.4. Interface Signals.............................................................................................. 20318.5. Software Programming Model.............................................................................203

18.5.1. HAL System Library Support.................................................................. 20418.5.2. Software Files...................................................................................... 204

18.6. Driver API....................................................................................................... 20418.7. EPCS/EPCQA Serial Flash Controller Core Revision History .....................................206

19. Intel FPGA Serial Flash Controller Core..................................................................... 20719.1. Parameters......................................................................................................207

19.1.1. Configuration Device Types.................................................................... 20719.1.2. I/O Mode.............................................................................................20819.1.3. Chip Selects.........................................................................................20819.1.4. Interface Signals.................................................................................. 208

19.2. Registers.........................................................................................................21019.2.1. Register Memory Map........................................................................... 21019.2.2. Register Descriptions............................................................................ 211

19.3. Nios II Tools Support........................................................................................ 21519.3.1. Booting Nios II from Flash..................................................................... 21519.3.2. Nios II HAL Driver................................................................................ 217

19.4. Driver API....................................................................................................... 21819.5. Intel FPGA Serial Flash Controller Core Revision History.........................................220

20. Intel FPGA Serial Flash Controller II Core................................................................. 22120.1. Parameters......................................................................................................221



20.3. Nios II Tools Support........................................................................................ 22920.3.1. Booting Nios II from Flash..................................................................... 22920.3.2. Nios II HAL Driver................................................................................ 232

20.4. Driver API....................................................................................................... 23220.5. Intel FPGA Serial Flash Controller II Core Revision History..................................... 234

21. Intel FPGA Generic QUAD SPI Controller Core...........................................................23521.1. Parameters......................................................................................................235



21.3. Nios II Tools Support........................................................................................ 24321.3.1. Nios II HAL Driver................................................................................ 243

21.4. Driver API....................................................................................................... 24421.5. Intel FPGA Generic QUAD SPI Controller Core Revision History............................... 246

Contents


7


22. Intel FPGA Generic QUAD SPI Controller II Core.......................................................24722.1. Parameters......................................................................................................247

22.1.1. Configuration Device Types ................................................................... 24722.1.2. I/O Mode.............................................................................................24822.1.3. Chip Selects.........................................................................................24822.1.4. Interface Signals.................................................................................. 248


22.3. Nios II Tools Support........................................................................................ 25522.3.1. Nios II HAL Driver................................................................................ 255

22.4. Driver API....................................................................................................... 25622.5. Intel FPGA Generic QUAD SPI Controller II Core Revision History............................ 257

23. Interval Timer Core...................................................................................................25823.1. Core Overview................................................................................................. 25823.2. Functional Description.......................................................................................258

23.2.1. Avalon-MM Slave Interface.................................................................... 25923.3. Configuration...................................................................................................259

23.3.1. Timeout Period.....................................................................................25923.3.2. Counter Size........................................................................................26023.3.3. Hardware Options.................................................................................26023.3.4. Configuring the Timer as a Watchdog Timer............................................. 261


23.5. Interval Time Core API......................................................................................26523.6. Interval Timer Core Revision History................................................................... 266

24. On-Chip FIFO Memory Core.......................................................................................26724.1. Core Overview................................................................................................. 26724.2. Functional Description.......................................................................................267

24.2.1. Avalon-MM Write Slave to Avalon-MM Read Slave......................................26724.2.2. Avalon-ST Sink to Avalon-ST Source....................................................... 26824.2.3. Avalon-MM Write Slave to Avalon-ST Source.............................................26924.2.4. Avalon-ST Sink to Avalon-MM Read Slave................................................ 27124.2.5. Status Interface................................................................................... 27224.2.6. Clocking Modes.................................................................................... 272

24.3. Configuration...................................................................................................27224.3.1. FIFO Settings.......................................................................................27224.3.2. Interface Parameters............................................................................ 27224.3.3. Interface Signals.................................................................................. 273

24.4. Software Programming Model.............................................................................27524.4.1. HAL System Library Support.................................................................. 27524.4.2. Software Files...................................................................................... 275

24.5. Programming with the On-Chip FIFO Memory.......................................................27624.5.1. Software Control.................................................................................. 27624.5.2. Software Example................................................................................ 279

24.6. On-Chip FIFO Memory API.................................................................................280

Contents


8


24.6.1. altera_avalon_fifo_init()........................................................................ 28024.6.2. altera_avalon_fifo_read_status()............................................................ 28024.6.3. altera_avalon_fifo_read_ienable()...........................................................28024.6.4. altera_avalon_fifo_read_almostfull()....................................................... 28124.6.5. altera_avalon_fifo_read_almostempty()...................................................28124.6.6. altera_avalon_fifo_read_event().............................................................28124.6.7. altera_avalon_fifo_read_level().............................................................. 28124.6.8. altera_avalon_fifo_clear_event()............................................................ 28224.6.9. altera_avalon_fifo_write_ienable()..........................................................28224.6.10. altera_avalon_fifo_write_almostfull().....................................................28224.6.11. altera_avalon_fifo_write_almostempty()................................................ 28324.6.12. altera_avalon_write_fifo()....................................................................28324.6.13. altera_avalon_write_other_info().......................................................... 28324.6.14. altera_avalon_fifo_read_fifo().............................................................. 28424.6.15. altera_avalon_fifo_read_other_info().....................................................284

24.7. On-Chip FIFO Memory Core Revision History........................................................ 284

25. On-Chip Memory (RAM and ROM) Core......................................................................28525.1. Core Overview................................................................................................. 28525.2. Component-Level Design for On-Chip Memory......................................................285

25.2.1. Memory Type....................................................................................... 28525.2.2. Size....................................................................................................28625.2.3. Read Latency.......................................................................................28625.2.4. ROM/RAM Memory Protection.................................................................28725.2.5. ECC Parameter.....................................................................................28725.2.6. Memory Initialization............................................................................ 287

25.3. Platform Designer System-Level Design for On-Chip Memory................................. 28725.4. Simulation for On-Chip Memory..........................................................................28725.5. Intel Quartus Prime Project-Level Design for On-Chip Memory................................28825.6. Board-Level Design for On-Chip Memory............................................................. 28825.7. Example Design with On-Chip Memory................................................................ 28825.8. On-Chip Memory (RAM and ROM) Core Revision History........................................ 288

26. Optrex 16207 LCD Controller Core............................................................................ 29026.1. Core Overview................................................................................................. 29026.2. Functional Description.......................................................................................29026.3. Software Programming Model.............................................................................291

26.3.1. HAL System Library Support.................................................................. 29126.3.2. Displaying Characters on the LCD........................................................... 29126.3.3. Software Files...................................................................................... 29226.3.4. Register Map........................................................................................29226.3.5. Interrupt Behavior................................................................................292

26.4. Optrex 16207 LCD Controller Core Revision History...............................................293

27. PIO Core................................................................................................................... 29427.1. Core Overview................................................................................................. 29427.2. Functional Description.......................................................................................294

27.2.1. Data Input and Output.......................................................................... 29527.2.2. Edge Capture.......................................................................................29527.2.3. IRQ Generation.................................................................................... 295

27.3. Example Configurations.....................................................................................29627.3.1. Avalon-MM Interface.............................................................................296

Contents


9


27.4. Configuration...................................................................................................29627.4.1. Basic Settings...................................................................................... 29627.4.2. Input Options.......................................................................................29727.4.3. Simulation...........................................................................................298

27.5. Software Programming Model.............................................................................29827.5.1. Software Files...................................................................................... 29827.5.2. Register Map........................................................................................29827.5.3. Interrupt Behavior................................................................................30027.5.4. Software Files...................................................................................... 300

27.6. PIO Core Revision History..................................................................................301

28. PLL Cores.................................................................................................................. 30228.1. Core Overview................................................................................................. 30228.2. Functional Description.......................................................................................303

28.2.1. ALTPLL IP Core.....................................................................................30328.2.2. Clock Outputs...................................................................................... 30328.2.3. PLL Status and Control Signals............................................................... 30428.2.4. System Reset Considerations................................................................. 304

28.3. Instantiating the Avalon ALTPLL Core.................................................................. 30428.4. Instantiating the PLL Core................................................................................. 30428.5. Hardware Simulation Considerations................................................................... 30528.6. Register Definitions and Bit List.......................................................................... 306

28.6.1. Status Register.................................................................................... 30628.6.2. Control Register................................................................................... 30628.6.3. Phase Reconfig Control Register............................................................. 307

28.7. PLL Cores Revision History.................................................................................308

29. DMA Controller Core..................................................................................................30929.1. Core Overview................................................................................................. 30929.2. Functional Description.......................................................................................309

29.2.1. Setting Up DMA Transactions..................................................................31029.2.2. The Master Read and Write Ports............................................................ 31129.2.3. Addressing and Address Incrementing.....................................................311

29.3. Parameters......................................................................................................31229.3.1. DMA Parameters (Basic)........................................................................31229.3.2. Advanced Options.................................................................................313


29.5. DMA Controller Core Revision History.................................................................. 318

30. Modular Scatter-Gather DMA Core.............................................................................31930.1. Core Overview................................................................................................. 31930.2. Feature Description.......................................................................................... 31930.3. mSGDMA Interfaces and Parameters...................................................................321

30.3.1. Interface............................................................................................. 32130.3.2. mSGDMA Parameter Editor.................................................................... 325

30.4. mSGDMA Descriptors........................................................................................32530.4.1. Read and Write Address Fields................................................................32630.4.2. Length Field.........................................................................................326

Contents


10


30.4.3. Sequence Number Field.........................................................................32630.4.4. Read and Write Burst Count Fields.......................................................... 32730.4.5. Read and Write Stride Fields.................................................................. 32730.4.6. Control Field........................................................................................ 327

30.5. Register Map of mSGDMA..................................................................................32930.5.1. Status Register.................................................................................... 32930.5.2. Control Register................................................................................... 33030.5.3. Write Fill Level Register......................................................................... 33230.5.4. Read Fill Level Register......................................................................... 33230.5.5. Response Fill Level Register................................................................... 33230.5.6. Write Sequence Number Register............................................................33230.5.7. Read Sequence Number Register............................................................ 33230.5.8. Component Configuration 1 Register....................................................... 33230.5.9. Component Configuration 2 Register....................................................... 33430.5.10. Component Type Register.................................................................... 33430.5.11. Component Version Register.................................................................335

30.6. Programming Model..........................................................................................33530.6.1. Stop DMA Operation............................................................................. 33530.6.2. Stop Descriptor Operation..................................................................... 33530.6.3. Recovery from Stopped on Error and Stopped on Early Termination.............336

30.7. Modular Scatter-Gather DMA Prefetcher Core....................................................... 33730.7.1. Functional Description...........................................................................337

30.8. Driver Implementation...................................................................................... 35030.8.1. alt_msgdma_standard_descriptor_async_transfer.....................................35030.8.2. alt_msgdma_extended_descriptor_async_transfer.................................... 35130.8.3. alt_msgdma_descriptor_async_transfer...................................................35230.8.4. alt_msgdma_standard_descriptor_sync_transfer...................................... 35330.8.5. alt_msgdma_extended_descriptor_sync_transfer......................................35430.8.6. alt_msgdma_descriptor_sync_transfer.................................................... 35530.8.7. alt_msgdma_construct_standard_st_to_mm_descriptor.............................35630.8.8. alt_msgdma_construct_standard_mm_to_st_descriptor.............................35730.8.9. alt_msgdma_construct_standard_mm_to_mm_descriptor..........................35830.8.10. alt_msgdma_construct_standard_descriptor...........................................35930.8.11. alt_msgdma_construct_extended_st_to_mm_descriptor.......................... 36030.8.12. alt_msgdma_construct_extended_mm_to_st_descriptor.......................... 36130.8.13. alt_msgdma_construct_extended_mm_to_mm_descriptor....................... 36230.8.14. alt_msgdma_construct_extended_descriptor.......................................... 36330.8.15. alt_msgdma_register_callback..............................................................36430.8.16. alt_msgdma_open.............................................................................. 36530.8.17. alt_msgdma_write_standard_descriptor.................................................36630.8.18. alt_msgdma_write_extended_descriptor................................................36730.8.19. alt_avalon_msgdma_init......................................................................36830.8.20. alt_msgdma_irq................................................................................. 368

30.9. Example Code Using mSGDMA Core....................................................................36830.10. Modular Scatter-Gather DMA Core Revision History............................................. 371

31. Scatter-Gather DMA Controller Core..........................................................................37231.1. Core Overview................................................................................................. 372

31.1.1. Example Systems................................................................................. 37231.1.2. Comparison of SG-DMA Controller Core and DMA Controller Core................374

31.2. Resource Usage and Performance....................................................................... 374

Contents


11


31.3. Functional Description.......................................................................................37431.3.1. Functional Blocks and Configurations.......................................................37531.3.2. DMA Descriptors...................................................................................37731.3.3. Error Conditions................................................................................... 379

31.4. Parameters......................................................................................................38131.5. Simulation Considerations................................................................................. 38131.6. Software Programming Model.............................................................................381

31.6.1. HAL System Library Support.................................................................. 38131.6.2. Software Files...................................................................................... 38231.6.3. Register Maps...................................................................................... 38231.6.4. DMA Descriptors...................................................................................38431.6.5. Timeouts.............................................................................................386

31.7. Programming with SG-DMA Controller................................................................. 38631.7.1. Data Structure..................................................................................... 38631.7.2. SG-DMA API........................................................................................ 38731.7.3. alt_avalon_sgdma_do_async_transfer().................................................. 38731.7.4. alt_avalon_sgdma_do_sync_transfer().................................................... 38831.7.5. alt_avalon_sgdma_construct_mem_to_mem_desc()................................. 38831.7.6. alt_avalon_sgdma_construct_stream_to_mem_desc()...............................38931.7.7. alt_avalon_sgdma_construct_mem_to_stream_desc()...............................38931.7.8. alt_avalon_sgdma_enable_desc_poll().................................................... 39031.7.9. alt_avalon_sgdma_disable_desc_poll()....................................................39031.7.10. alt_avalon_sgdma_check_descriptor_status().........................................39031.7.11. alt_avalon_sgdma_register_callback()...................................................39131.7.12. alt_avalon_sgdma_start()....................................................................39131.7.13. alt_avalon_sgdma_stop().................................................................... 39131.7.14. alt_avalon_sgdma_open()....................................................................392

31.8. Scatter-Gather DMA Controller Core Revision History............................................ 392

32. SDRAM Controller Core............................................................................................. 39432.1. Core Overview................................................................................................. 39432.2. Functional Description.......................................................................................394

32.2.1. Avalon-MM Interface.............................................................................39532.2.2. Off-Chip SDRAM Interface......................................................................39532.2.3. Board Layout and Pinout Considerations.................................................. 39732.2.4. Performance Considerations...................................................................397

32.3. Configuration...................................................................................................39832.3.1. Memory Profile Page............................................................................. 39832.3.2. Timing Page.........................................................................................400

32.4. Hardware Simulation Considerations................................................................... 40032.4.1. SDRAM Controller Simulation Model........................................................ 40132.4.2. SDRAM Memory Model.......................................................................... 401

32.5. Example Configurations.....................................................................................40132.6. Software Programming Model.............................................................................40332.7. Clock, PLL and Timing Considerations..................................................................403

32.7.1. Factors Affecting SDRAM Timing............................................................. 40332.7.2. Symptoms of an Untuned PLL................................................................ 40432.7.3. Estimating the Valid Signal Window.........................................................40432.7.4. Example Calculation..............................................................................405

32.8. SDRAM Controller Core Revision History ............................................................. 407

Contents


12


33. Tri-State SDRAM Core............................................................................................... 40933.1. Core Overview................................................................................................. 40933.2. Feature Description.......................................................................................... 409

33.2.1. Block Diagram..................................................................................... 41033.3. Configuration Parameter....................................................................................410

33.3.1. Memory Profile Page............................................................................. 41033.3.2. Timing Page.........................................................................................410

33.4. Interface.........................................................................................................41133.5. Reset and Clock Requirements........................................................................... 41433.6. Architecture.....................................................................................................414

33.6.1. Avalon-MM Slave Interface and CSR........................................................41433.6.2. Block Level Usage Model........................................................................415

33.7. Intel SDRAM Tri-State Controller Core Revision History.......................................... 415

34. Video Sync Generator and Pixel Converter Cores...................................................... 41634.1. Core Overview................................................................................................. 41634.2. Video Sync Generator....................................................................................... 416

34.2.1. Functional Description...........................................................................41634.2.2. Parameters..........................................................................................41734.2.3. Signals................................................................................................41834.2.4. Timing Diagrams.................................................................................. 418

34.3. Pixel Converter................................................................................................ 41934.3.1. Functional Description...........................................................................41934.3.2. Parameters..........................................................................................42034.3.3. Signals................................................................................................420

34.4. Hardware Simulation Considerations................................................................... 42034.5. Video Sync Generator and Pixel Converter Cores Revision History........................... 420

35. Intel FPGA Interrupt Latency Counter Core...............................................................42235.1. Core Overview................................................................................................. 42235.2. Feature Description.......................................................................................... 422

35.2.1. Avalon-MM Compliant CSR Registers....................................................... 42335.2.2. 32-bit Counter..................................................................................... 42535.2.3. Interrupt Detector................................................................................ 425

35.3. Component Interface........................................................................................ 42535.4. Component Parameterization............................................................................. 42635.5. Software Access...............................................................................................426

35.5.1. Routine for Level Sensitive Interrupts......................................................42635.5.2. Routine for Edge/Pulse Sensitive Interrupts..............................................426

35.6. Implementation Details..................................................................................... 42735.6.1. Interrupt Latency Counter Architecture....................................................427

35.7. IP Caveats.......................................................................................................42835.8. Intel FPGA Interrupt Latency Counter Core Revision History................................... 428

36. Performance Counter Unit Core.................................................................................42936.1. Core Overview................................................................................................. 42936.2. Functional Description.......................................................................................429

36.2.1. Section Counters..................................................................................42936.2.2. Global Counter.....................................................................................43036.2.3. Register Map........................................................................................43036.2.4. System Reset.......................................................................................431

Contents


13


36.3. Configuration...................................................................................................43136.3.1. Define Counters................................................................................... 43136.3.2. Multiple Clock Domain Considerations......................................................431

36.4. Hardware Simulation Considerations................................................................... 43136.5. Software Programming Model.............................................................................431

36.5.1. Software Files...................................................................................... 43136.5.2. Using the Performance Counter.............................................................. 43136.5.3. Interrupt Behavior................................................................................433

36.6. Performance Counter API.................................................................................. 43436.6.1. PERF_RESET()..................................................................................... 43436.6.2. PERF_START_MEASURING()...................................................................43436.6.3. PERF_STOP_MEASURING().................................................................... 43436.6.4. PERF_BEGIN()..................................................................................... 43536.6.5. PERF_END()........................................................................................ 43536.6.6. perf_print_formatted_report()................................................................43536.6.7. perf_get_total_time()........................................................................... 43636.6.8. perf_get_section_time()........................................................................43636.6.9. perf_get_num_starts()..........................................................................43636.6.10. alt_get_cpu_freq()..............................................................................437

36.7. Performance Counter Core Revision History..........................................................437

37. Vectored Interrupt Controller Core........................................................................... 43837.1. Core Overview................................................................................................. 43837.2. Functional Description.......................................................................................440

37.2.1. External Interfaces............................................................................... 44037.2.2. Functional Blocks..................................................................................44137.2.3. Daisy Chaining VIC Cores...................................................................... 44337.2.4. Latency Information..............................................................................443

37.3. Register Maps.................................................................................................. 44437.4. Parameters......................................................................................................44837.5. Intel FPGA HAL Software Programming Model.......................................................449

37.5.1. Software Files...................................................................................... 44937.5.2. Macros................................................................................................44937.5.3. Data Structure..................................................................................... 45037.5.4. VIC API...............................................................................................45037.5.5. Run-time Initialization...........................................................................45237.5.6. Board Support Package......................................................................... 452

37.6. Implementing the VIC in Platform Designer..........................................................45837.6.1. Adding VIC Hardware............................................................................45837.6.2. Software for VIC.................................................................................. 463

37.7. Example Designs..............................................................................................46537.7.1. Example Description............................................................................. 46537.7.2. Example Usage.................................................................................... 46737.7.3. Software Description.............................................................................46737.7.4. Positioning the ISR in Vector Table.......................................................... 46937.7.5. Latency Measurement with the Performance Counter.................................470

37.8. Advanced Topics...............................................................................................47137.8.1. Real Time Latency Concerns.................................................................. 47137.8.2. Software Interrupt................................................................................475

37.9. Vectored Interrupt Controller Core Revision History...............................................476

Contents


14


38. Avalon-ST Data Pattern Generator and Checker Cores.............................................. 47738.1. Core Overview................................................................................................. 47738.2. Data Pattern Generator..................................................................................... 477

38.2.1. Functional Description...........................................................................47738.2.2. Configuration.......................................................................................479

38.3. Data Pattern Checker........................................................................................47938.3.1. Functional Description...........................................................................47938.3.2. Configuration.......................................................................................481


38.5.1. Register Maps...................................................................................... 48238.6. Avalon-ST Data Pattern Generator and Checker Cores Revision History.................... 486

39. Avalon-ST Test Pattern Generator and Checker Cores...............................................48739.1. Core Overview................................................................................................. 48739.2. Resource Utilization and Performance..................................................................48739.3. Test Pattern Generator...................................................................................... 488

39.3.1. Functional Description...........................................................................48839.3.2. Configuration.......................................................................................489

39.4. Test Pattern Checker.........................................................................................49039.4.1. Functional Description...........................................................................49039.4.2. Configuration.......................................................................................491


39.6.1. HAL System Library Support.................................................................. 49239.6.2. Software Files...................................................................................... 49239.6.3. Register Maps...................................................................................... 492

39.7. Test Pattern Generator API................................................................................ 49639.7.1. data_source_reset()............................................................................. 49639.7.2. data_source_init()................................................................................ 49639.7.3. data_source_get_id()............................................................................49739.7.4. data_source_get_supports_packets()......................................................49739.7.5. data_source_get_num_channels().......................................................... 49739.7.6. data_source_get_symbols_per_cycle()....................................................49739.7.7. data_source_set_enable()..................................................................... 49839.7.8. data_source_get_enable()..................................................................... 49839.7.9. data_source_set_throttle().................................................................... 49839.7.10. data_source_get_throttle().................................................................. 49839.7.11. data_source_is_busy()........................................................................ 49939.7.12. data_source_fill_level()....................................................................... 49939.7.13. data_source_send_data().................................................................... 499

39.8. Test Pattern Checker API................................................................................... 50039.8.1. data_sink_reset().................................................................................50039.8.2. data_sink_init()....................................................................................50039.8.3. data_sink_get_id()............................................................................... 50039.8.4. data_sink_get_supports_packets()......................................................... 50039.8.5. data_sink_get_num_channels()..............................................................50139.8.6. data_sink_get_symbols_per_cycle()....................................................... 50139.8.7. data_sink_set enable()..........................................................................50139.8.8. data_sink_get_enable().........................................................................501

Contents


15


39.8.9. data_sink_set_throttle()........................................................................50239.8.10. data_sink_get_throttle()......................................................................50239.8.11. data_sink_get_packet_count()............................................................. 50239.8.12. data_sink_get_symbol_count().............................................................50239.8.13. data_sink_get_error_count()................................................................50339.8.14. data_sink_get_exception()...................................................................50339.8.15. data_sink_exception_is_exception()......................................................50339.8.16. data_sink_exception_has_data_error()..................................................50339.8.17. data_sink_exception_has_missing_sop()............................................... 50439.8.18. data_sink_exception_has_missing_eop()............................................... 50439.8.19. data_sink_exception_signalled_error().................................................. 50439.8.20. data_sink_exception_channel()............................................................ 504

39.9. Avalon-ST Test Pattern Generator and Checker Cores Revision History..................... 505

40. System ID Peripheral Core........................................................................................ 50640.1. Core Overview................................................................................................. 50640.2. Functional Description.......................................................................................50640.3. Configuration...................................................................................................50740.4. Software Programming Model.............................................................................507

40.4.1. alt_avalon_sysid_test()......................................................................... 50840.5. System ID Core Revision History........................................................................ 508

41. Avalon Packets to Transactions Converter Core........................................................ 50941.1. Core Overview................................................................................................. 50941.2. Functional Description.......................................................................................509

41.2.1. Interfaces............................................................................................50941.2.2. Operation............................................................................................510

41.3. Avalon Packets to Transactions Converter Core Revision History..............................511

42. Avalon-ST Multiplexer and Demultiplexer Cores........................................................51342.1. Core Overview................................................................................................. 513

42.1.1. Resource Usage and Performance........................................................... 51342.2. Multiplexer...................................................................................................... 514

42.2.1. Functional Description...........................................................................51442.2.2. Parameters..........................................................................................515

42.3. Demultiplexer.................................................................................................. 51642.3.1. Functional Description...........................................................................51642.3.2. Parameters..........................................................................................517

42.4. Hardware Simulation Considerations................................................................... 51842.5. Software Programming Model.............................................................................51842.6. Avalon-ST Multiplexer and Demultiplexer Cores Revision History............................. 518

43. Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores........................... 52043.1. Core Overview................................................................................................. 52043.2. Functional Description.......................................................................................520

43.2.1. Interfaces............................................................................................52143.2.2. OperationAvalon-ST Bytes to Packets Converter Core..............................52143.2.3. OperationAvalon-ST Packets to Bytes Converter Core..............................522

43.3. Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores Revision History... 522

44. Avalon-ST Delay Core................................................................................................52444.1. Core Overview................................................................................................. 524

Contents


16


44.2. Functional Description.......................................................................................52444.2.1. Reset..................................................................................................52444.2.2. Interfaces............................................................................................525

44.3. Parameters......................................................................................................52544.4. Avalon-ST Delay Core Revision History................................................................ 526

45. Avalon-ST Round Robin Scheduler Core.................................................................... 52745.1. Core Overview................................................................................................. 52745.2. Performance and Resource Utilization..................................................................52745.3. Functional Description.......................................................................................528

45.3.1. Interfaces............................................................................................52845.3.2. Operations...........................................................................................529

45.4. Parameters......................................................................................................53045.5. Avalon-ST Round Robin Scheduler Core Revision History........................................530

46. Avalon-ST Splitter Core.............................................................................................53146.1. Core Overview................................................................................................. 53146.2. Functional Description.......................................................................................531

46.2.1. Backpressure.......................................................................................53146.2.2. Interfaces............................................................................................532

46.3. Parameters......................................................................................................53246.4. Avalon-ST Splitter Core Revision History..............................................................533

47. Avalon-MM DDR Memory Half Rate Bridge Core........................................................ 53547.1. Core Overview................................................................................................. 53547.2. Resource Usage and Performance....................................................................... 53647.3. Functional Description...............

Embedded Peripherals IP User Guide · Intel FPGA Avalon Compact Flash Core Revision History.....198 18. EPCS/EPCQA Serial Flash Controller Core ...

Documents