Embedded MRAM Technology For logic VLSI …For logic VLSI Application 1 Work supported by the FIRST program of JSPS. Existing Embedded Memory Market 2 WW Market @ 2010 MOS Micro 61B

Naoki Kasai1, Shoji Ikeda1,2, Takahiro Hanyu1,3, Tetsuo Endoh1,4, and Hideo Ohno1,2

1Center for Spintronics Integrated Systems, Tohoku University, JAPAN

2Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, JAPAN

3Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku University, JAPAN

4Center for Interdisciplinary Research, Tohoku University, JAPAN

http://www.csis.tohoku.ac.jp/

November 7, 2011

2011 11th Non-Volatile Memory Technology Symposium

Embedded MRAM Technology For logic VLSI Application

1 Work supported by the FIRST program of JSPS.

Existing Embedded Memory Market

2

WW Market @ 2010

MOS Micro 61B (US$)

MOS Logic 77B (US$)

Applications Micro-processor (PC, Server, …)

Micro-computer (4-32 bit MCUs)

ASIC, ASSP, FPGA (Mobile, Graphic, …)

Embedded Memory

SRAM L1-L3 cash SRAM NOR-Flash

SRAM DRAM

Requirements Ultra high speed RAM Large capacity RAM

High speed RAM Large capacity NVM

High speed RAM Large capacity RAM Wide band width RAM

Scaling Issues

Operation margin (Vth variation) Cell size scaling

Cell size scaling Reliable NVM

Cell size scaling Low operation power Low standby power

Key challenge Low Power Voltage scaling

Wide temp. range Low cost

Voltage scaling Low cost

World Semiconductor Trade Statistics

3

Trade-off relation between “performance” and “cost”

10M

100M

1G

100 50 10 5 Cell Area Factor, a ( a =cell area/F 2 )

Rea

d C

lock

Fre

quen

cy (H

z)

High-speed eSRAM

eSRAM

SRAM

eDRAM

EEPROM NOR Flash

NAND Flash

eFLASH DRAM

MRAM, FRAM

Low Cost

Hig

h P

erfo

rman

ce

Logic

eSRAM

MPU, ASIC ...

Graphics …

Wide Bandwidth Low Power Large Capacity

High Speed RAM Logic Compatibility

• Low Voltage • Design

Logi

c MCU

eDRAM

Logic

eSRAM

eFlash

High Speed NVM Various Application

• Wide Temp. Range • High Reliability

Memory Portfolio

Alternative eMRAM

4

10M

100M

1G

100 50 10 5 Cell Area Factor, a ( a =cell area/F ) 2

Rea

d C

lock

Fre

quen

cy (H

z)

High-speed eSRAM

eSRAM

SRAM

eDRAM

EEPROM NOR Flash

NAND Flash

eFLASH DRAM

MRAM, FRAM

Low Cost

Hig

h P

erfo

rman

ce

No universal embedded MRAM, but some types of MRAMs must be suitable for embedded applications.

High speed eMRAM

High density eMRAM

Embedded MRAM Issues

5

Standard CMOS Process compatible Suitable memory cell structure Number of cell components; MTJ, transistor, wiring Data write scheme; Magnetic Field, STT, ….

MTJ: Magnetic Tunnel Junction MR ratio Magnetic anisotropy; Materials of stacked thin magnetic layers and tunnel barrier film

Free Layer Tunnel Barrier Fixed Layer

in-plane anisotropy

perpendicular anisotropy

Free Layer Tunnel Barrier Fixed Layer

CMOS Process Compatible

6

Standard CMOS Logic

MTJs formed in back-end of line, BEOL CMOS characteristics unchanged No Yoke (magnetic clad) lines Cu & low-k interconnect applicable 350 ºC thermal stability in BEOL fabrication process MTJ

Spintronics CMOS Logic

MTJ Formation

Typical MRAM Cells

7

MTJ

No Transistor 0Tr + 1MTJ

One Transistor 1Tr + 1MTJ

Two Transistors 2Tr + 1MTJ

Magnetic Field

induced by write current through metal wires

Domain Wall Motion (DWM)

by current through free layer

write word-line

Write bit-line

Spin Transfer Torque (STT) by current through MTJ

Cell Type Data Write Scheme

Domain Wall

MTJ MTJ

MTJ

MTJ

half-selected cell

unselected cell

selected cell

unselected cell

selected cell

Current

Prob

abili

ty Read

Write

Barrier Breakdown

High Density eMRAM Cell

8

Simple cell structure without snake path Random access read/write in cell array Scalable MTJ size & write current Large magneto-resistance(MR) ratio BEOL process temperature 350 ºC Reliability Low tunnel current density Non-volatality Δ=E/k BT

0Tr + 1MTJ 1Tr + 1MTJ 2Tr + 1MTJ

Magnetic Field STT

DWM

In plane Perpendicular

Al2O5

MgO

MgO

Requirements Choices

CoFeB/MgO/CoFeB MTJ

9

S. Ikeda et. al., Appl. Phys. Lett. 93, 082508 (2008).

0

100

200

300

400

500

600

700

1994 1996 1998 2000 2002 2004 2006 2008 2010

トンネル

磁気抵抗比

(%)

年

AlOx-barrier MTJs

CanonANELVA & AIST

AIST

Tohoku Univ. & Hitachi

604%@RT(1144%@5K)

IBMAIST

AIST

TMR

rati

o (%

)Tohoku Univ.

MgO-barrier MTJs

Year

CoFeB

MgO

CoFeB

bcc (001) rock salt (001) bcc(001)

SiO2/Si sub.

Ta(5) Ru(10) Ta(5)

CoFeB(5 ) →

MgO(2.1) CoFeB(6) →

Ta(5) Ru (5) Cr/Au

In-plane anisotropy pseudo-SV

Large MR Ratio

Dependence of tCoFeB on Anisotropy

10

Ikeda et al., Nat. Mat., 9 (2010) pp.721-724

-1

0

1

-0.5 0.0 0.5 1.0

-1

0

1

tCoFeB = 2.0 nm

in-plane out-of-plane

M (

T)

tCoFeB = 1.3 nm

µ0H (T)

In-plane anisotropy

Perpendicular anisotropy

Ta=300oC

Ta=300oC

CoFeB(tCoFeB ) MgO(1)

SiO2/Si sub. Ta(5)

Ru(10) Ta(5)

m0Hs_in-plane = 0.34 T Ms = 1.58 T K = 2.1x105 J/m3

Ta=300 oC, 4 kOe, 1h

Perpendicular Anisotropy

CoFeB/MgO/CoFeB MTJ

11

Perpendicular Anisotropy

Ikeda et al., Nat. Mat., 9 (2010) pp.721-724

SiO2/Si sub.

Ta(5)Ru(10)Ta(5)

CoFeB(0.9 )

MgO(0.9)CoFeB(1.5 )

Ta(5)Ru (5)Cr/Au

Al2O3

V-

V+

(nm)

40 nm

-0.2 -0.1 0.0 0.1 0.210

20

30

40

50

R (kΩ

)µ0H (T)

Parallel

Antiparallel

Spin Transfer Torque switching

12

Ikeda et al., Nat. Mat., 9 (2010) pp.721-724

CoFeB/MgO/CoFeB MTJ

-0.2 -0.1 0.0 0.1 0.210

20

30

-4 -2 0 2 4 6

0 10 20-2

0

2

4

610-9 10-7 10-5 10-3 10-1

-25

0

25

50

75

R (kΩ

)

µ0H (T)

J (MA/cm2)

τP = 300 µsec

1.0 sec

I C (µA

)

ln(τP/τ0)

J C (M

A/cm

2 ) P → AP

AP → P

τP (sec)

SiO2/Si sub.

Ta(5) Ru(10) Ta(5)

CoFeB(1.0 ) MgO(0.85) CoFeB(1.7)

Ta(5) Ru (5) Cr/Au TMR ratio =124%

RA = 18 Ωμm2

Hshift = 37 mT IC0 = 50 µA (P-> AP) - 20 µA (AP-> P) E/kBT = (∆P ) (∆AP )

40 nm

Parallel stateLow resistance

Different polarity=Stable

Free

Reference

N

S

N

S

Antiparallel stateHigh resistance

The same polarity=Unstable

N

S

N

S

13 K. Miura et al., 2011 VLSI Technology, 11B-3.

Stability Enhancement Structure

100 nm

Conventional structure

100 nm CoFeB

CoFeB

MgO 1.5 nm 0.9 nm 0.9 nm

CoFeB

CoFeB

MgO

100 nm

100 nm

300 nm

E/kBT“1” “0”

∆AP ∆P

dipole interlayer coupling field

“1” “0”∆AP ∆P

E/kBT

Hs Hs

Stepped structure

Free Layer

Reference Layer

14 K. Miura et al., 2011 VLSI Technology, 11B-3.

Stability Enhancement Structure

1

2

3

4

-100 -50 0 50 100

Res

ista

nce

(kΩ

)

Magnetic field (mT)

1

2

3

4

-100 -50 0 50 100

Res

ista

nce

(kΩ

)

Magnetic field (mT)

00.20.40.60.8

1

-150 -75 0 75 150

Prob

abili

ty

Magnetic field (mT)

00.20.40.60.8

1

-150 -75 0 75 150Pr

obab

ility

Magnetic field (mT)

“P”->”AP” “AP”->”P” “P”->”AP” “AP”->”P”

TMR Ratio (%) 100 97

RA (Ωµm2) 13 13

Hs (mT) 22 5

∆P 71.2 72.9

∆AP 46.5 70.1

Conventional structure Stepped structure

Alternative High Density RAM

15

10M

100M

1G

100 50 10 5 Cell Area Factor, a ( a =cell area/F ) 2

Rea

d C

lock

Fre

quen

cy (H

z)

High-speed eSRAM

eSRAM

SRAM

eDRAM

EEPROM NOR Flash

NAND Flash

eFLASH DRAM

MRAM, FRAM DRAM (1T+1C)

STTRAM (1T+1R)

1T+1R STT MRAM must have potential to be substituted for not only embedded DRAM but also commodity DRAM.

MRAM (2T+1R)

Alternative High Speed RAM

16

High speed RAM

10M

100M

1G

100 50 10 5 Cell Area Factor, a ( a =cell area/F ) 2

Rea

d C

lock

Fre

quen

cy (H

z)

High-speed eSRAM

eSRAM

SRAM

eDRAM

EEPROM NOR Flash

NAND Flash

eFLASH DRAM

MRAM, FRAM

High density RAM

DRAM (1T+1C)

STTRAM (1T+1R)

Current

Prob

abili

ty Read

Write

Barrier Breakdown

Current Path (Read & Write)

SRAM (6T)

Write Current

Read Current

High Speed eMRAM Cell

17

0Tr + 1MTJ 1Tr + 1MTJ 2Tr + 1MTJ

Magnetic Field STT

DWM

In plane Perpendicular

Al2O5

MgO

Requirements Choices

Disturb free cell structure High speed random access read/write Scalable MTJ size & write current Large magneto-resistance(MR) ratio BEOL process temperature 350 ºC Reliability Low tunnel current density Non-volatality Δ=E/k BT

Domain Wall

Domain Wall Motion(DWM) Writing

18

Domain Wall

R. Nebashi, et. al., Sym. VLSI Circuits. p. 300, 2011.

Free Layer

Reference Layer

Sense Layer Pinning Layer (2)

H. Honjo, et. al., 56th MMM Conference, 2011.

Pinning Layer (1)

Free Region Fixed Fixed

Write Current

Write Current Spin Transfer Torque

Spin Transfer Torque

Perpendicular Anisotropy •Two Pinning Layers (PL) •DWM Free Layer (FL) Hc(PL) >> Hc(FL)

Domain Wall Motion(DWM) Reading

19

R. Nebashi, et. al., Sym. VLSI Circuits. p. 300, 2011.

H. Honjo, et. al., 56th MMM Conference, HR-10, 2011.

In-plane Anisotropy •Sense Layer (SL) •Reference Layer (RL) Hc(RL) >> Hc(SL)

“0”

“1”

Sense layer magnetic direction is changed by stray field from DWM free layer

MTJ parallel

MTJ anti-parallel

Read Current

Domain Wall Free Layer

Reference Layer

Sense Layer Pinning Layer (2)

Pinning Layer (1)

Write Current ( Iw ) Target

Write Current (mA)

Cel

l Are

a (a

.u.)

0

0.5

1.0

1.5

2.0

2.5

3.0

0 0.5 1.0 1.5

2T1MTJ Cell Area

eMRAM with normal logic rule

eMRAM with modified rule

6T- eSRAM

Iw < 0.5mA Competitive in cost against eSRAM

-150-100 -50 0 50 100 150R

Hal

l(O

hm)

Current (µA)

CoFeB I w

rite

(mA

)

W (nm)

0.00.20.40.60.81.01.2

0 100 200

Co/PtCo/Ni

Domain wall

W

[Co/Ni]n

S. Fukami, et. al., Sym. VLSI Tech. p. 230, 2009.

20

S. Fukami ,et. al. Appl. Phys. Lett. Vol. 98, 082504, 2011.

21

DWM NVM Fabrication

5th-Metal line

PL1 PL2 4th-Via 4th-Via

In –Plane MTJ (Sense FL)

140nm

Side view

Front view R. Nebashi, et. al., Sym. VLSI Circuits. p. 300, 2011.

22

“Non-volatile logic-in-memory architecture”

FIRST Program Target

New Energy Saving System on a Chip for

Variety of applications

NV logic-in-memory

NV full adder NV TCAM NV flip-flop NV …… NV ……

Storage / Logic merged

nsec

Dynamic Power Reduction

Logic

Non-volatile memory

Logic with NVM

2 terminal STT 3 terminal MRAM ……

Static Power Reduction

By NVM

Please visit our homepage http://www.csis.tohoku.ac.jp/

Summary

23

1T+1MTJ STT(Spin Torque Transfer) MRAM has the potentials for substitution of embedded DRAM to apply high density embedded NVM application.

2T+1MTJ DWM(Domain Wall Motion) MRAM has the potentials for substitution of embedded SRAM to apply high speed NVM application.

These embedded MRAM technology leads to “logic-in-memory architecture” for future new energy saving SoC(System on a Chip).

Acknowledgements

24

This research is granted by the Japan Society for the Promotion of Science (JSPS) through the “Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program),” initiated by the Council for Science and Technology Policy (CSTP). Prof. Hideo Ohno has been conducting the program “Research and Development of Ultra-low Power Spintronics-based VLSIs“ as the core researcher.

Thanks to K. Miura, H. Yamamoto, K. Misunuma, H. D. Gan, M, Endo, S. Kanai, J. Hayakawa, F. Matsukura, M. Yamanouchi, J. Hayakawa, R. Kiizumi, S. Fukami, T. Suzuki, K. Nagahara, N. Ohshima, Y. Ozaki, S. Saito, R. Nebashi, N. Sakimura, H. Honjo, K. Mori, C. Igarashi, S. Miura, N. Ishiwata, K. Kinoshita, Y. Nakatani, Y. Tsuji, R. Nebashi, N. Sakimura, H. Honjo, K. Mori, H. Tanigawa, S. Miura, and T. Sugibayashi