Embedded Developer: September 2015

High-torque Electric Motors & Drive Systems Push e-Bikes to New Heights

Formal Low-power Verification

Profile of Today’s

Engineer

◀

◀

SEPT

EMBE

R, 2

105

EMBEDDED DEVEL

Your Guide to Embedded MCUs and Development Tools.

w w w . e m b e d d e d d e v e l o p e r . c o m

Everything you’re looking for in one place.

http://www.embeddeddeveloper.com

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EEWeb

EDITORIAL STAFFContent EditorAlex Maddalena [email protected]

Digital Content ManagerHeather Hamilton [email protected] Tel | 208-639-6485

Global Creative DirectorNicolas Perner [email protected]

Graphic DesignerCarol Smiley [email protected]

Audience DevelopmentClaire Hellar [email protected]

Register at EEWebhttp://www.eeweb.com/register/

Published byAspenCore

950 West Bannock Suite 450

Boise, Idaho 83702 Tel | 208-639-6464

Victor Alejandro Gao General Manager Executive Publisher

Cody Miller Global Media Director

Group Publisher

Glenn ImObersteg Publisher

Embedded Developer, LLC

Embedded Developer CONTENTS

38

4 28

CONTEST

The Evolution of the “Selfie”NXP Secure Interface & Power Embraces the Creativity of the Engineer

EEWEB FEATURE

Profile of Today’s Engineer

Assembly by Hand vs. Machine Assembly

Assembling High-current Heavy Copper PCBs

TECH REPORT

Formal Low-power Verification of Power-aware Designs

COVER STORY

High-torque Electric Motors & Drive System Push e-Bikes to New Heights

4

1622

10

28

38

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https://plus.google.com/106739393028670099537/posts

https://www.youtube.com/user/EEWebVideos

4

Embedded Developer

The Rise of

In a new program based on the creativity of the engineer, NXP Secure Interface and Power utilizes a new medium to share technical information.

the Selfie

By Glenn ImObersteg, Convergence Promotions

CONTEST

5

The Rise of

In a new program based on the creativity of the engineer, NXP Secure Interface and Power utilizes a new medium to share technical information.

the Selfie


www.askinterface.com

6

Embedded Developer

The Rise of the Selfie and Social Media in the Business and Engineering Environment

Today, almost 40% of the world’s population has regular access to the internet, compared to 12% a decade ago, spawning a dramatic rise in the use of social media as a new communication channel. Predominantly a consumer pastime, and once viewed as a distraction in the business and engineering environment by an older generation of engineers, it has steadily taken its place as a preeminent communication medium for the younger, more savvy engineering generation.

One aspect of the popularity of the rise of social media in the workplace are videos and personal contact. Technical videos and direct contact have replaced whitepapers and case studies as the leading source of technical information. This rising popularity is due to access to an abundance of information in one place: YouTube. Studies show that YouTube is now the number two search engine in the world, with over 100 hours of video footage uploaded every minute.

The Selfie is an Important Element in the NXP ASKInterface, Q & A Program

The popularity of the video as a viable marketing tool for the engineering community, paired with the rising popularity of the Selfie, has spawned a new information exchange and Q&A program from Convergence, sponsored by NXP Secure Interface and Power, called AskInterface.

Getting Started

Convergence Promotions and their sponsors, NXP, expect that this combination of selfies, interactive Q&A and community will open a new channel for business-to-business interaction in the social media venue. Get started with the InYourFace program and maybe this month yours will be one of the eight questions or answers selected to win $100 Amazon gift cards like the contestants on the right. Click on the video here or go to www.Askinterface.com.

ASKInterface Winners for the July/August Topic:

Load Switches

Winning Answer:

KEVIN MORRIS

In response to:

“What is the benefit of using an integrated load switch over an LDO for distributing power?”

There are several benefits. The first advantage is that load switches reduce power dissipation by presenting a much lower voltage drop across the channel. Load switches also give you in-rush current protection by limiting the slew rate under heavy loading. Another bonus is that it offers a higher level of integration and can save PCB space—the benefits are pretty substantial.

Winning Answer:

ARMSTRONG FOUNDJEM

In response to:

“How do I select a load switch for my new design?”

The criteria for selecting load switches will depend on whether power savings or power sequencing is your concern. Then, look for a slew rate-controlled load switch with low and flat on-resistance for the intended range of operation.

If you want to protect either voltage or current, choose load switches based on current or surge rating and whether the device should open or regulate during a surge event. You’ll also want to consider package, quiescent current, and features like over-temperature protection, reverse-current protection, and ESD protection.

http://www.askinterface.com

CONTEST

7

The Rise of the Selfie and Social Media in the Business and Engineering Environment

Today, almost 40% of the world’s population has regular access to the internet, compared to 12% a decade ago, spawning a dramatic rise in the use of social media as a new communication channel. Predominantly a consumer pastime, and once viewed as a distraction in the business and engineering environment by an older generation of engineers, it has steadily taken its place as a preeminent communication medium for the younger, more savvy engineering generation.

One aspect of the popularity of the rise of social media in the workplace are videos and personal contact. Technical videos and direct contact have replaced whitepapers and case studies as the leading source of technical information. This rising popularity is due to access to an abundance of information in one place: YouTube. Studies show that YouTube is now the number two search engine in the world, with over 100 hours of video footage uploaded every minute.

The Selfie is an Important Element in the NXP ASKInterface, Q & A Program

The popularity of the video as a viable marketing tool for the engineering community, paired with the rising popularity of the Selfie, has spawned a new information exchange and Q&A program from Convergence, sponsored by NXP Secure Interface and Power, called AskInterface.

Getting Started

Convergence Promotions and their sponsors, NXP, expect that this combination of selfies, interactive Q&A and community will open a new channel for business-to-business interaction in the social media venue. Get started with the InYourFace program and maybe this month yours will be one of the eight questions or answers selected to win $100 Amazon gift cards like the contestants on the right. Click on the video here or go to www.Askinterface.com.


Load Switches

Winning Answer:

KEVIN MORRIS

In response to:

“What is the benefit of using an integrated load switch over an LDO for distributing power?”

There are several benefits. The first advantage is that load switches reduce power dissipation by presenting a much lower voltage drop across the channel. Load switches also give you in-rush current protection by limiting the slew rate under heavy loading. Another bonus is that it offers a higher level of integration and can save PCB space—the benefits are pretty substantial.

Winning Answer:

ARMSTRONG FOUNDJEM

In response to:


The criteria for selecting load switches will depend on whether power savings or power sequencing is your concern. Then, look for a slew rate-controlled load switch with low and flat on-resistance for the intended range of operation.

If you want to protect either voltage or current, choose load switches based on current or surge rating and whether the device should open or regulate during a surge event. You’ll also want to consider package, quiescent current, and features like over-temperature protection, reverse-current protection, and ESD protection.

8

Embedded Developer

Congratulations to the winners of $100 Amazon gift cards for their answers! To join the October & November ASKInterface contest, and chances to win $1000 worth of Amazon gift cards, register at www.askinterface.com.

Winning Answer:

LOGAN HUNTER

In response to:

“Why would I use a surge protection device over a discrete MOSFET?”

A discrete MOSFET will not provide safety functions or allow programmability. A surge-protection device provides multi-level protection and prevents excessive current draw from a load or short circuit. It can damp or regulate voltage during a surge or with heavy line transients. When such an event occurs, the device will disconnect.

Winning Answer:

DARELL PARKER

In response to:


If you are concerned with saving power or power sequencing, look for a slew rate controlled load switch with low and flat on-resistance for the intended range of operation. If you need voltage protection or current protection, choose a load switch based on current rating and surge rating of the device and whether the device should open or regulate during a surge event. You’ll also want to consider package, quiescent current, and features like over-temperature protection, reverse current protection, and ESD protection.

Winning Answer:

KATHY CLARK

In response to:

“Can the internal structure of the load switch prevent the backflow of current from the load to the power source?”

Load switches integrating RCP (reverse current protection) will block the backflow of current from the output to the input. If output voltage exceeds input by a predetermined value, the power FET will open and disconnect the input to output connection. This also eliminates the need for external diodes.

Winning Answer:

YUVAL

In response to:


The answer is “yes,” but only if the load switch designed with dual back-to-back MOSFETs in the signal path.


Load Switches

Recent studies show that YouTube is now the number two search engine in the world, with over 100 hours of video footage uploaded every minute.

www.askinterface.com

CONTEST

9

Congratulations to the winners of $100 Amazon gift cards for their answers! To join the October & November ASKInterface contest, and chances to win $1000 worth of Amazon gift cards, register at www.askinterface.com.

Winning Answer:

LOGAN HUNTER

In response to:

“Why would I use a surge protection device over a discrete MOSFET?”

A discrete MOSFET will not provide safety functions or allow programmability. A surge-protection device provides multi-level protection and prevents excessive current draw from a load or short circuit. It can damp or regulate voltage during a surge or with heavy line transients. When such an event occurs, the device will disconnect.

Winning Answer:

DARELL PARKER

In response to:


If you are concerned with saving power or power sequencing, look for a slew rate controlled load switch with low and flat on-resistance for the intended range of operation. If you need voltage protection or current protection, choose a load switch based on current rating and surge rating of the device and whether the device should open or regulate during a surge event. You’ll also want to consider package, quiescent current, and features like over-temperature protection, reverse current protection, and ESD protection.

Winning Answer:

KATHY CLARK

In response to:


Load switches integrating RCP (reverse current protection) will block the backflow of current from the output to the input. If output voltage exceeds input by a predetermined value, the power FET will open and disconnect the input to output connection. This also eliminates the need for external diodes.

Winning Answer:

YUVAL

In response to:


The answer is “yes,” but only if the load switch designed with dual back-to-back MOSFETs in the signal path.


Load Switches

Recent studies show that YouTube is now the number two search engine in the world, with over 100 hours of video footage uploaded every minute.

http://www.askinterface.com

10

Embedded Developer

PLAID ATTIRE

CAD DRAWINGS

REVISIONS 1-4

RESIDES IN THENORTHWESTERNUNITED STATES

AGE: 26 - 35

$50,000 - $150,000SALARY

Josh is a plaid-wearing professional in Boise, Idaho,

both in that he works professionally and that he’s

really good at wearing plaid. He’s been a Navy

Communications Officer, a Company Commander and

an Assistant Public Works Officer. Now, he’s a writer and

marketer, a micro business owner in product design,

and a man of all trades. Josh is an electrical engineer.

ENGINEER

Profile ofToday’s

11

EEWeb FEATURE

PLAID ATTIRE

CAD DRAWINGS

REVISIONS 1-4

RESIDES IN THENORTHWESTERNUNITED STATES

AGE: 26 - 35

$50,000 - $150,000SALARY

Josh is a plaid-wearing professional in Boise, Idaho,

both in that he works professionally and that he’s

really good at wearing plaid. He’s been a Navy

Communications Officer, a Company Commander and

an Assistant Public Works Officer. Now, he’s a writer and

marketer, a micro business owner in product design,

and a man of all trades. Josh is an electrical engineer.

ENGINEER

Profile ofToday’s

12

Embedded Developer

Day to day, his work varies. He’s writing technical articles, reviewing schematics, designing hardware projects and attempting to explain the 3D printer to his less technically inclined coworkers. In his free time, Josh is a maker, working to develop products and ideas that address his many passions.

Josh works in the northwestern region of the United States, along with 11.91% of engineers surveyed in a study by Advanced Assembly. His fellow engineers are in the northeast (15.32%), the southwest (14.04%) the southeast (8.94%), central region (15.04%), and Canada (2.84%). Unsurprisingly, 31.91% of respondents reside elsewhere.

While Josh falls within the 26-35 age range with nearly 19% of respondents, the under 45 category accounts for a total percentage of only 49.64%, with those over the age of 46 accounting for the remaining 50.35%.

WHERE THEY’RE WORKING

Most engineers surveyed have, like Josh, been at their job for between one and five years. They’re coming from small companies who employ between one and five engineers. Of course, some respondents are working

for companies that employ 20, 40, and even 1,000 people.

Their income varies greatly, ranging from around $50,000 to upwards of $150,000, which may reflect the fact that they’re working at companies of different sizes, are geographically varied, and have a variety of job experience.

THE DESIGN PROCESS

For Josh, the longest part of PCB design is the initial design—but what feels the longest is the debugging process. There’s a sense of excitement in the initial phases, a momentum created in the making of something new. Debugging can be tedious and wear the initial enthusiasm thin, though Josh admits that a properly working board offers significant reward.

Data suggests that Josh is not alone—nearly 34% of surveyed engineers believe that the most work goes into the design process, followed closely by debugging. Others work harder in the scoping, manufacturing, and prototyping stage. Within the prototyping stage, almost 27% of engineers find changing job requirements to cause the most headaches, though the purchasing of parts and boards, budgetary restrictions and looming deadlines are also stress inducers. Interestingly, few engineers

(11.86%) have trouble finding a quality manufacturer and assembler.

And it is no surprise that the design process is the most tedious—32.71% of engineers revise around three times, though most all fall under five. In a perfect world, second revisions are production ready. In reality, three to five revisions are needed to get to production. Lower numbers might represent engineers who are building less expensive boards with parts that can be easily changed out (jumpers, etc.). However, for small consumer items produced in the millions, revisions are very necessary.

The majority of engineers are designing with fewer parts, between one and 25, with the number of engineers becoming incrementally smaller as the number of parts increases. There are likely a number of reasons for this, including breadth of work being performed.

ASSEMBLY PARTNERS

Engineers seem to be fairly split in terms of how often they require assembly services—though over half fall in categories using assembly services four or less times per year. The smallest percentage of engineers require assembly weekly, and few more require

it even monthly. Around 80% need under 25 boards, and an extremely small percentage need over 100.

It probably comes as no surprise that the overwhelming majority of engineers would like communication with PCB assembly vendors via email, though a small number prefer telephone or video conferencing. Choosing which assembly house to partner with can be quite a struggle though. For Josh, it can depend on the board. For simple boards, cost is the primary consideration. For complex boards, he rates speed, communication, and trust as the most important factors.

Josh identifies some crucial characteristics of the types of assembly houses engineers want to engage with. Among those surveyed, on time delivery was most desired, followed closely by clear and consistent communication. Contact in case of problems and flexibility of price also ranked highly.

Of the engineers surveyed, most were actually relying on hand assembly at their company (59.78%). The second highest number of responding engineers reported that their boards were assembled at a local assembly shop. Finally, equal numbers (around 10%) used

Nearly 34% of surveyed engineers believe that the most work goes into the design process, followed closely by debugging.

For simple boards, cost is the primary consideration. For complex boards, speed, communication, and trust are the most important factors.

13

EEWeb FEATURE

Day to day, his work varies. He’s writing technical articles, reviewing schematics, designing hardware projects and attempting to explain the 3D printer to his less technically inclined coworkers. In his free time, Josh is a maker, working to develop products and ideas that address his many passions.

Josh works in the northwestern region of the United States, along with 11.91% of engineers surveyed in a study by Advanced Assembly. His fellow engineers are in the northeast (15.32%), the southwest (14.04%) the southeast (8.94%), central region (15.04%), and Canada (2.84%). Unsurprisingly, 31.91% of respondents reside elsewhere.

While Josh falls within the 26-35 age range with nearly 19% of respondents, the under 45 category accounts for a total percentage of only 49.64%, with those over the age of 46 accounting for the remaining 50.35%.

WHERE THEY’RE WORKING

Most engineers surveyed have, like Josh, been at their job for between one and five years. They’re coming from small companies who employ between one and five engineers. Of course, some respondents are working

for companies that employ 20, 40, and even 1,000 people.

Their income varies greatly, ranging from around $50,000 to upwards of $150,000, which may reflect the fact that they’re working at companies of different sizes, are geographically varied, and have a variety of job experience.

THE DESIGN PROCESS

For Josh, the longest part of PCB design is the initial design—but what feels the longest is the debugging process. There’s a sense of excitement in the initial phases, a momentum created in the making of something new. Debugging can be tedious and wear the initial enthusiasm thin, though Josh admits that a properly working board offers significant reward.

Data suggests that Josh is not alone—nearly 34% of surveyed engineers believe that the most work goes into the design process, followed closely by debugging. Others work harder in the scoping, manufacturing, and prototyping stage. Within the prototyping stage, almost 27% of engineers find changing job requirements to cause the most headaches, though the purchasing of parts and boards, budgetary restrictions and looming deadlines are also stress inducers. Interestingly, few engineers

(11.86%) have trouble finding a quality manufacturer and assembler.

And it is no surprise that the design process is the most tedious—32.71% of engineers revise around three times, though most all fall under five. In a perfect world, second revisions are production ready. In reality, three to five revisions are needed to get to production. Lower numbers might represent engineers who are building less expensive boards with parts that can be easily changed out (jumpers, etc.). However, for small consumer items produced in the millions, revisions are very necessary.

The majority of engineers are designing with fewer parts, between one and 25, with the number of engineers becoming incrementally smaller as the number of parts increases. There are likely a number of reasons for this, including breadth of work being performed.

ASSEMBLY PARTNERS

Engineers seem to be fairly split in terms of how often they require assembly services—though over half fall in categories using assembly services four or less times per year. The smallest percentage of engineers require assembly weekly, and few more require

it even monthly. Around 80% need under 25 boards, and an extremely small percentage need over 100.

It probably comes as no surprise that the overwhelming majority of engineers would like communication with PCB assembly vendors via email, though a small number prefer telephone or video conferencing. Choosing which assembly house to partner with can be quite a struggle though. For Josh, it can depend on the board. For simple boards, cost is the primary consideration. For complex boards, he rates speed, communication, and trust as the most important factors.

Josh identifies some crucial characteristics of the types of assembly houses engineers want to engage with. Among those surveyed, on time delivery was most desired, followed closely by clear and consistent communication. Contact in case of problems and flexibility of price also ranked highly.

Of the engineers surveyed, most were actually relying on hand assembly at their company (59.78%). The second highest number of responding engineers reported that their boards were assembled at a local assembly shop. Finally, equal numbers (around 10%) used

Nearly 34% of surveyed engineers believe that the most work goes into the design process, followed closely by debugging.

For simple boards, cost is the primary consideration. For complex boards, speed, communication, and trust are the most important factors.

www.aapcb.com

14

Embedded Developer

their company’s own machine assembly line or sought the help of a large contract manufacturer.

INDUSTRY CHANGES AND AREAS OF INTEREST

Engineers, Josh included, are hungry for information, and they’re particularly interested in PCB design tips, current technologies, new markets and economic trends.

Of the engineers surveyed, around 35% said that they aren’t using any technology this year that they weren’t using last year—a surprising number in an industry that experiences such growth and change. Of course, many are also taking advantage of new CAD programs, 3D printers, mobile and web based tools, microtechnology

Advanced Assembly was founded to help engineers assemble their prototype and low-volume PCB orders. Based on years of experience within the printed circuit board industry, Advanced Assembly developed a proprietary system to deliver consistent, machine surface mount technology (SMT) assembly in 1-5 days. It’s our only focus. We take the hassle out of PCB assembly and make it easy, so you can spend time on other aspects of your design.

20100 E. 32nd Pkwy #225 | Aurora, CO 80011 | www.aapcb.com | 1-800-838-5650

and CNC. As for Josh, he’s using a new 3D CAD tool for enclosures.

And Josh’s own enclosure? Like many engineers, it is an office within an office, a place intermittently buzzing with conversation and quiet. Amidst the tap tap of fingers on keys, one hears the zzzzzzzthurp! of a 3D printer, gradually constructing the cookie cutter Josh designed for his wife.

A QUICK NOTE

While Josh and those surveyed represent some electrical engineers, they are but 905 members of a much larger, varied community of professionals. All, some, or none of the data represented may be reflective of the experience of any given electrical engineer.

http://www.aapcb.com

MYLINK

their company’s own machine assembly line or sought the help of a large contract manufacturer.

INDUSTRY CHANGES AND AREAS OF INTEREST

Engineers, Josh included, are hungry for information, and they’re particularly interested in PCB design tips, current technologies, new markets and economic trends.

Of the engineers surveyed, around 35% said that they aren’t using any technology this year that they weren’t using last year—a surprising number in an industry that experiences such growth and change. Of course, many are also taking advantage of new CAD programs, 3D printers, mobile and web based tools, microtechnology



and CNC. As for Josh, he’s using a new 3D CAD tool for enclosures.

And Josh’s own enclosure? Like many engineers, it is an office within an office, a place intermittently buzzing with conversation and quiet. Amidst the tap tap of fingers on keys, one hears the zzzzzzzthurp! of a 3D printer, gradually constructing the cookie cutter Josh designed for his wife.

A QUICK NOTE

While Josh and those surveyed represent some electrical engineers, they are but 905 members of a much larger, varied community of professionals. All, some, or none of the data represented may be reflective of the experience of any given electrical engineer.

http://www.pcbweb.com

16

Embedded Developer

Nearly every successful company passes through the difficult transformation of being small to being large. As this transition occurs, there are many

product development decisions to be made. For instance, in the past, it was not uncommon for smaller companies and startups to hand solder small quantities of circuit boards in order to fine-tune their PCB designs. As things ramp up and production increased, however, it made sense move to automated machine assembly. Today, it is possible to affordable machine-assemble boards regardless of the product lifecycle phase. In fact, companies exist that specialize in machine assembling low-volume and prototype orders—even for just one or two boards.

MACHINE

Assembly by Hand

vs.

A S S E M B LY

17

EEWeb FEATURE

Nearly every successful company passes through the difficult transformation of being small to being large. As this transition occurs, there are many

product development decisions to be made. For instance, in the past, it was not uncommon for smaller companies and startups to hand solder small quantities of circuit boards in order to fine-tune their PCB designs. As things ramp up and production increased, however, it made sense move to automated machine assembly. Today, it is possible to affordable machine-assemble boards regardless of the product lifecycle phase. In fact, companies exist that specialize in machine assembling low-volume and prototype orders—even for just one or two boards.

MACHINE

Assembly by Hand

vs.

A S S E M B LY

18

Embedded Developer

With individual hand-solder joints, achieving consistent quality in large volumes can be difficult. Before pick-and-place machines, the industry suffered from variable quality, as operators tirelessly soldered thousands of solder joints a day. The hand-assembly process with human fallibility easily can result in incorrect part placement on a PCB. Inconsistency is a major problem with hand assembly while automatic assembly virtually eliminates misplaced components. Size constraints imposed by hand assembly are also a consideration. During the period from 1960 to 1990, the industry was only concerned with leaded resistors and through-hole chip packages. As electronics got smaller, the ability to hand solder these new parts decreased. Pick-and-place machines make it possible to properly place the new, smaller, lower cost 0402, 0201 and 01005 chips and larger, high pin count, BGA chips.

Lead-free solders are different from traditional tin/lead solder and more difficult to hand solder, as they have higher melting points and inferior wetting properties. Using a typical hand-solder iron, solder wetting will take a little longer and the solder will tend to spread less. Non-eutectic, lead-free alloys have a very small plastic range so the part being soldered must not be moved until the solder has cooled down and solidified; something that can be hard to achieve with hand placement and hand soldering. Due to this and other factors, the quality of hand soldering by even the best workers will struggle when compared to the consistency of infrared-tunnel soldered joints. The even solder joints and flat components delivered through the combination of infrared soldering reflow, properly metered solder paste, and a good quality pick-and-place machine is hard to beat.

Speed also is a major roadblock with hand soldering. A manual operator would have to work very hard to put down and solder 1000 parts an hour. A solder paste applier, high-speed chip shooter, pick-and-place machine and infrared oven placed in a conveyor configuration can apply solder paste, place and solder 50,000 parts or more per hour. While certain pick-and-place machines advertise significantly higher numbers than that, real life cases usually bring the actual specifications down. However, even at the reduced rate, pick and place machines are orders of magnitude faster than hand soldering.

To set up a small, automatic assembly line is not difficult, but can be expensive. You would need an accurate screen stencil printer and a universal type pick-and-place machine, which is designed to place the type of chips and parts that you use. You would also need a small, infrared tunnel oven and a microscope quality assurance station. You can have individual assembly units and PCB stackers to hold the PCB while in progress or you can connect all the machines together with automatic handlers and let them pass through the entire automated process without

human interaction. You will probably need a few hand-repair stations as well as special hand-operated, hot-air chip soldering/de-soldering units for those parts that need some touch up. As an operator, it is important to protect the workers from health concerns. A serious problem with hand soldering is that the operator is exposed to solder fumes and flux fumes.

Small, vacuum-operated local fans can help to cut the operators’ contact with metallic compounds such as lead, copper, cadmium, bismuth, antimony and tin. Even without the lead, the exposure threat still exists with lead free solder, as the operator is handling solder rolls and components.

Pick-and-place machines make it possible to properly place the new, smaller, lower cost 0402, 0201 and 01005 chips and larger, high pin count, BGA chips.

19

EEWeb FEATURE

With individual hand-solder joints, achieving consistent quality in large volumes can be difficult. Before pick-and-place machines, the industry suffered from variable quality, as operators tirelessly soldered thousands of solder joints a day. The hand-assembly process with human fallibility easily can result in incorrect part placement on a PCB. Inconsistency is a major problem with hand assembly while automatic assembly virtually eliminates misplaced components. Size constraints imposed by hand assembly are also a consideration. During the period from 1960 to 1990, the industry was only concerned with leaded resistors and through-hole chip packages. As electronics got smaller, the ability to hand solder these new parts decreased. Pick-and-place machines make it possible to properly place the new, smaller, lower cost 0402, 0201 and 01005 chips and larger, high pin count, BGA chips.

Lead-free solders are different from traditional tin/lead solder and more difficult to hand solder, as they have higher melting points and inferior wetting properties. Using a typical hand-solder iron, solder wetting will take a little longer and the solder will tend to spread less. Non-eutectic, lead-free alloys have a very small plastic range so the part being soldered must not be moved until the solder has cooled down and solidified; something that can be hard to achieve with hand placement and hand soldering. Due to this and other factors, the quality of hand soldering by even the best workers will struggle when compared to the consistency of infrared-tunnel soldered joints. The even solder joints and flat components delivered through the combination of infrared soldering reflow, properly metered solder paste, and a good quality pick-and-place machine is hard to beat.

Speed also is a major roadblock with hand soldering. A manual operator would have to work very hard to put down and solder 1000 parts an hour. A solder paste applier, high-speed chip shooter, pick-and-place machine and infrared oven placed in a conveyor configuration can apply solder paste, place and solder 50,000 parts or more per hour. While certain pick-and-place machines advertise significantly higher numbers than that, real life cases usually bring the actual specifications down. However, even at the reduced rate, pick and place machines are orders of magnitude faster than hand soldering.

To set up a small, automatic assembly line is not difficult, but can be expensive. You would need an accurate screen stencil printer and a universal type pick-and-place machine, which is designed to place the type of chips and parts that you use. You would also need a small, infrared tunnel oven and a microscope quality assurance station. You can have individual assembly units and PCB stackers to hold the PCB while in progress or you can connect all the machines together with automatic handlers and let them pass through the entire automated process without

human interaction. You will probably need a few hand-repair stations as well as special hand-operated, hot-air chip soldering/de-soldering units for those parts that need some touch up. As an operator, it is important to protect the workers from health concerns. A serious problem with hand soldering is that the operator is exposed to solder fumes and flux fumes.

Small, vacuum-operated local fans can help to cut the operators’ contact with metallic compounds such as lead, copper, cadmium, bismuth, antimony and tin. Even without the lead, the exposure threat still exists with lead free solder, as the operator is handling solder rolls and components.

Pick-and-place machines make it possible to properly place the new, smaller, lower cost 0402, 0201 and 01005 chips and larger, high pin count, BGA chips.

www.aapcb.com

20

Embedded Developer

A properly set up assembly line only needs a few people to run; a significant savings in labor costs over hand soldering. A single automatic line can place and solder more components than 50 hand solder operators, and do it with better, more consistent quality. This increased amount of automation can bring the automated assembly costs down to the same level as hand soldering, while also experiencing a higher level of quality and repeatability. However, the most economic route for machine-assembling PCBs is to outsource the assembly to a trusted assembly partner. PCB assembly companies have invested in the equipment and processes necessary to deliver high-quality, fully assembled boards in less than a week. Leaving the assembly to the experts, will shave days, or even weeks, off your product development timeline, allowing you to bring products to market faster with higher profit margins.



A single automatic line can place and solder more components than 50 hand solder operators, and do it with better, more consistent quality.


MYLINK

A properly set up assembly line only needs a few people to run; a significant savings in labor costs over hand soldering. A single automatic line can place and solder more components than 50 hand solder operators, and do it with better, more consistent quality. This increased amount of automation can bring the automated assembly costs down to the same level as hand soldering, while also experiencing a higher level of quality and repeatability. However, the most economic route for machine-assembling PCBs is to outsource the assembly to a trusted assembly partner. PCB assembly companies have invested in the equipment and processes necessary to deliver high-quality, fully assembled boards in less than a week. Leaving the assembly to the experts, will shave days, or even weeks, off your product development timeline, allowing you to bring products to market faster with higher profit margins.



A single automatic line can place and solder more components than 50 hand solder operators, and do it with better, more consistent quality.

http://www.orderpcbs.com

22

Embedded Developer

Many designers and assemblers do not know what is readily available

in high current heavy copper PCB. Heavy copper boards can contain three ounces to twenty ounces of copper conductors. Quite surprisingly, a heavy copper PCB (ten ounces) can also have very fine features.

High-Current Heavy Copper

PCBs

Assembling

23

EEWeb FEATURE

Many designers and assemblers do not know what is readily available

in high current heavy copper PCB. Heavy copper boards can contain three ounces to twenty ounces of copper conductors. Quite surprisingly, a heavy copper PCB (ten ounces) can also have very fine features.

High-Current Heavy Copper

PCBs

Assembling

24

Embedded Developer

There are many variations of the heavy copper technology, including buried heavy copper, multiple levels of copper, and multilayer heavy copper. The simplest form of heavy copper is the single or double-sided PCB, containing three- to twenty-ounce thickness of copper. By starting with a heavy copper base, such as eight-ounce foil on FR4, imaging and etching the circuit, single and double-sided PCBs have the lowest cost. On all heavy copper boards, the designer has the choice of starting copper thickness and the amount plated in the holes. The current required to be passed in the vias will determine the amount of copper plated in the hole. To plate ten ounces of copper in the holes of a twelve ounce thick PCB, the manufacturer will start with two ounces of copper and plate up to ten ounces in the holes and on the traces.

Resolution will be quite good as the manufacturer is only etching two ounces of copper foil. To plate that thick, multiple layers of dry

film will be sequentially layered on three to ten times and then imaged and developed, creating very deep dry film trenches to plate copper up. The plating of ten ounces of copper is quite slow, taking forty-five minutes per ounce, so the PCB will be expensive but can carry hundreds of amps.

Multilayer heavy copper can have four to eight layers, up to fifteen ounces of copper per layer and interconnected with heavy copper in the vias. In both multilayer and double-sided PCBs, the use of large thermal reliefs is of utmost importance for assembly. The heavy copper conducts so much heat that you would never be able to solder the components.

A very advanced heavy copper PCB is the multilayer PCB with two to five different copper levels, all interconnected and intertwined on the same layer. Note the extra vias in the large pads to pass more current and keep the pad attached, as well as providing a stronger pad for the bolt holding the cable in place.

Assembling a high current, heavy copper board can be difficult, but not impossible. Extra care and engineering when designing the board must be observed to allow the thermal transfer of the heat from a soldering iron to the pads. The use of track neck downs as well as large open thermal reliefs help the soldering iron deliver the heat needed. It is not recommended to IR or wave solder a heavy copper board. The heat picked up by the copper will be retained for so long that the heat in the FR4 joint will cause failure, and the copper traces will lift off the board.

The soldering of heavy copper PCBs can present problems if your assembly company is not experienced in trying to get enough heat into the board to solder the components. Many heavy copper PCBs need to be hand soldered on a hot plate just to get a high enough temperature to solder properly. The very thick copper in the vias can make heating the via pad to a high enough temperature difficult without losing adhesion to the FR4 and lifting

the pad. Most experienced heavy copper designers will add extra vias around the pads to rivet the pad to the FR4 board. It is recommended that the PCB manufacturer use high-temperature lead-free rated laminate to help keep the pads attached with all the retained heat.

Problems encountered in assembling heavy copper PCBs are mostly based on cold solder joints, without full flow through to the other side of the via.

A new lower cost manufacturing method assists the assembly by replacing the heavy copper protruding up to twenty mils off the surface. The new buried heavy technology is flat to the surface. The buried heavy copper PCB presents a different view of the product because it looks and feels like a normal board, but has up to ten ounces of copper buried into the FR4 under the surface. This new technology helps assembly companies as the thinner one to two ounce copper pads will solder without a hot plate.

As all the tops of the traces are at the same solder height, paste stencils can be used. However, the ten-ounce area will still need assistance with external heat to properly solder. Buried heavy boards can have any amount of the copper below or above the surface.

Example: Typical ten-ounce power board, eight-ounce below and two ounce copper traces above. Also, the top copper can have any amount of plating added to any tracks as well as the vias. The two-ounce SMT

A very advanced heavy copper PCB is the multilayer PCB with two to five different copper levels, all interconnected and intertwined on the same layer.

The buried heavy copper PCB presents a different view of the product because it looks and feels like a normal board, but has up to ten ounces of copper buried into the FR4 under the surface.

25

EEWeb FEATURE

There are many variations of the heavy copper technology, including buried heavy copper, multiple levels of copper, and multilayer heavy copper. The simplest form of heavy copper is the single or double-sided PCB, containing three- to twenty-ounce thickness of copper. By starting with a heavy copper base, such as eight-ounce foil on FR4, imaging and etching the circuit, single and double-sided PCBs have the lowest cost. On all heavy copper boards, the designer has the choice of starting copper thickness and the amount plated in the holes. The current required to be passed in the vias will determine the amount of copper plated in the hole. To plate ten ounces of copper in the holes of a twelve ounce thick PCB, the manufacturer will start with two ounces of copper and plate up to ten ounces in the holes and on the traces.

Resolution will be quite good as the manufacturer is only etching two ounces of copper foil. To plate that thick, multiple layers of dry

film will be sequentially layered on three to ten times and then imaged and developed, creating very deep dry film trenches to plate copper up. The plating of ten ounces of copper is quite slow, taking forty-five minutes per ounce, so the PCB will be expensive but can carry hundreds of amps.

Multilayer heavy copper can have four to eight layers, up to fifteen ounces of copper per layer and interconnected with heavy copper in the vias. In both multilayer and double-sided PCBs, the use of large thermal reliefs is of utmost importance for assembly. The heavy copper conducts so much heat that you would never be able to solder the components.

A very advanced heavy copper PCB is the multilayer PCB with two to five different copper levels, all interconnected and intertwined on the same layer. Note the extra vias in the large pads to pass more current and keep the pad attached, as well as providing a stronger pad for the bolt holding the cable in place.

Assembling a high current, heavy copper board can be difficult, but not impossible. Extra care and engineering when designing the board must be observed to allow the thermal transfer of the heat from a soldering iron to the pads. The use of track neck downs as well as large open thermal reliefs help the soldering iron deliver the heat needed. It is not recommended to IR or wave solder a heavy copper board. The heat picked up by the copper will be retained for so long that the heat in the FR4 joint will cause failure, and the copper traces will lift off the board.

The soldering of heavy copper PCBs can present problems if your assembly company is not experienced in trying to get enough heat into the board to solder the components. Many heavy copper PCBs need to be hand soldered on a hot plate just to get a high enough temperature to solder properly. The very thick copper in the vias can make heating the via pad to a high enough temperature difficult without losing adhesion to the FR4 and lifting

the pad. Most experienced heavy copper designers will add extra vias around the pads to rivet the pad to the FR4 board. It is recommended that the PCB manufacturer use high-temperature lead-free rated laminate to help keep the pads attached with all the retained heat.

Problems encountered in assembling heavy copper PCBs are mostly based on cold solder joints, without full flow through to the other side of the via.

A new lower cost manufacturing method assists the assembly by replacing the heavy copper protruding up to twenty mils off the surface. The new buried heavy technology is flat to the surface. The buried heavy copper PCB presents a different view of the product because it looks and feels like a normal board, but has up to ten ounces of copper buried into the FR4 under the surface. This new technology helps assembly companies as the thinner one to two ounce copper pads will solder without a hot plate.

As all the tops of the traces are at the same solder height, paste stencils can be used. However, the ten-ounce area will still need assistance with external heat to properly solder. Buried heavy boards can have any amount of the copper below or above the surface.

Example: Typical ten-ounce power board, eight-ounce below and two ounce copper traces above. Also, the top copper can have any amount of plating added to any tracks as well as the vias. The two-ounce SMT

A very advanced heavy copper PCB is the multilayer PCB with two to five different copper levels, all interconnected and intertwined on the same layer.

The buried heavy copper PCB presents a different view of the product because it looks and feels like a normal board, but has up to ten ounces of copper buried into the FR4 under the surface.

www.aapcb.com

26

Embedded Developer



Assembly technology for heavy copper boards needs to be tested and figured out before you can solder the heat absorbing heavy copper. The thickness of the copper varies between four ounces and twenty ounces of copper on the surface and possibly in the through holes. The heavy copper PCB can be on almost any type of laminate from flex to FR4 through polyimide. The heavy copper PCB will most likely be very heavy and thicker than a normal PCB. Your assembly company will have a learning curve and will need some solder samples to experiment with.

When trying to solder twenty ounces of copper, it can be a big surprise when placing a large soldering iron on a big pad to solder it. No matter what you do, the solder won’t melt. A large adjustable lab-style hot plate works well to preheat the heavy copper PCB. Monitor the PCB temperature with an accurate thermocouple type meter. After you have soldered the board, let it cool slowly so as not to delaminate the board.

pads are soldered as normal after a hot plate is used to solder a few push in connectors into the ten-ounce section.

Buried heavy copper has a large number of variants, which can be used to make just about any possible combination of copper weights and technologies.

The heavy copper PCB will most likely be very heavy and thicker than a normal PCB.


Schematics.com

Your Circuit Starts Here.Sign up to design, share, and collaborate

on your next project—big or small.

Click Here to Sign Up

http://www.schematics.com

28

Embedded Developer

By

Power reduction and management methods are now all pervasive

in a system-on-chip (SoC) designs. They are used in SoCs targeted

at power-critical applications ranging from mobile appliances with

limited battery life to big-box electronics that consume large amounts

of increasingly expensive power. Power reduction methods are now

applied throughout the chip design flow from architectural design

through RTL implementation to physical design.

Formal Low-power VERIFICATION of Power-aware Designs

The Cadence® JasperGold® Low-power Verification (LPV) App works with other JasperGold Apps to overcome verification challenges posed by power-aware chip design, including power management, IP use and re-use, and DFT circuitry.

TECH REPORT

29

By

Power reduction and management methods are now all pervasive

in a system-on-chip (SoC) designs. They are used in SoCs targeted

at power-critical applications ranging from mobile appliances with

limited battery life to big-box electronics that consume large amounts

of increasingly expensive power. Power reduction methods are now

applied throughout the chip design flow from architectural design

through RTL implementation to physical design.

Formal Low-power VERIFICATION of Power-aware Designs

The Cadence® JasperGold® Low-power Verification (LPV) App works with other JasperGold Apps to overcome verification challenges posed by power-aware chip design, including power management, IP use and re-use, and DFT circuitry.

30

Embedded Developer

Power-aware Verification Challenges

Power-aware verification must ensure not only that the power intent has been completely and correctly implemented as described in the Unified Power Format (UPF) specification [1] or the Common Power Format (CPF) specification [2], but also that the functional design continues to operate correctly after the insertion of power management circuitry.

Power estimates are made at several stages in the design flow, with accurate estimates becoming available only after physical layout. Consequently, design changes such as RTL modifications and layout reworks ripple back and forth through the design flow. This iterative power optimization increases verification and debug effort, project risk, and cost. The objective is to achieve the target power consumption while limiting the cost of doing so.

The Power Management Scheme

Initially, an implementation-independent functional specification is devised to meet product requirements. The functionality is then partitioned across hardware and software. An initial power management scheme can be devised at this architectural level, but it defines only which functionality can or should be deactivated for any given use case, not how it should be deactivated.

The functionality is then implemented in RTL, making extensive use and reuse of pre-design silicon IP blocks, together with new RTL blocks. Some of these blocks may be under the control of software stacks.

At this stage, decisions are made about how functionality should be deactivated, using a multiplicity of power reduction methods to achieve the requisite low-power characteristics. These decisions must comprehend both hardware- and software-controlled circuit activity. Common power management methods include:

> Clock gating

> Dynamic voltage-frequency scaling (DVFS)

> Power shut-off

> Memory access optimizations

> Multiple supply voltages

> Substrate biasing

These early-stage power management decisions can be influenced by a physical floorplan, but they do not—and cannot— comprehend the final partitioning at P& R, where accurate power estimates are made. Consequently, the power management scheme can be modified and must be re-verified after P& R.

Clearly, the power management scheme is a moving target, and requires iterative design optimization, verification, and re-verification at every stage of the design flow—including architecture, RTL implementation, and physical design.

Additional Complications

Implementing any scheme is often subject to significant additional complications, such as the impact of IP use and re-use and of DFT circuitry.

A given IP block can implement several functions, each of which can be or must be switched off independently of the others, for example, by adding interfaces to the power-control registers or signals. These functions can be problematic in the case of third-party IP, where (often) only black box information about its behavior is available. In any case, the verification challenge now includes re-verifying the redesigned IP block(s) as well as verifying the power management circuitry.

In order to minimize test pattern count and test time, conventional DFT assumes that the whole chip operates with all functions up and running. That is how it operates not only on the tester, but also in field diagnostics. With power-aware design, DFT circuitry must now mesh with the design’s power management scheme in order to avoid excessive power consumption and unnecessary yield loss at final test.

Power-Aware Verification Requirements

Functional analysis, optimization, and verification throughout the design flow, complicated by inadequate visibility of third-party IP white-box functionality, mandates the following five principal requirements for implementing and verifying a low-power scheme:

> Sufficiently accurate power estimates using representative waveforms, both pre- and post-route

> Accurate visibility and analysis of the white box behavior of third-party IP prior to its modification and reuse

> Deployment and ongoing optimization and verification of appropriate power reduction techniques, both pre- and post-integration

> Exhaustive functional verification at the architectural and RT levels, both before and after the deployment of power optimization circuitry

> Verification of hardware functionality compliance with software control sequences

The first requirement can be addressed with commercially available tools that use simulation and formal methods. The rest of this section deals with the remaining requirements.


TECH REPORT

31

Power-aware Verification Challenges

Power-aware verification must ensure not only that the power intent has been completely and correctly implemented as described in the Unified Power Format (UPF) specification [1] or the Common Power Format (CPF) specification [2], but also that the functional design continues to operate correctly after the insertion of power management circuitry.

Power estimates are made at several stages in the design flow, with accurate estimates becoming available only after physical layout. Consequently, design changes such as RTL modifications and layout reworks ripple back and forth through the design flow. This iterative power optimization increases verification and debug effort, project risk, and cost. The objective is to achieve the target power consumption while limiting the cost of doing so.

The Power Management Scheme

Initially, an implementation-independent functional specification is devised to meet product requirements. The functionality is then partitioned across hardware and software. An initial power management scheme can be devised at this architectural level, but it defines only which functionality can or should be deactivated for any given use case, not how it should be deactivated.

The functionality is then implemented in RTL, making extensive use and reuse of pre-design silicon IP blocks, together with new RTL blocks. Some of these blocks may be under the control of software stacks.

At this stage, decisions are made about how functionality should be deactivated, using a multiplicity of power reduction methods to achieve the requisite low-power characteristics. These decisions must comprehend both hardware- and software-controlled circuit activity. Common power management methods include:

> Clock gating

> Dynamic voltage-frequency scaling (DVFS)

> Power shut-off

> Memory access optimizations

> Multiple supply voltages

> Substrate biasing

These early-stage power management decisions can be influenced by a physical floorplan, but they do not—and cannot— comprehend the final partitioning at P& R, where accurate power estimates are made. Consequently, the power management scheme can be modified and must be re-verified after P& R.


Additional Complications

Implementing any scheme is often subject to significant additional complications, such as the impact of IP use and re-use and of DFT circuitry.

A given IP block can implement several functions, each of which can be or must be switched off independently of the others, for example, by adding interfaces to the power-control registers or signals. These functions can be problematic in the case of third-party IP, where (often) only black box information about its behavior is available. In any case, the verification challenge now includes re-verifying the redesigned IP block(s) as well as verifying the power management circuitry.

In order to minimize test pattern count and test time, conventional DFT assumes that the whole chip operates with all functions up and running. That is how it operates not only on the tester, but also in field diagnostics. With power-aware design, DFT circuitry must now mesh with the design’s power management scheme in order to avoid excessive power consumption and unnecessary yield loss at final test.

Power-Aware Verification Requirements

Functional analysis, optimization, and verification throughout the design flow, complicated by inadequate visibility of third-party IP white-box functionality, mandates the following five principal requirements for implementing and verifying a low-power scheme:

> Sufficiently accurate power estimates using representative waveforms, both pre- and post-route

> Accurate visibility and analysis of the white box behavior of third-party IP prior to its modification and reuse

> Deployment and ongoing optimization and verification of appropriate power reduction techniques, both pre- and post-integration

> Exhaustive functional verification at the architectural and RT levels, both before and after the deployment of power optimization circuitry

> Verification of hardware functionality compliance with software control sequences

The first requirement can be addressed with commercially available tools that use simulation and formal methods. The rest of this section deals with the remaining requirements.


32

Embedded Developer

As previously indicated, the power management scheme starts at the architectural level, so any available architectural features such as communication protocols must first be verified (see Figure 1).

In the subsequent functional implementation (RTL) flow, low-power management constructs are introduced at different phases in the SoC development, depending upon the data available and the optimizations required. Taking the deployment of power domains as an example, verification must ensure that:

Figure 1. Ongoing power-aware optimization and verification.

Architectural Models

Architectural-level verification

Power Architecture RTL Micro-Architecture

Power DomainImplementation Functional Implementation Software-Controlled

Power Sequences

• Power domains • Clock controls

• UPF/CPF- defined • Pre- and post-integration

• Power estimation • Power optimization scheme • IP use and reuse • Third-party IP exploration and modification

- IP white-box analysis and visualization

- Exhaustive functional verification

- “Before and after” equivalence checking

- Control and status register verification

- X- propagation

- Connectivity verification

Figure 1: Ongoing power-aware optimization and verification


• Normal design functionality is not adversely affected by the addition of power domains and controls. “Before and after” checking is critical.

• A domain recovers the correct power states at the end of the power-switching sequence, and generates no additional Xs at outputs or in given block signals.

• It achieves a high level of coverage of power-up/power-down events, which are very control-intensive operations.

• Switching off a power domain does not break connectivity between IP blocks.

Therefore, taking the RTL model verified prior to the insertion of power management circuitry as the “golden” reference model, power-aware verification requires a combination of:

• Architecture-level verification

• IP white-box functional visualization and analysis

• Exhaustive functional verification

• Sequential equivalence checking

• Control and Status Register (CSR) verification

• X-propagation analysis

• Connectivity checking

Limitations of Traditional Power-Aware Verification

Various tools and approaches are used for power-aware analysis and verification. This patchwork of tools and approaches clearly provides limited analysis and verification capability, and demonstrably achieves inadequate QoR.

Automated structural analysis and limited, manual functional analysis can identify potential opportunities for the use of power management circuitry. Such analysis can assure consistency between the RTL design and the UPF/CPF specification, but cannot verify design correctness.

At the architectural level, power analysis usually is performed manually with spreadsheets.

Power-aware simulation is used at the RTL, but, like conventional simulation, is not exhaustive. This situation is exacerbated by the state space explosion resulting from the insertion of complex power management schemes. It not only significantly degrades simulation performance, but also fails to systematically avoid X optimism and pessimism.

Power-related DRC can enable limited power integrity analysis at the gate level.

www.cadence.com 3

Formal Low-Power Verification of Power-Aware Designs


> Architecture-level verification

> IP white-box functional visualization and analysis

> Exhaustive functional verification

> Sequential equivalence checking

> Control and Status Register (CSR) verification

> X-propagation analysis

> Connectivity checking



Automated structural analysis and limited, manual functional analysis can identify potential opportunities for the use of power management circuitry. Such analysis can assure consistency between the RTL

> Normal design functionality is not adversely affected by the addition of power domains and controls. “Before and after” checking is critical.

> A domain recovers the correct power states at the end of the power-switching sequence, and generates no additional Xs at outputs or in given block signals.

> It achieves a high level of coverage of power-up /power-down events, which are very control-intensive operations.

> Switching off a power domain does not break connectivity between IP blocks.

design and the UPF/CPF specification, but cannot verify design correctness.




Meeting Power-Aware Verification Requirements with JasperGold Apps

The JasperGold power-aware verification flow comprehensively meets power- aware verification requirements with the requisite QoR.

The front-end of the flow is the JasperGold LPV App (see Figure 2), which automatically creates power-aware transformations and automatically generates a power-aware model that identifies power domains, the power supply network and switches, isolation rules, and state retention rules. It does so

The power management scheme starts at the architectural level, so any available architectural features such as communication protocols must first be verified.

TECH REPORT

33

As previously indicated, the power management scheme starts at the architectural level, so any available architectural features such as communication protocols must first be verified (see Figure 1).


Figure 1. Ongoing power-aware optimization and verification.

Architectural Models

Architectural-level verification

Power Architecture RTL Micro-Architecture

Power DomainImplementation Functional Implementation Software-Controlled

Power Sequences

• Power domains • Clock controls

• UPF/CPF- defined • Pre- and post-integration

• Power estimation • Power optimization scheme • IP use and reuse • Third-party IP exploration and modification

- IP white-box analysis and visualization

- Exhaustive functional verification

- “Before and after” equivalence checking

- Control and status register verification

- X- propagation

- Connectivity verification

Figure 1: Ongoing power-aware optimization and verification


• Normal design functionality is not adversely affected by the addition of power domains and controls. “Before and after” checking is critical.

• A domain recovers the correct power states at the end of the power-switching sequence, and generates no additional Xs at outputs or in given block signals.

• It achieves a high level of coverage of power-up/power-down events, which are very control-intensive operations.

• Switching off a power domain does not break connectivity between IP blocks.


• Architecture-level verification

• IP white-box functional visualization and analysis

• Exhaustive functional verification

• Sequential equivalence checking

• Control and Status Register (CSR) verification

• X-propagation analysis

• Connectivity checking



Automated structural analysis and limited, manual functional analysis can identify potential opportunities for the use of power management circuitry. Such analysis can assure consistency between the RTL design and the UPF/CPF specification, but cannot verify design correctness.




www.cadence.com 3



> Architecture-level verification

> IP white-box functional visualization and analysis

> Exhaustive functional verification

> Sequential equivalence checking

> Control and Status Register (CSR) verification

> X-propagation analysis

> Connectivity checking



Automated structural analysis and limited, manual functional analysis can identify potential opportunities for the use of power management circuitry. Such analysis can assure consistency between the RTL

> Normal design functionality is not adversely affected by the addition of power domains and controls. “Before and after” checking is critical.

> A domain recovers the correct power states at the end of the power-switching sequence, and generates no additional Xs at outputs or in given block signals.

> It achieves a high level of coverage of power-up /power-down events, which are very control-intensive operations.

> Switching off a power domain does not break connectivity between IP blocks.

design and the UPF/CPF specification, but cannot verify design correctness.






The front-end of the flow is the JasperGold LPV App (see Figure 2), which automatically creates power-aware transformations and automatically generates a power-aware model that identifies power domains, the power supply network and switches, isolation rules, and state retention rules. It does so

The power management scheme starts at the architectural level, so any available architectural features such as communication protocols must first be verified.

34

Embedded Developer

by parsing and extracting relevant data from the UPF/CPF specification, the RTL code, and any user-defined assertions. It then automatically generates assertions that are used by other JasperGold Apps to verify that the power reduction and management circuitry conforms to the UPF/CPF specification and does not corrupt the original RTL functionality.

Power-aware Model

The resulting power-aware model enables the analysis and verification

> Power-supply network connectivity, to detect power intent errors made when defining the power-supply network.

> Power-aware correctness, ensuring equivalence between a power-aware design and the original RTL when all power domains are continuously on.

LPV-generated Assertions

Examples of assertions automatically generated by the JasperGold LPV App include:

> Ensure that a power domain clock is disabled when the domain’s power supply is switched on or off

> If a power supply net has resolution semantics, there is never more than one active driver

> Ensure that the power supply of retention logic is on when the value of an element is restored from that logic

> Whenever a power domain is powered down, all the isolation conditions related to this power domain are true before, during, and after power shut-off

> No signal is isolated twice with contradictory clamp values

The JasperGold Apps Approach

In contrast to the general purpose, all-in-one formal verification tool approach, the JasperGold Apps approach enables step-wise adoption of formal methods. Each JasperGold App provides all of the tool functionality and formal methodology necessary to perform its

intended application-specific task. This approach requires design teams to acquire only the expertise necessary for the particular task at hand, and at a pace that suits the project requirements and user expertise.

Providing an empirical measurement on the effectiveness and progress of the formal verficiation, the JasperGold Design Coverage Verification (COV) App takes in the user’s RTL, assertion properties, and constraint properties and outputs a textual and GUI-based report showing how aspects of the DUT were verified by the formal analysis. These reports how lines of code (“statement coverage”), conditional statements (“branch coverage”), and functional coverage points that were exercised.

The JasperGold Formal Property Verification (FPV) App performs exhaustive verification of (a) all RTL functionality before the insertion of power management circuitry, and (b) the power management circuitry itself. For example, it analyzes and verifies power sequencing both during block design and after integration, including sequence safety such as clock deactivation, block isolation, and power down, as well as state correctness.

The JasperGold Control and Status Register (CSR) Verification App verifies that the design complies with the CSR specification, and that the value read from a register is always correct, both before and after power management insertion.

Figure 2. Jasper Gold power-aware verification flow.



The front-end of the flow is the JasperGold LPV App (see Figure 2), which automatically creates power-aware trans-formations and automatically generates a power-aware model that identifies power domains, the power supply network and switches, isolation rules, and state retention rules. It does so by parsing and extracting relevant data from the UPF/CPF specification, the RTL code, and any user-defined assertions. It then automatically generates assertions that are used by other JasperGold Apps to verify that the power reduction and management circuitry conforms to the UPF/CPF specification and does not corrupt the original RTL functionality.

JasperGold LPV App

Assertions

Bugs

Optimization

Status

JasperGold Architecture Modeling (ARCH) App

JasperGold COV App

JasperGold SEC App

JasperGold FPV App

JasperGold CONN App

JasperGold CSR App

JasperGold XPROP App

CPF/UPF RTLUser-Defined

Assertions

• Power-aware internal model generation • Assertion inference

Figure 2: Jasper Gold power-aware verification flow

Power-aware model

The resulting power-aware model enables the analysis and verification of a wide-range of power management characteristics, for example:

• Power-domain correctness, such as the absence (or otherwise) of clock glitches and correct operation of reset logic

• Power state table consistency, analyzing all possible power-state transitions and detecting illegal ones

• Retention cell verification, validating the integrity of saved data in all power states.

• Power-supply network connectivity, to detect power intent errors made when defining the power-supply network

• Power-aware correctness, ensuring equivalence between a power-aware design and the original RTL when all power domains are continuously on

LPV-generated assertions


• Ensure that a power domain clock is disabled when the domain’s power supply is switched on or off

• If a power supply net has resolution semantics, there is never more than one active driver

• Ensure that the power supply of retention logic is on when the value of an element is restored from that logic

• Whenever a power domain is powered down, all the isolation conditions related to this power domain are true before, during, and after power shut-off

• No signal is isolated twice with contradictory clamp values

www.cadence.com 4


of a wide-range of power management characteristics, for example:

> Power-domain correctness, such as the absence (or otherwise) of clock glitches and correct operation of reset logic

> Power state table consistency, analyzing all possible power-state transitions and detecting illegal ones

> Retention cell verification, validating the integrity of saved data in all power states.

Each JasperGold App provides all of the tool functionality and formal methodology necessary to perform its intended application-specific task.

TECH REPORT

35

by parsing and extracting relevant data from the UPF/CPF specification, the RTL code, and any user-defined assertions. It then automatically generates assertions that are used by other JasperGold Apps to verify that the power reduction and management circuitry conforms to the UPF/CPF specification and does not corrupt the original RTL functionality.

Power-aware Model

The resulting power-aware model enables the analysis and verification

> Power-supply network connectivity, to detect power intent errors made when defining the power-supply network.

> Power-aware correctness, ensuring equivalence between a power-aware design and the original RTL when all power domains are continuously on.

LPV-generated Assertions


> Ensure that a power domain clock is disabled when the domain’s power supply is switched on or off

> If a power supply net has resolution semantics, there is never more than one active driver

> Ensure that the power supply of retention logic is on when the value of an element is restored from that logic

> Whenever a power domain is powered down, all the isolation conditions related to this power domain are true before, during, and after power shut-off

> No signal is isolated twice with contradictory clamp values

The JasperGold Apps Approach

In contrast to the general purpose, all-in-one formal verification tool approach, the JasperGold Apps approach enables step-wise adoption of formal methods. Each JasperGold App provides all of the tool functionality and formal methodology necessary to perform its

intended application-specific task. This approach requires design teams to acquire only the expertise necessary for the particular task at hand, and at a pace that suits the project requirements and user expertise.

Providing an empirical measurement on the effectiveness and progress of the formal verficiation, the JasperGold Design Coverage Verification (COV) App takes in the user’s RTL, assertion properties, and constraint properties and outputs a textual and GUI-based report showing how aspects of the DUT were verified by the formal analysis. These reports how lines of code (“statement coverage”), conditional statements (“branch coverage”), and functional coverage points that were exercised.

The JasperGold Formal Property Verification (FPV) App performs exhaustive verification of (a) all RTL functionality before the insertion of power management circuitry, and (b) the power management circuitry itself. For example, it analyzes and verifies power sequencing both during block design and after integration, including sequence safety such as clock deactivation, block isolation, and power down, as well as state correctness.

The JasperGold Control and Status Register (CSR) Verification App verifies that the design complies with the CSR specification, and that the value read from a register is always correct, both before and after power management insertion.

Figure 2. Jasper Gold power-aware verification flow.



The front-end of the flow is the JasperGold LPV App (see Figure 2), which automatically creates power-aware trans-formations and automatically generates a power-aware model that identifies power domains, the power supply network and switches, isolation rules, and state retention rules. It does so by parsing and extracting relevant data from the UPF/CPF specification, the RTL code, and any user-defined assertions. It then automatically generates assertions that are used by other JasperGold Apps to verify that the power reduction and management circuitry conforms to the UPF/CPF specification and does not corrupt the original RTL functionality.

JasperGold LPV App

Assertions

Bugs

Optimization

Status

JasperGold Architecture Modeling (ARCH) App

JasperGold COV App

JasperGold SEC App

JasperGold FPV App

JasperGold CONN App

JasperGold CSR App

JasperGold XPROP App

CPF/UPF RTLUser-Defined

Assertions

• Power-aware internal model generation • Assertion inference

Figure 2: Jasper Gold power-aware verification flow

Power-aware model

The resulting power-aware model enables the analysis and verification of a wide-range of power management characteristics, for example:

• Power-domain correctness, such as the absence (or otherwise) of clock glitches and correct operation of reset logic

• Power state table consistency, analyzing all possible power-state transitions and detecting illegal ones

• Retention cell verification, validating the integrity of saved data in all power states.

• Power-supply network connectivity, to detect power intent errors made when defining the power-supply network

• Power-aware correctness, ensuring equivalence between a power-aware design and the original RTL when all power domains are continuously on

LPV-generated assertions


• Ensure that a power domain clock is disabled when the domain’s power supply is switched on or off

• If a power supply net has resolution semantics, there is never more than one active driver

• Ensure that the power supply of retention logic is on when the value of an element is restored from that logic

• Whenever a power domain is powered down, all the isolation conditions related to this power domain are true before, during, and after power shut-off

• No signal is isolated twice with contradictory clamp values

www.cadence.com 4


of a wide-range of power management characteristics, for example:

> Power-domain correctness, such as the absence (or otherwise) of clock glitches and correct operation of reset logic

> Power state table consistency, analyzing all possible power-state transitions and detecting illegal ones

> Retention cell verification, validating the integrity of saved data in all power states.

Each JasperGold App provides all of the tool functionality and formal methodology necessary to perform its intended application-specific task.

www.cadence.com/cadence/contact_us

www.cadence.com

36

Embedded Developer

References and Further Information

[1] 1801-2013 - IEEE Standard for Design and Verification of Low-Power Integrated Circuits. Available at http://standards.ieee.org /findstds /standard /1801-2013.html.

[2] Si2 Common Power Format (CPF) Specification. Available at http://w w w.si2.org /?page = 811.

To learn more about Cadence JasperGold Apps, contact your local sales office at http://www.cadence.com/cadence/contact_us.

Cadence Design Systems enables global electronic design innovation and plays an essential role in the creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design and verify today’s mobile, cloud and connectivity applications. www.cadence.com

The JasperGold Sequential Equivalence Checking (SEC) App verifies the equivalence of blocks before and after power management circuitry is inserted, as well as those blocks subject to late-stage modification. In addition, it verifies that memory optimizations do not compromise functionality. For example, where a memory is replaced by two low-power memories with a wrapper, the JasperGold SEC App verifies that the two memory models are equiv- alent to the original memory.

The JasperGold X-Propagation App (XPROP) analyzes and verifies Xs at block outputs caused by power-down, and compares differences in output X behavior before and after application of the UPF/CPF specification.

The JasperGold Connectivity (CONN) Verification App exhaustively verifies RTL connections at the block and unit level, and after integration.

Conclusion

The Cadence JasperGold power-aware formal verification flow enables exhaustive analysis and verification of power-aware designs, achieving QoR superior to those designs produced by the traditional ad hoc patchwork of tools and approaches. Starting with the JasperGold LPV App to automatically generate a power-aware model and the appropriate assertions, the flow leverages an expandable range of additional JasperGold Apps, each targeted at a particular task. Design teams can deploy JasperGold Apps as needed and acquire expertise in a low-risk, step-wise fashion.

The Cadence JasperGold power-aware formal verification flow enables exhaustive analysis and verification of power-aware designs, achieving QoR superior to those designs produced by the traditional ad hoc patchwork of tools and approaches.

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38

Embedded Developer

The bike is a collaboration of three

German technology companies: The

Fritzmeier Group, M1-Sportechnik

and TQ-Group. The sleek, ultra-

modern frame of the bike is

manufactured by the Fritzmeier

Group, a company noted for their

carbon fiber designs in such products

as the BMWi8, skis, surfboards,

and the first carbon mountain bike,

manufactured for M1-Sportechnique,

the “Magma Red Hot.” The bike is

assembled by M1 with the finest

components, including hydraulic disc

brakes, 10-speed Shimano gears, and

a NuVinci (roller-based) continuously

variable transmission.



The M1 Sporttechnik Spitzing

is the fastest bike on two

wheels you can legally own—

outside of a motorcycle.

COVER STORY

39

The bike is a collaboration of three

German technology companies: The

Fritzmeier Group, M1-Sportechnik

and TQ-Group. The sleek, ultra-

modern frame of the bike is

manufactured by the Fritzmeier

Group, a company noted for their

carbon fiber designs in such products

as the BMWi8, skis, surfboards,

and the first carbon mountain bike,

manufactured for M1-Sportechnique,

the “Magma Red Hot.” The bike is

assembled by M1 with the finest

components, including hydraulic disc

brakes, 10-speed Shimano gears, and

a NuVinci (roller-based) continuously

variable transmission.



The M1 Sporttechnik Spitzing

is the fastest bike on two

wheels you can legally own—

outside of a motorcycle.

40

Embedded Developer

The heart of the e-Bike is TQ’s revolutionary Pin-Drive—an electric motor that is capable of driving from 0-45 mph in a screaming 7 seconds. The hollow core of the drive means that the pedals and gears can run through the center of the motor, saving valuable space.

Power to Spare

Powering the Spitzing motor is a lithium manganese cobalt battery pack that’s mounted below the downtube for the lowest possible center of gravity and superb front-to-rear balance. The cell configuration inside offers 48-volts of

power, enabling higher wattage motor settings, which improves electrical efficiency on all models. With 18.4 amp hours of capacity, the Spitzing is capable of long distance riding—but it’s tricky to say just how far (due to the variable riding conditions that an all-terrain e-bike might encounter). However, at the lowest level of assist on relatively flat paved surfaces, this bike could get close to 100 miles of range—and that’s incredible for an e-bike. Since this is a true pedelec—meaning you can opt to use just foot-pounds or leg muscles, with a little effort, you can extend the distance for quite some time.

The motor is the Heart of the bike

The hollow shaft motor and patented pin-ring drive from TQ-Group is the heart of the bike and the secret to its unmatched performance.

For e-bikes, the pin-ring drive provides:

1. Above-average power density and high single-stage reduction

2. Rotationally symmetrical and compact dimensions— e-drive, gear, sensors and power electronics in single unit

3. Low weight and noise

combines a high-torque curve and power density relative to the weight and installation space. This means that not only does this motor generate twice the power of any motor in the industry, but it is half the size and weight of comparable motors—making it an ideal solution on an e-bike, (where weight and size are critical).

The motor is also ideal for applications such as robotics for the medical and military industries, where power and precision, and lightweight and small form factors are requirements.

RoboDrive was developed by the Institute for Robotics and Mechatronics of the German Aerospace Center (DLR). This technology, patented by TQ-Systems,

COVER STORY

41

The heart of the e-Bike is TQ’s revolutionary Pin-Drive—an electric motor that is capable of driving from 0-45 mph in a screaming 7 seconds. The hollow core of the drive means that the pedals and gears can run through the center of the motor, saving valuable space.

Power to Spare

Powering the Spitzing motor is a lithium manganese cobalt battery pack that’s mounted below the downtube for the lowest possible center of gravity and superb front-to-rear balance. The cell configuration inside offers 48-volts of

power, enabling higher wattage motor settings, which improves electrical efficiency on all models. With 18.4 amp hours of capacity, the Spitzing is capable of long distance riding—but it’s tricky to say just how far (due to the variable riding conditions that an all-terrain e-bike might encounter). However, at the lowest level of assist on relatively flat paved surfaces, this bike could get close to 100 miles of range—and that’s incredible for an e-bike. Since this is a true pedelec—meaning you can opt to use just foot-pounds or leg muscles, with a little effort, you can extend the distance for quite some time.

The motor is the Heart of the bike

The hollow shaft motor and patented pin-ring drive from TQ-Group is the heart of the bike and the secret to its unmatched performance.

For e-bikes, the pin-ring drive provides:

1. Above-average power density and high single-stage reduction

2. Rotationally symmetrical and compact dimensions— e-drive, gear, sensors and power electronics in single unit

3. Low weight and noise

combines a high-torque curve and power density relative to the weight and installation space. This means that not only does this motor generate twice the power of any motor in the industry, but it is half the size and weight of comparable motors—making it an ideal solution on an e-bike, (where weight and size are critical).

The motor is also ideal for applications such as robotics for the medical and military industries, where power and precision, and lightweight and small form factors are requirements.

RoboDrive was developed by the Institute for Robotics and Mechatronics of the German Aerospace Center (DLR). This technology, patented by TQ-Systems,

42

Embedded Developer

The Cleanmobile Package

The motor, the pin-drive, the component devices, and wire harness to assemble the e-bike are all packaged under the trademark Cleanmobile. Under the Cleanmobile brand, TQ develops and produces customer-specific drive systems and components for pedelecs, e-bikes, and electric cargo vehicles.

The bundle includes the following components (shown here on an Audi demo bike):

1. Electric pin drive

2. Customer-specific lithium ion battery

3. Cable harness

4. Display

5. Speed sensor

6. Torque sensor

Off-road Trials

The video showing one of Germany’s premier all-terrain riders on an M1 Spitzing can be seen here: https://www.youtube.com/watch?v=WMgp-4HtkPg

Buy Your Own Spitzing— Or Just the Motor

You can be the first on one your block to leave the other cyclists in the dust for a small price: The M1 Sporttechnik Spitzing is available in the US for around $9000 (which is quite reasonable, given that similar carbon-based road bikes are priced in this range—without a motor). For more information and to locate a dealer near you: http://m1-sporttechnik.info/en/

If you want to build your own, the RoboDrive motors and the

cleanmobile packages are available in North America from Convergence

Promotions. Contact [email protected] for more

information on how you can design it into your next bike—or robot.

3

4

56

1

2

https://www.youtube.com/watch?v=WMgp-4HtkPg

http://m1-sporttechnik.info/en/

COVER STORY

43

The Cleanmobile Package

The motor, the pin-drive, the component devices, and wire harness to assemble the e-bike are all packaged under the trademark Cleanmobile. Under the Cleanmobile brand, TQ develops and produces customer-specific drive systems and components for pedelecs, e-bikes, and electric cargo vehicles.

The bundle includes the following components (shown here on an Audi demo bike):

1. Electric pin drive

2. Customer-specific lithium ion battery

3. Cable harness

4. Display

5. Speed sensor

6. Torque sensor

Off-road Trials

The video showing one of Germany’s premier all-terrain riders on an M1 Spitzing can be seen here: https://www.youtube.com/watch?v=WMgp-4HtkPg

Buy Your Own Spitzing— Or Just the Motor

You can be the first on one your block to leave the other cyclists in the dust for a small price: The M1 Sporttechnik Spitzing is available in the US for around $9000 (which is quite reasonable, given that similar carbon-based road bikes are priced in this range—without a motor). For more information and to locate a dealer near you: http://m1-sporttechnik.info/en/

If you want to build your own, the RoboDrive motors and the

cleanmobile packages are available in North America from Convergence

Promotions. Contact [email protected] for more

information on how you can design it into your next bike—or robot.

3

4

56

1

2



http://m1-sporttechnik.info/en/

Click here

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