JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.3, NO. 3, SEPTEMBER, 2003 153 Manuscript received August 27, 2003; revised September 17, 2003. IBM Semiconductor Research and Development Center (SRDC) Essex Junction, Vermont 05452 Tel : 802-769-8368, Fax: 802-769-9659, E-mail: [email protected]Electrostatic Discharge (ESD) and Failure Analysis: Models, Methodologies and Mechanisms for CMOS, Silicon On Insulator and Silicon Germanium Technologies Steven H. Voldman Abstract− Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed. Index Terms− Reliability, Electrostatic, Discharge, CMOS, SOI, SiGe I. INTRODUCTION Failure analysis is invaluable in the learning process of ESD protection design and development. Today, there is still no design tool which will predict ESD protection levels in a semiconductor chip for human body model (HBM), machine model (MM) and charged device model (CDM) simulation tests. ESD prediction is a difficult task because ESD phenomena spans both on microscopic and macroscopic physical scale. ESD phenomena involves semiconductor device, circuit, and package effects and their interactions. Although significant resources have been placed on semiconductor design tools, ESD analysis and prediction remains significantly behind other circuit tool development. As a result, failure analysis assist the design and development process by providing visualization of the mechanisms leading to ESD failure. In this paper, we will focus on models, methodologies and mechanisms associated with ESD failures and failure analysis by use of examples from semiconductor technologies. The scope of the paper will show examples of failure analysis and characterization of CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies. In our discussion, we will present how failure analysis can assist in providing insight into achieving ESD robust implementations. 2. FAILURE MODELS ESD failure analytical models were established to provide predictive capability for semiconductor devices. ESD failure models typically are based on the relationship of the thermal physics and pulse parameters [1-5] or statistical analysis [6-9]. ESD physical models of devices explored the relationship between the ESD pulse and the thermal transport and its role in prediction in the power-to-failure. Wunsch focused on the time scale where the thermal diffusion time is on the order of the pulse width demonstrating a 1/t f 1/2 dependence [1]. Tasca analyzed the power-to-failure, P f , in a spherical source. Tasca explored the dependence on the power-to- failure when the pulse is significantly smaller than the
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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.3, NO. 3, SEPTEMBER, 2003
153
Manuscript received August 27, 2003; revised September 17, 2003. IBM Semiconductor Research and Development Center (SRDC)
Electrostatic Discharge (ESD) and Failure Analysis: Models, Methodologies and Mechanisms for CMOS,
Silicon On Insulator and Silicon Germanium Technologies
Steven H. Voldman
Abstract−Failure analysis is fundamental to the
design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.
Index Terms−Reliability, Electrostatic, Discharge,
CMOS, SOI, SiGe
I. INTRODUCTION
Failure analysis is invaluable in the learning process
of ESD protection design and development. Today, there
is still no design tool which will predict ESD protection
levels in a semiconductor chip for human body model
(HBM), machine model (MM) and charged device
model (CDM) simulation tests. ESD prediction is a
difficult task because ESD phenomena spans both on
microscopic and macroscopic physical scale. ESD
phenomena involves semiconductor device, circuit, and
package effects and their interactions. Although
significant resources have been placed on semiconductor
design tools, ESD analysis and prediction remains
significantly behind other circuit tool development. As a
result, failure analysis assist the design and development
process by providing visualization of the mechanisms
leading to ESD failure. In this paper, we will focus on
models, methodologies and mechanisms associated with
ESD failures and failure analysis by use of examples
from semiconductor technologies. The scope of the
paper will show examples of failure analysis and
characterization of CMOS, silicon-on-insulator (SOI)
and silicon germanium (SiGe) technologies. In our
discussion, we will present how failure analysis can
assist in providing insight into achieving ESD robust
implementations.
2. FAILURE MODELS
ESD failure analytical models were established to
provide predictive capability for semiconductor devices.
ESD failure models typically are based on the
relationship of the thermal physics and pulse parameters
[1-5] or statistical analysis [6-9]. ESD physical models
of devices explored the relationship between the ESD
pulse and the thermal transport and its role in prediction
in the power-to-failure. Wunsch focused on the time
scale where the thermal diffusion time is on the order of
the pulse width demonstrating a 1/tf1/2 dependence [1].
Tasca analyzed the power-to-failure, Pf, in a spherical
source. Tasca explored the dependence on the power-to-
failure when the pulse is significantly smaller than the
STEVEN H. VOLDMAN : ELECTROSTATIC DISCHARGE (ESD) AND FAILURE ANALYSIS: MODELS, METHODOLOGIES… 154
pulse width, demonstrating an adiabatic dependence with
a 1/tf form [2]. Tasca also showed that as the pulse width
is much greater than the thermal diffusion time, the
power-to-failure is time independent. Today, the work of
Tasca and Wunsch-Bell together are integrated into a
single model to analyze the power-to-failure over all
time regimes. Arkhipov, Astvaturyan, Godovsyn, and
Rudenko developed a model assuming the discharge
follows a cylindrical discharge phenomenon [4].
( )[ ]
+
−=
ππ
π4
ln42ln
4
Dbft
ToTcKafP
Dwyer also extended the Wunsch-Bell model by
addressing the three dimensional nature of the thermal
transport as three different thermal diffusion time scales
ta, tb, and tc [5]. The work of Arkhipov et al influenced
the direction of the Dwyer model by the introduction of
the logarithm term.
( )ft
oTcTpMCfP
−=
( ) ( )2ctft
oTcTpCKabPf
−−
=ρπ
( )( ) ( )b
cbtft
oTcTKafP
−+−=
2ln
4π
( )
ftat
b
c
b
aoTcTKa
Pf
−−+
−=
22ln
2π
Another method of prediction is from a statistical
approach. For ESD field failure prediction, the power-to-
failure distribution can be compared to the actual pulse
power distribution [9]. Assuming a Gaussian distribution
of the design parameters, a probability distribution
function can be defined for the power-to-failure.
−−=
221exp
2
1)(
pSfPfP
pSfPfPf π
where the power-to-failure, Pf, is the random variable
and mean power-to-failure <Pf>, and standard deviation,
Sp. The standard deviation can be expressed as
{ }212
1
1
1
−
−= ∑
=
N
ifP
ifP
NpS
The net field failure is the cumulative distribution
function of the probability of the pulse power is greater
than the power-to-failure of the device. Models have
been developed by Alexander [7], Enlow [8], and Pierce-
Mason [9] to provide predictive ESD results in
semiconductor chips. Pierce and Mason applied this
concept by assuming a Wunsch-Bell time dependence as
the probability distribution and addressed dimensional
variation as cause of the statistical variation .
Although these analytical and statistical models exist
in the industry, a significant amount of ESD analysis
today relies on failure analysis. The existence of the
models, both analytical and statistical, has not assisted in
the prediction and assurance needed to achieve ESD
results. As a result, failure analysis plays a fundamental
role in achieving successful ESD results. Failure analysis
combined with other methodologies and techniques is
key to the ESD verification and learning process.
3. FAILURE ANALYSIS AND HEURISTIC DESIGN METHODOLOGY USING DESIGN
SYMMETRY
A goal of designing ESD protection networks and
ESD-robust circuits is to provide uniform current
distribution throughout a device. This can be achieved
using three dimensional (3-D) electro-thermal device
simulation [10]. Although 2-D and 3-D electro-thermal
semiconductor device simulators exist, today, most ESD
networks are still developed experimentally. The primary
reason is the availability, development time, calibration
effort and accuracy of simulation tools. As a result,
experimental design and failure analysis plays a key role
in the ESD design process today. As a methodology of
developing ESD protection networks, it is superior to use
intuition, design symmetry, and failure analysis as a
means of development of a good ESD protection
network. Our intuition teaches us, as a first step, that
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.3, NO. 3, SEPTEMBER, 2003
155
Fig. 1. Probability distribution functions of the ESD pulse
power and the power-to-failure of a component. Integration
over the cross-hatched area provides the total failure rate.
current uniformity will exist when design symmetry is
self-evident in a design. Hence by providing a design
whose physical layout embodies design symmetry on all
design levels, it would makes sense that current
uniformity will occur. Failure analysis plays a key role in
verifying the intuition of the ESD engineer in this first-
cut assumption. In reality, there are many reasons this
heuristic method is flawed. First, the actual processed
on-wafer does not always represent the design level
dimensions and process-induced asymmetry can be
established that influence the ESD results. Second, it is
hard to anticipate three-dimensional electro-thermal
effects. Third, while intuition helps us with visualizing
the physical layout symmetry, the “physical layout
symmetry” may not be equivalent to the “electrical
symmetry” or “electro-thermal symmetry”. Failure
analysis plays a key role in correcting intuition and
provides bridging from the layout to the understanding
of the electrical and thermal response of a device or
circuit network.
The FA damage pattern itself and its distribution
throughout the ESD network can be used as a “efficiency
factor” or ESD metric. In actuality, a device which has a
significant percentage of the area as damaged,
demonstrates the ability to utilize the maximum
percentage of the silicon area for providing ESD
protection. The damage pattern symmetry also is an
indicator of the ability to achieve current uniformity and
a measure of good ESD design practices.
4. FAILURE ANALYSIS METHODOLOGY AND
ELECTROTHERMAL SIMULATION
Using a heuristic understanding of the design layout,
failure analysis followed by electro-thermal simulation
can provide a higher intuition allowing the ESD designer
bridge from the physical to the electro-thermal results.
Failure patterns can teach the regions of peak thermal
heating and failure [10, 11]. Electro-thermal device
simulation can help understand the location and the root
cause of the ESD failure. As an example, the corner of
an shallow trench isolation (STI) bound p+ diffusion/n-
well diode was failing on the diffusion-to-STI corner.
Using a scanning electron microscope (SEM), an
emission microscope (EMMI) tool (Figure 2), and a
(a) (b)
Fig. 2. Emission microscope (EMMI) tool photon map of a p+ diode structure pre-ESD stress.
STEVEN H. VOLDMAN : ELECTROSTATIC DISCHARGE (ESD) AND FAILURE ANALYSIS: MODELS, METHODOLOGIES… 156
Fig. 3. Kelvin probe force microscope (KPFM) topography
image of p+ diode post-ESD stress.
Fig. 4. Electrothermal Simulation Results.
Kelvin force probe microscope (KPFM) atomic force
tool (Figure 3), the ESD damage was imaged. The SEM
provided a bird’s eye view of the ESD device after
removal of the metal films. The EMMI tool provides a
photon-mapping of the ESD structure during direct
current (d.c.) measurement. The KPFM atomic force tool
provided both a topographic as well as electrical
potential mapping. Using a 3-D semiconductor electro-
thermal tool FIELDAY III, our analysis demonstrated
and verified that the peak lattice temperatures was at the
end of the p+ diode implant [10].
Although 3-D electro-thermal device simulation is
possible, it is extremely sensitive to the electrical and
thermal Von Neumann and Dirichlet boundary
conditions, mesh quality and mesh densification
techniques. Even with good refinements, heat capacity
and thermal conductivity models are not well
characterized or calibrated in the high temperature
regimes. Independent of the calibration and model fitting,
FA combined with the electro-thermal simulation
establishes good intuition and a good methodology for
the design of ESD protection networks and circuits.
5. FAILURE ANALYSIS METHODS AS A MEANS OF ESD DEVICE OPERATION VERIFICATION
Failure analysis can be used as a means of verifying
ESD device operation. At times, it is not clear to all ESD
engineers how an ESD device is operating or the current
paths. Failure analysis is a key means of verification of
the current transfer based on the location of the damage
on given shapes, or between shapes. The FA damage is a
verification of current transfer and clearly can show
device operation and the path of current transfer. For
example, in integrated cascode MOSFET, the electrical
schematics would not explain the nature of the failure
mechanism. Early measurements of cascode MOSFETs
anticipated that the MOSFET snapback voltage would
serve as the sum of the two MOSFETs. Experimental
results verified that integrated series cascode MOSFET
was significantly less than the sum of the two MOSFETs.
It is clear from the failure analysis that the interaction for
cascaded MOSFET second breakdown occurs in the
same local region, providing a response which behaved
as a single MOSFET. From the AFM failure analysis, it
is clear that the parasitic bipolar transistor is interactive
locally as one device. The AFM failure analysis results
then shows that treating the series cascode MOSFET
structure can not be modeled as two independent
components. Since this early work, the issue of analysis
of series cascode MOSFETs has had increased interest in
mixed-voltage interface networks in microprocessors
and peripheral circuits.
6. FAILURE ANALYSIS AND ESD TESTING METHODOLOGY
For failure analysis to be effective for ESD learning, a
good ESD testing methodology and strategy is needed to
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.3, NO. 3, SEPTEMBER, 2003
157
maximize the ESD learning on ESD networks, circuits
and products. The ESD testing methodology is key in
providing valuable correlation between the ESD failure
and the failure mechanism. In IBM, the testing and
failure analysis strategy, developed by Gross and
Voldman [12], all pins are tested to a given power rail.
Second, each pin is tested from zero volts on the source,
and step stressed in small increments. It is also key that
all pins are tested to failure. The failure distribution
function of all the pins are plotted and evaluated to
determine the “mean failure distribution”, standard
deviation, and other statistics of the whole chip. In many
corporations, the FA focus is primarily on the worst case
pins. In this methodology, the failure analysis of the
“good” pins are as important to evaluate as well. This
allows documentation and classification of the pin types,
the failure mechanism and ESD results. This
methodology allows to verify at what level different
failure mechanisms are evident as well as quantify what
mechanisms are occurring in what circuit function. This
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STEVEN H. VOLDMAN : ELECTROSTATIC DISCHARGE (ESD) AND FAILURE ANALYSIS: MODELS, METHODOLOGIES… 166
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Steven Voldman received his MS in electrical engineering from MIT in 1982 and Ph.D. from University of Vermont in 1991. He is a senior scientist at IBM Essex Junction Vermont. Voldman is a pioneer in the ESD studies and he is a ESDA standards committee member and associated with EOS/ESD symposium
for many years and was Chairman in 2001. He has over 100 publications and more than 50 US patents to his credit. Steve Voldman is an IEEE Fellow.