Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 1 VSB ENGINEERING COLLEGE KARUR – 639111 V SEM III Year B.E. MECHANICAL ENGINEERING ELECTRONICS AND MICROPROCESSOR LABORATORY LAB MANUAL Prepared By J. Cyril Robinson Azariah Assistant Professor, ECE & C. Moorthy Lecturer, ECE
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Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 1
VSB ENGINEERING COLLEGE
KARUR – 639111
V SEM III Year B.E. MECHANICAL ENGINEERING
ELECTRONICS AND MICROPROCESSOR LABORATORY
LAB MANUAL
Prepared By
J. Cyril Robinson Azariah
Assistant Professor, ECE
&
C. Moorthy
Lecturer, ECE
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 2
CONTENTS
Exp.
No.
Date Name of the Experiments Page
No.
Marks
Award
Faculty
Sign.
CYCLE I - ELECTRONICS EXPERIMENTS
1.(a) VI Characteristics of PN Junction
Diode
4
1.(b) VI Characteristics of Zener Diode 7
2. Characteristics Study Of Common
Emitter Configuration of a npn type
Bipolar Junction Transistor (BJT)
11
3. Design of an RC Phase Shift Oscillator
Using Opamp IC 741
15
4. Verification and Study of Logic Gates 19
5. Design of Half Adder and Full Adder
Using Logic Gates
26
6. Study and Construction of Flip- Flops
Using Logic Gates
28
CYCLE II - MICROPROCESSOR EXPERIMENTS
7.(a) 8-bit Addition and Subtraction Using
8085 Microprocessor
33
7.(b) 8-bit Multiplication and Division Using
8085 Microprocessor
40
8. Finding Smallest Number and largest
Number from the Array of Numbers
Using 8085 Microprocessor
44
9. Sorting an Array of Numbers in
Ascending and descending Order
Using 8085 Microprocessor
47
10. Transferring Block of Data Using 8085
Microprocessor
51
11. Stepper Motor Interfacing Using 8085
Microprocessor
53
Appendix: 8085 Op-code Sheet
Viva Questions & Answers
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CYCLE I EXPERIMENTS
ELECTRONICS
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Ex. No. 1. (a)
Date:
VI Characteristics of PN Junction Diode
Aim: To plot the VI characteristics of a PN Junction Diode
Apparatus Required:
S.No. Name of the Apparatus Range/Type Quantity
1. Ammeter (0-100)mA
(0-500)µA
1
1
2. Voltmeter (0-1)V
(0-30)V
1
1
3. Resistor 220Ω 1
4. PN Junction Diode 1N4007 1
5. Regulated Power Supply (0-30)V 1
6. Bread-Board - 1
7. Connecting Wires - Few
Procedure:
1. Wire up the circuit shown in circuit diagram of the forward biased diode.
2. Record the voltage across the diode (V) and current (I) through it as a function
of input voltage.
3. Repeat the experiment of the reverse biased diode.
4. Plot the relevant graphs.
5. Plot it along with I-V characteristics of forward biased PN Junction Diode.
Diode Symbol:
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Circuit Diagram:
Forward Biased:
Reverse Biased:
Tabulation:
Forward Bias Reverse Bias
Voltage (VF)
volts
Current (IF)
mA
Voltage (VR)
volts
Current (IR)
µA
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Model Graph:
Theory:
The PN junction region of a Junction Diode has the following important
characteristics:
1) Semiconductors contain two types of mobile charge carriers, Holes and Electrons.
2) The holes are positively charged while the electrons negatively charged.
3) A semiconductor may be doped with donor impurities such as Antimony (N-
type doping), so that it contains mobile charges which are primarily
electrons.
4) A semiconductor may be doped with acceptor impurities such as Boron (P-
type doping), so that it contains mobile charges which are mainly holes.
5) The junction region itself has no charge carriers and is known as the depletion
region.
6) The junction (depletion) region has a physical thickness that varies with the
applied voltage. 7) When a diode is Zero Biased no external energy source is applied and a
natural Potential Barrier is developed across a depletion layer which is
approximately 0.5 to 0.7v for silicon diodes and approximately 0.3 of a volt for
germanium diodes. 8) When a junction diode is Forward Biased the thickness of the depletion
region reduces and the diode acts like a short circuit allowing full current to
flow. 9) When a junction diode is Reverse Biased the thickness of the depletion
region increases and the diode acts like an open circuit blocking any current
flow, (only a very small leakage current).
Result:
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Ex. No. 1. (b)
Date:
VI Characteristics of Zener Diode
Aim: To plot the VI characteristics of a Zener Diode
Apparatus Required:
S.No. Name of the Apparatus Range/Type Quantity
1. Ammeter (0-100)mA
(0-500)µA
1
1
2. Voltmeter (0-1)V
(0-30)V
1
1
3. Resistor 330Ω 1
4. Zener Diode 1N47XX 1
5. Regulated Power Supply (0-30)V 1
6. Bread-Board - 1
7. Connecting Wires - Few
PROCEDURE:
Static characteristics:-
1. Connections are made as per the circuit diagram.
2. The Regulated power supply voltage is increased in steps.
3. The zener current (lz), and the zener voltage (Vz.) are observed and then
noted in the tabular form.
4. A graph is plotted between zener current (Iz) and zener voltage (Vz).
Regulation characteristics:-
1. The voltage regulation of any device is usually expressed as percentage
regulation
2. The percentage regulation is given by the formula
((VNL-VFL)/VFL)X100
VNL=Voltage across the diode, when no load is connected.
VFL=Voltage across the diode, when load is connected.
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3. Connection are made as per the circuit diagram
4. The load is placed in full load condition and the zener voltage (Vz),
Zener current (lz), load current (IL) are measured.
5. The above step is repeated by decreasing the value of the load in steps.
6. All the readings are tabulated.
7. The percentage regulation is calculated using the above formula
OBSERVATIONS:-
Static characteristics:-
S.NO
ZENER
VOLTAGE(VZ)
ZENER CURRENT(I
Z)
Regulation characteristics:-
S.N0 VNL(VOLTS)
VFL (VOLTS)
RL
(KΏ)
%
REGULATION
Diode Symbol:
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Circuit Diagram:
Forward Biased:
Reverse Biased:
Model Graph:
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Theory:
A Zener Diode is a special kind of diode which permits current to flow in the
forward direction as normal, but will also allow it to flow in the reverse direction
when the voltage is above a certain value - the breakdown voltage known as
the Zener voltage.
The Zener voltage of a standard diode is high, but if a reverse current above that
value is allowed to pass through it, the diode is permanently damaged.Zener
diodes are designed so that their zener voltage is much lower - for example just 2.4
Volts. When a reverse current above the Zener voltage passes through a Zener
diode, there is a controlled breakdown which does not damage the diode. The
voltage drop across the Zener diode is equal to the Zener voltage of that diode no
matter how high the reverse bias voltage is above the Zener voltage.
The illustration above shows this phenomenon in a Current vs. Voltage graph. With a
zener diode connected in the forward direction, it behaves exactly the same as a
standard diode - i.e. a small voltage drop of 0.3 to 0.7V with current flowing through
pretty much unrestricted. In the reverse direction however there is a very
small leakage current between 0V and the Zener voltage - i.e. just a tiny amount of
current is able to flow. Then, when the voltage reaches the breakdown voltage (Vz),
suddenly current can flow freely through it.
Result:
a) Static characteristics of zener diode are obtained and drawn.
b) Percentage regulation of zener diode is calculated.
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Ex. No. 2
Date:
Characteristics Study Of Common Emitter Configuration of a npn
type Bipolar Junction Transistor (BJT)
Aim: To plot the input and output characteristics of Bipolar Junction Transistor (BJT)
in Common Emitter mode Configuration and to find the Input Impedance (Ri), Output
Admittance (Ro), Forward Current Gain (hfc) and Reverse Voltage Gain (hrv)
Apparatus Required:
S.No. Name of the Apparatus Range/Type Quantity
1. Ammeter (0-30)mA
(0-500)µA
1
1
2. Voltmeter (0-1)V
(0-10)V
1
1
3. Resistor 330Ω 1
4. Bipolar Junction Transistor
(BJT)
BC107 1
5. Regulated Power Supply (0-30)V 1
6. Bread-Board - 1
7. Connecting Wires - Few
Procedure:
1. Connections are given as per the circuit diagram.
2. Power supplies are switched ON.
3. To determine the input characteristics:
a) VCB is kept constant by using the power supply Vcc.
b) VBE is varied by using the power supply VBB and the corresponding
variations in IB is noted.
c) The above step is repeated for different values of VCB.
4. To determine the output characteristics:
a) IB is kept constant by using the power supply VCC and the corresponding
value in IC is noted.
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b) VCE is varied by using the power supply and the corresponding value in IC is
noted.
c) The above step is repeated for different values of IB.
5. Graph is plotted using the tabulation.
Formulae Used:
Input Impedance ri = ∆VBE/∆IB [Unit – ohm (Ω)]
Output Admittance ro=∆IC /∆VCE [Unit – mho (Ω-1)]
Forward Current Gain hfc=∆IC/∆IB [No Unit]
Reverse Voltage Gain hrv=∆VBE/∆VCE [No Unit]
Circuit Diagram:
THEORY:
A transistor is a three terminal device. The terminals are emitter, base,
collector. In common emitter configuration, input voltage is applied
between base and emitter terminals and out put is taken across the
collector and emitter terminals. Therefore the emitter terminal is common
to both input and output.
The input characteristics resemble that of a forward biased
diode curve. This is expected since the Base-Emitter junction of the
transistor is forward biased. As compared to CB arrangement IB
increases less rapidly with VBE. Therefore input resistance of CE circuit
is higher than that of CB circuit.
The output characteristics are drawn between Ic and VCE at
constant IB. the collector current varies with VCE unto few volts only.
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After this the collector current becomes almost constant, and
independent of VCE. The value of VCE up to which the collector current
changes with V CE is known as Knee voltage. The transistor always
operated in the region above Knee voltage, IC is always constant and is
approximately equal to IB.
The current amplification factor of CE configuration is given by
Β = ∆IC/∆IB
MODEL GRAPHS:
INPUT CHARACTERSTICS:
OUTPUT CHARECTERSTICS:
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PRECAUTIONS:
1. The supply voltage should not exceed the rating of the transistor
2. Meters should be connected properly according to their polarities
RESULT:
1. the input and out put characteristics of a transistor in CE configuration are
Drawn
2. the β of a given transistor is calculated as
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Ex. No. 3
Date:
Design of an RC Phase Shift Oscillator Using Opamp IC 741
Aim: To design an RC phase shift Oscillator using Opamp IC 741
Apparatus Required:
S.No. Name of the Apparatus Range/Type Quantity
1. Op Amp IC 741 1
2. Resistors 1K,
10K,
3
1
3. Resistor (Use Decade
Resistance Box)
290K 1
4. DC Power Supply -12V-0V-+12V 1
5. CRO Digital 1
6. Bread-Board - 1
7. Connecting Wires - Few
IC 741 Pin Diagram:
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Circuit Diagram:
Model Graph:
Observation:
Amplitude Time Period Practical Frequency
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Tabulation:
S.NO
THEORETICAL
FREQUENCY
PRACTICAL
FREQUENCY
OUTPUT VOLTAGE
Design:
The attenuation, B of the three section RC feedback circuit is B = 1/29
Where, B=R1/Rf=1/29. Then Rf=29*R1, R1 = 10*R
and the frequency of oscillation (fo) is given by
Theory:
RC phase shift oscillator is a sinusoidal oscillator used to produce sustained well
shaped sine wave oscillations. It is used for different applications such as local
oscillator for synchronous receivers, musical instruments, study purposes etc. The
main part of an RC phase shift oscillator are an op amp inverting amplifier with its
output fed back into its input using a regenerative feedback RC filter network,
Hence the name RC phase shift oscillator. By varying capacitor, the frequency of
oscillations can be varied. The feedback RC network has a phase shift of 60 degrees
each. Hence total phase shift provided by the three RC network is 180 degrees. The
op amp is connected as inverting amplifier hence the total phase shift around the
loop will be 360 degrees. This condition is essential for sustained oscillations.
Working of RC Phase shift oscillator
The feedback network offers 180 degrees phase shift at the oscillation
frequency, and the op amp is configured as an Inverting amplifier it also
provide 180 degrees phase shift. Hence to total phase shift around the loop is
360=0degrees, it is essential for sustained oscillations.
At the oscillation frequency each of the resistor capacitor filter produces a
phase shift of 60° so the whole filter circuit produces a phase shift of 180°.
The energy storage capacity of capacitor in his circuit produces a noise
voltage which is similar to a small sine wave, it is then amplified using op amp
inverting amplifier.
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By taking feedback, the output sine wave also attenuates 1/29 times while
passing through the RC network, so the gain of inverting amplifier should be
29 in order to keep loop gain as unity.
The unity loop gain and 360 degree phase shift are essential for the sustained
oscillation.
RC Oscillators are stable and provide a well shaped sine wave output with the
frequency being proportional to 1/RC and therefore, a wider frequency range
is possible when using a variable capacitor.
However, RC Oscillators are restricted to frequency applications because at
high frequency the reactance offered by the capacitor is very low so it acts as
a short circuit.
Why it uses 3 RC stages?
Number of RC stages help improve the frequency stability. The total phase
shift introduced by the feedback network is 180 degrees, if we are using N RC
stages each RC section provide 180/N degree phase shift.
1. When 2 RC sections are cascaded, the frequency stability is low. For 3
sections cascaded the phase change rate is high so there is improved
frequency stability. However for 4 RC sections there is an good phase change
rate resulting in the most stable oscillator configuration. But 4 RC sections
increases cost and makes circuit complexity.
Hence phase shift oscillators make use of 3 RC sections in which each section
provides a phase shift of 60 degree. The latter is generally used in high
precision applications where cost is not much regarded and only accuracy
plays a major role.
Procedure:
1. The circuit is constructed as per the given circuit diagram.
2. Switch ON the power supply and observe the output on the CRO (Sine wave
oscillation).
3. Note down the practical frwquency and compare with the theoretical
frequency.
Result:
Thus the RC phase shift oscillator was designed and the output waveform
was obtained. Practical frequency fo=______Hz.
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Ex. No. 4
Date:
Verification and Study of Logic Gates
Aim:
To study the various logic gates and verify its truth table.
Apparatus Required:
S.NO
APPARATUS
QUANTITY
1. Digital trainer kit 1
2. IC 7408 [AND] 1
3. IC 7432 [OR] 1
4. IC 7404 [NOT] 1
5. IC 7400 [NAND] 1
6. IC 7402 [ NOR] 1
7. IC 7486 [XOR 1
8. IC 74266[XNOR] 1
9. Connecting Wires 1
Theory:
Logic gates are the basic components in digital electronics. They are used to create
digital circuits and even complex integrated circuits. For example, complex integrated
circuits may bring already a complete circuit ready to be used – microprocessors and
microcontrollers are the best example – but inside them they were projected using several logic
gates.
A gate is a digital electronic circuit having only one output but one or more
inputs. The output or a signal will appear at the output of the gate only for certain input-signal
combinations.
There are many types of logic gates; such as AND, OR and NOT, which are usually called the
three basic gates. Other popular gates are the NAND and the NOR gates; which are simply
combinations of an AND or an OR gate with a NOT gate inserted just before the output signal. Other
gates include the XOR “Exclusive-OR” and the XNOR "Exclusive NOR" gates. All the logic gates
used in the exercises below are known as TTL (transistor-to-transistor) logic. These have the
convenient property that the output of any gate can be used directly as input to another gate. All
these TTL circuits are operated from a 5 V power supply, and the binary digits 0 and 1 are
represented by low and high voltages on the gate terminals.
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AND: The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A
dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e.
AB
OR: The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.
NOT: The NOT gate is an electronic circuit that produces an inverted version of the input at its output.
It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is
also shown as A', or A with a bar over the top, as shown at the outputs.
NAND: This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of
all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on
the output. The small circle represents inversion.
NOR: This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all
NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the
output. The small circle represents inversion.
XOR: The 'Exclusive-OR' or EOR or XOR gate is a circuit which will give a high output if either, but not
both, of its two inputs are high. An encircled plus sign ( ) is used to + show the EOR operation.
XNOR: The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if
either, but not both, of its two inputs are high. The symbol is an EXOR gate with a
small circle on the output. The small circle represents inversion.
IC Pin Diagram, Logic Diagram and Truth Table:
1. AND gate:
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2. OR gate:
3. NOT Gate:
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4. NAND gate:
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5. NOR gate:
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6. XOR gate:
7. XNOR gate:
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Procedure:
Implementing the Solution
1. Plug the chips you will be using into the breadboard. Point all the
chips in the same direction with pin 1 at the upper-left corner. (Pin 1
is often identified by a dot or a notch next to it on the chip package).
2. Connect +5V and GND pins of each chip to the power and ground
bus strips on the breadboard.
3. Make the connections as per the circuit diagram.
4. Switch on VCC and apply various combinations of input according
to truth table.
RESULT:
Thus, the logic gates are studied and its truth tables are verified.
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Ex. No. 5
Date:
Design of Half Adder and Full Adder Using Logic Gates
Aim: To implement half-adder and full adder circuits.
Apparatus Required:
IC 7486, IC 7432, IC 7408, IC 7400, Digital Trainer Kit, Connecting wires, etc.
Logic Circuit Diagram:
Theory:
HALF ADDER
A half adder has two inputs for the two bits to be added and two outputs one from
the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the X-OR Gate
the carry out from the AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 27
half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry
output will be taken from OR Gate.
PROCEDURE:
1. Plug the chips you will be using into the breadboard. Point all the chips in the same
direction with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch
next to it on the chip package).
2. Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.
3. Make the connections as per the circuit diagram.
4. Switch on VCC and apply various combinations of input according to truth table.
5. Note down the output readings for half/full adder and sum and the carry bit for different
combinations of inputs in following Tables where S & V indicating logic value of the
output. And fill your result in S (V) and C (V) in voltage. Where 5V indicating logic 1
and 0V indicating logic 0.
Truth Table:
Observation:
Result:
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Ex. No. 6
Date:
Study and Construction of Flip- Flops Using Logic Gates
Aim: To construct the various flipflops using logic gates.
Apparatus Required:
Digital Trainer Kit, IC 7400, IC 7410, IC 7404, Connecting Wires..
Theory:
RS and D Flip-Flop:-
–S Flip flop has two data inputs R & S.
application.
inadvertently.
lop a circuit that needs only a single data input.
- Flop using NOR Gate.
output Q is
in the truth table.
J-K Flip-flop:-
-Flop is the most versatile binary strange element.
-flop. The uncertainty in the
State of SR Flip- Flop when S = R = 1 can be eliminated by using JK Flip-Flop
T Flip –Flop:-
obtained by using NAND or NOR gates.
) and two outputs
Q and Q.
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stable state Q=1 which is referred to as the 1 state( or set state ) whereas in
the other stable state Q=0 which is referred to as the 0 state ( or reset state )
it is in 0 state, it continues to remain in this state.
bit of digital information.
as shown in fig.
table 1. If T=1 it acts as a toggle switch for every clock pulse the output
Q changes.
Procedure:-
1. Study the circuit diagram.
2. Connect the circuit as shown in fig i.e. JK Flip Flop by using connecting
wires.
3. Switch „ON‟ the power supply.
4. Apply proper I/P to J & K I/Ps of Flip-Flop from Logic I/P
5. Check the O/P on Logic O/P Section.
6. Change the I/P & Verify the Truth Table.
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Logic Diagram and Truth Table:
SR Flipflop:
D Flipflop:
JK Flipflop:
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T FlipFlop:
Result:
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CYCLE II
MICROPROCESSOR
EXPERIMENTS
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Ex No. 7(a)
Date: __/__/2012 8-bit Addition and Subtraction Using 8085 Microprocessor
AIM:
To perform the addition and subtraction of two 8-bit data (a) without
carry/borrow and (b) with carry/borrow using 8085 Microprocessor.
EQUIPMENTS REQUIRED:
8085 Microprocessor kit, keyboard (optional), power supply unit – 1 each.
ALGORITHM:
ADDITION OF TWO 8-BIT DATA WITHOUT CARRY:
Step 1: Start the program.
Step 2: Initialize the address of the memory register as a 16-bit data.
Step 3: Get the first data in the first location and the second data in the second
location.
Step 4: Move the first data to the accumulator.
Step 5: Go to the second location and add the second data with the first data.
Step 6: Move the result stored in the accumulator in the next memory location.
Step 7: Terminate the program.
ADDITION OF TWO 8-BIT DATA WITH CARRY:
Step 1: Start the program.
Step 2: Initialize the address of the memory register of HL register pair as a 16-
bit data.
Step 3: Get the first data in the first location and the second data in the second
location.
Step 4: Move the first data to the accumulator. Initialize any general purpose
register (say „C‟ register) to zero.
Step 5: Perform addition between the two 8-bit data.
Step 6: Store the result in any address location (say „4152H‟).
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Step 7: Check for the carry flag. If CY=1, then increment the data in the general
purpose register else keep the content as such.
Step 8: Store the data in the general purpose register to any memory location
(say „4153H‟).
Step 9: Stop the program.
SUBTRACTION OF TWO 8-BIT DATA WITHOUT BORROW:
Step 1: Start the program.
Step 2: Initialize the address of the memory.
Step 3: Get the first data in the first location and the second data in the second
location.
Step 4: Move the first data to the accumulator.
Step 5: Go to the second location and formulate the subtraction operation.
Step 6: Move the result stored in the accumulator in the next memory location.
Step 7: Terminate the program.
SUBTRACTION OF TWO 8-BIT DATA WITH BORROW:
Step 1: Start the program.
Step 2: Initialize the address of the memory register of HL register pair as a 16-
bit data.
Step 3: Get the first data in the first location and the second data in the second
location.
Step 4: Move the first data to the accumulator. Initialize any general purpose
register (say „C‟ register) to zero.
Step 5: Perform subtraction between the two 8-bit data, move the difference in
the Accumulator.
Step 6: Store the result in any address location (say „4152H‟).
Step 7: Check for the carry flag. If CY=0, then keep the content as such.
Step 8: If CY=1, then increment the data in the general purpose register, take
1‟s Complement to the data in the accumulator and add 01 to it.
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Step 9: Store the data in the general purpose register to any memory location
(say „4153H‟).
Step 10: Stop the program.
PROGRAM:
ADDITION OF TWO 8-BIT DATA WITHOUT CARRY:
Memory
Address
Label Mnemonics Opcode Comments
4100 LXI H, 4150 Load the HL register pair of the
contents of the address 4150H
4101
4102
4103 MOV A, M Move the first data to
Accumulator
4104 INX H HL register points to 4151H
4105 MOV B, M Move the second data to B
register
4106 ADD B Perform Addition between A &
B [A+B A] and store the sum
in Accumulator.
4107 STA 4152 Store the results in the address
4152H from the accumulator.
4108
4109
410A HLT Stop the Program
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 36
OBSERVATION:
INPUT ADDRESS INPUT DATA OUTPUT ADDRESS OUTPUT DATA
4150 03
4152
4151 06
ADDITION OF TWO 8-BIT DATA WITH CARRY:
Memory
Address
Label Mnemonics Opcode Comments
4100 LXI H,4150 Load the HL register pair of
the content to the address
4150H.
4103 MOV A, M Move the first data to
Accumulator.
4104 INX H HL register points to 4151H
4105 MOV B, M Move the second data to B
register
4106 MVI C, 00 Initialize C register to zero
4107 ADD B Perform addition between
A & B register [A+B A]
4108 JNC 410C Loop Check for carry flag, if
CY=0, go to 410C else go to
410B
410B INR C Increment C register
410C Loop STA 4152 Store the result in 4152H
410F MOV A, C Move the content of C to
Accumulator
4110 STA 4153 Stores the data in A at
4153H
4113 HLT Stop the Program
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 37
OBSERVATION:
INPUT ADDRESS INPUT DATA OUTPUT ADDRESS OUTPUT DATA
4150 FF 4152
4151 06 4153
SUBTRACTION OF TWO 8-BIT DATA WITHOUT BORROW:
Memory
Address
Label Mnemonics Opcode Comments
4100 LXI H,4150 Load the HL register pair of
the contents to the address
4150H.
4103 MOV A, M Move the first data to
Accumulator.
4104 INX H HL register pair points to
4151
4105 MOV B, M Move Second data to B
register.
4106 SUB B Perform Subtraction
between A and B [A-B A]
and store the difference in
Accumulator.
4107 STA 4152 Store the results in the
address 4152H.
410A HLT Stop the Program.
OBSERVATION:
INPUT ADDRESS INPUT DATA OUTPUT ADDRESS OUTPUT DATA
4150 FF 4152
4151 06
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 38
SUBTRACTION OF TWO 8-BIT DATA WITH BORROW:
Memory
Address
Label Mnemonics Operand Opcode Comments
4100 MVI C, 00 Clear C reg.
4102 LXI H, 4500 Initialize HL reg. to 4500
4105
MOV
A, M
Transfer first data to
accumulator 4106
INX
H
Increment HL reg. to point
next memory location. 4107
SUB
M
Subtract first number from
acc. Content.
4108 JNC L1 Jump to location if result
does not yield borrow.
410B INR C Increment C reg.
410C
CMA
Complement the Acc.
content
410D ADI 01H Add 01H to content of acc.
410F
INX
H
Increment HL reg. to point
next memory location. 4110
MOV
M, A
Transfer the result from acc.
to memory. 4111
INX
H
Increment HL reg. To point
next memory location. 4112
MOV
M, C
Move carry to memory.
4113 HLT Stop the program
OBSERVATION:
INPUT ADDRESS INPUT DATA OUTPUT ADDRESS OUTPUT DATA
4150 06 4152
4151 FF 4153
Result:
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 39
Ex No. 7(b)
Date: __/__/2012 8-bit Multiplication and Division Using 8085 Microprocessor
AIM:
1. To multiply two 8 bit numbers stored at consecutive memory locations and store the
result in memory.
2. To divide two 8-bit numbers and store the result in memory.
ALGORITHM:
1. Multiplication:
LOGIC: Multiplication can be done by repeated addition.
1. Initialize memory pointer to data location.
2. Move multiplicand to a register.
3. Move the multiplier to another register.
4. Clear the accumulator.
5. Add multiplicand to accumulator
6. Decrement multiplier
7. Repeat step 5 till multiplier comes to zero.
8. The result, which is in the accumulator, is stored in a memory location.
2.Division:
LOGIC: Division is done using the method Repeated subtraction.
1. Load Divisor and Dividend
2. Subtract divisor from dividend
3. Count the number of times of subtraction which equals the quotient
4. Stop subtraction when the dividend is less than the divisor
.The dividend now becomes the remainder. Otherwise go to step 2.
5. Stop the program execution.
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 40
Program:
1. Multiplication:
Memory
Address
Label Mnemonics Operand Opcode Comments
4100 LXI H, 4500 Load HL register with
data in memory
location 4500
4101
4102
Transfer first data to
register B.
4103
MOV
B, M
4104
INX
H
Increment HL reg. to
point next
memory location.
4105 MVI A, 00H Clear the accumulator.
4106
4107 MVI C, 00H Clear C register for
carry.
4108
4109
L1
ADD
M
Add data in memory
location
with
accumulator.
410A JNC NEXT
Jump to NEXT if there
is no carry.
410B
410C
410D INR C Increment C register.
410E NEXT DCR B Decrement B register.
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 41
410F JNZ L1
Jump to L1 if B is not
zero.
4110
4111
4112
INX
H
Increment HL register to
point next
memory location.
4113
MOV
M, A Transfer the result from
acc. to memory.
4114 INX H Increment HL register.
4115
MOV
M, C Transfer the result from
C reg. to memory.
4116 HLT Stop the program
2. Division:
ADDRES S OPCOD E
LABEL MNEMONIC S OPERAN D
COMMENTS
4100 MVI B,00 Clear B register for
quotient 4101
4102 LXI H,4500
Initialize HL register
to 4500H 4103
4104
4105
MOV
A,M Transfer dividend to
accumulator.
4106
INX
H
Increment HL register
to point next memory
location.
4107
LOOP
SUB
M Subtract divisor from
dividend
4108 INR B Increment B register.
4109 JNC LOOP Jump to LOOP if
result does not yield
borrow
410A
410B
410C ADD M Add divisor to acc.
410D DCR B Decrement B reg.
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 42
410E
INX
H
Increment HL reg to
point next memory
location.
410F
MOV
M,A Transfer the remainder
from acc. to memory.
4110
INX
H
Increment HL reg to
point next memory
location.
4111
MOV
M,B Transfer the quotient
from B reg to memory.
4112 HLT Stop the program
OBSERVATION:
INPUT OUTPUT
4500 4502
4501 4503
RESULT:
Thus the 8-bit multiplication and 8-bit division was done in 8085p.
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 43
Ex No. 8
Date: __/__/2012
Finding Smallest Number and largest Number from the Array of
Numbers Using 8085 Microprocessor AIM:
i) To find the largest element in an array.
ii) To find the smallest element in an array.
Using 8085 Microprocessor
ALGORITHM: a) the largest element in an array
1. Place all the elements of an array in the consecutive memory locations.
2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of
elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content
(next element).
7. If the accumulator content is smaller, then move the memory content (largest
element) to the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero.
10. Store the result (accumulator content) in the specified memory location.
b) To find the smallest element in an array.
1. Place all the elements of an array in the consecutive memory locations.
2. Fetch the first element from the memory location and load it
in the accumulator.
3. Initialize a counter (register) with the total number of
elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content
(next element).
7. If the accumulator content is smaller, then move the memory content (largest
element) to the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 44
Program:
1. Largest Number:
ADDRESS OPCODE LABEL MNEMONICS OPERAN D
COMMENTS
8001 LXI H,8100
Initialize HL reg to
8100H 8002
8003
8004 MVI B,04 Initialize B reg with
no. of comparisons(n-
1)
8005
8006
MOV
A,M Transfer first data to
acc.
8007
LOOP1
INX
H
Increment HL reg. to
point next
memory location
8008 CMP M Compare M & A
8009 JNC LOOP
If A is greater than M
then go to loop 800A
800B
800C
MOV
A,M Transfer data from M
to A reg
800D LOOP DCR B Decrement B reg
800E JNZ LOOP1
If B is not Zero go to
loop1 800F
8010
8011 STA 8105
Store the result in
a memory location. 8012
8013
8014 HLT Stop the program
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 45
2) Smallest Number:
ADDRESS OPCODE LABEL
MNEMONICS OPERAND
COMMENTS
8001 LXI H,8100 Initialize HL reg to
8100H 8002
8003
8004 MVI B,04 Initialize B reg with no. of
comparisons(n-1) 8005
8006 MOV A,M Transfer first data to acc. 8007
LOOP1
INX
H
Increment HL reg. to
point next memory
location
8008 CMP M Compare M & A
8009 JC LOOP
If A is lesser than M then go
to loop 800A
800B 800C
MOV
A,M
Transfer data from M to
A reg
800D LOOP DCR B Decrement B reg
800E JNZ LOOP1
If B is not Zero go to
loop1 800F
8010
8011 STA 8105
Store the result in a
memory location. 8012
8013
8014 HLT Stop the program
OBSERVATION:
INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8100 8105
8101
8102
8103
8104 RESULT:
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 46
Ex No. 9
Date: __/__/2012
Sorting an Array of Numbers in Ascending and Descending Order Using 8085
Microprocessor
Aim: To sort the given number in the ascending and descending order using 8085
microprocessor.
Algorithm:
1. Ascending Order:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is larger than second
then interchange the number.
3. If the first number is smaller, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
2. Descending Order:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is smaller than second
then interchange the number.
3. If the first number is larger, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
Program:
1. Ascending Order:
ADDRESS OPCODE LABEL MNEMONICS OPERAND
COMMENTS
8000 MVI B,04 Initialize B reg with
number of comparisons
(n-1)
8001
8002 LOOP
3
LXI
H,8100
Initialize HL reg to
8100H 8003
8004
8005 MVI C,04 Initialize C reg with no. of
comparisons(n-1) 8006
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 47
8007
LOOP2
MOV
A,M Transfer first data to
acc.
8008
INX
H
Increment HL reg. to
point next memory
location
8009 CMP M Compare M & A
800A JC LOOP1
If A is less than M then go
to loop1 800B
800C
800D
MOV
D,M Transfer data from M to
D reg
800E
MOV
M,A Transfer data from acc
to M
800F DCX H Decrement HL pair
8010
MOV
M,D Transfer data from D to
M
8011 INX H Increment HL pair
8012 LOOP1 DCR C Decrement C reg
8013 JNZ LOOP2
If C is not zero go to
loop2 8014
8015
8016 DCR B Decrement B reg
8017 JNZ LOOP3
If B is not Zero go to
loop3 8018
8019
801A HLT Stop the program
2. Descending Order:
ADDRESS OPCODE LABEL MNEMONICS OPERAND
COMMENTS
8000 MVI B,04 Initialize B reg with
number of comparisons
(n-1)
8001
8002
LOOP
3
LXI
H,8100
Initialize HL reg.
to8100H 8003
8004
8005 MVI C,04 Initialize C reg with no.
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 48
8006 of comparisons(n-1)
8007 LOOP2 MOV A,M Transfer first data to acc. 8008
INX
H
Increment HL reg. to
point next memory
location
8009 CMP M Compare M & A
800A JNC LOOP1 If A is greater than M
then go to loop1 800B
800C 800D
MOV
D,M
Transfer data from M to
D reg 800E
MOV
M,A
Transfer data from acc to
M
800F DCX H Decrement HL pair 8010
MOV
M,D
Transfer data from D to
M
8011 INX H Increment HL pair
8012 LOOP1 DCR C Decrement C reg
8013 JNZ LOOP2
If C is not zero go to
loop2 8014
8015
8016 DCR B Decrement B reg
8017 JNZ LOOP3
If B is not Zero go to
loop3 8018
8019
801A HLT Stop the program
OBSERVATION: Ascending:
INPUT OUTPUT
MEMORY
LOCATION
DATA MEMORY
LOCATION
DATA
8100 8100
8101 8101
8102 8102
8103 8103
8104 8104
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 49
Descending:
INPUT OUTPUT
MEMORY
LOCATION
DATA MEMORY
LOCATION
DATA
8100 8100
8101 8101
8102 8102
8103 8103
8104 8104
Result:
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 50
Ex No. 10
Date: __/__/2012
Transferring Block of Data Using 8085 Microprocessor
AIM:
To transfer a block of data from one block to another block
using 8085 microprocessor. ALGORITHM:
1. Get the numbers to be transferred from the memorylocations.
2. Initialize the counter value.
3. Initialize the D register with the destination address
4. Increment the H and D register and Decrement the counter.
5. If counter value is not zero then move to loop 1, until counter becomes
zero.
6. Store the result in the specified memory location.
PROGRAM:
ADDRESS OPCODE LABEL MNEMONICS OPERAND
COMMENTS
8100 LXI H,8200 Initialize H reg with
number of comparisons
(n-1)
8101
8102
Initialize C reg with no. of
comparisons(n-1) 8103 MVI C,05
8104
8105 LXI D,8300 Initialize D reg with no. of
comparisons(n-1) 8106
8107
8108 LOOP1 MOV D,M
8109 INX H
810A INX D If A is less than M then go
to loop1 810B DCR C
810C JNZ LOOP1 800D
Transfer data from M to
D reg 800E
Transfer data from acc
to M
800F HLT Stop the program
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 51
OBSERVATION:
INPUT OUTPUT
MEMORY
LOCATION
DATA MEMORY
LOCATION
DATA
8100 8100
8101 8101
8102 8102
8103 8103
8104 8104
RESULT:
Thus the transferring a block of data from one block to another block program is
executed and thus the data’s are transferred from one block to another block.
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 52
Ex No. 11
Date: __/__/2012
STEPPER MOTOR INTERFACING WITH 8085
Aim:
The aim of the experiment is to demonstrate the forward/reverse stepped motions of a
stepper motor, using 8085 microprocessor.
Apparatus Required:
8085 Microprocessor kit, Interfacing card, Stepper Motor, Power supply unit
Algorithm:
1. Enter the program starting from the location 8100.
2. Execute the same.
3. The stepper motor rotates.
4. Speed can be varied by varying the count at DE pair.
5. Direction can be varied by entering the data in the look –up table in the reverse order.
DESCRIPTION:
The stepper motors have immense applications in printing, Industrial Robotics, Precision
tool motions in drilling, cutting and shaping machines, lathe etc.
This project is proposed to demonstrate interfacing of stepper motor to 8085
microprocessor and to run it in continuous or stepped motion in forward or reverse direction
under program control, using 8085 microprocessor.
HARDWARE DESCRIPTION:
The hardware setup consists of a microprocessor motherboard and stepper motor
interface board. The motherboard consists of 8085 MPU, 8KB EPROM, 8KB RAM, Keyboard
and display controller 8279, 21-key Hex-keypad and six numbers of seven segment LEDs and
Bus Expansion connector. The stepper motor interface consists of driver transistors for stepper
motor windings and address decoding circuit. The microprocessor output the binary sequence
through data bus, which are converted to current pulses by the driver transistors and used to drive
stepper motor. The software for the system is developed in 8085 assembly language.
Prepared by J.Cyril Robinson Azariah & C.Moorthy Page 53