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CHAPTER 14 CMOS DIGITAL LOGIC CIRCUITS
Chapter Outline14.1 Digital Logic Inverters14.2 The CMOS
Inverter14.3 Dynamic Operation of the CMOS Inverter14.4 CMOS
Logic-Gate Circuits14.5 Implications of Technology Scaling: Issues
in Deep-Submicron Design
NTUEE Electronics III 14-1
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14.1 DIGITAL LOGIC INVERTERS
The Voltage-Transfer Characteristic (VTC) The function of the
inverter is to invert the logic value of its input signal The
voltage-transfer characteristic is used to evaluate the quality of
inverter operation
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VTC parameters VOH: output high level VOL: output low level VIH:
the minimum value of input interpreted by the inverter as a logic 1
VIL: the maximum value of input interpreted by the inverter as a
logic 0 Transition region: input level between VIL and VIH
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Noise Margins The VTC is generally non-linear VIH and VIL are
defined as the points at which the slope of the VTC is 1 Robustness
(noise margin at a high level): NMH = VOH VIH Robustness (noise
margin at a low level): NML = VIL VOL Static inverter
characteristics for ideal VTC:
VOH = VDD VOL = 0 VIH = VIL = VDD/2 NMH = NML = VDD/2
NTUEE Electronics III 14-3
NMH NML VDD/2
Ideal VTC
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Power Dissipation Static power dissipation: power dissipated
when the inverter stays in logic 0 or logic 1 Dynamic power
dissipation: power dissipated as the output is switching
Propagation Delay tPHL : high-to-low propagation delay tPLH :
low-to-high propagation delay tP (propagation delay) = ( tPLH +
tPHL )/2 Maximum switching frequency fmax = 1/2tP The output
transient of the inverter can be characterized by a RC
charge/discharge model
2 DDD CVfP
NTUEE Electronics III 14-4
The output transient of the inverter can be characterized by a
RC charge/discharge modelRCt
O eVVVtv/
0 )()(
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Power-Delay Product and Energy-Delay Product Power and delay are
often in conflict for inverter operation Power-delay product is a
figure-of-merit for comparing logic-circuit technologies or
families Power-delay product is defined as Energy-delay product is
defined as
Silicon Area Area reduction through advances in processing
technology Area reduction through advances in circuit design
techniques Area reduction through careful chip layout
2/ 2DDPD CVtPPDP 2/ 2 PDDtCVEDP
NTUEE Electronics III 14-5
Fan-In and Fan-Out Fan-in of a gate is the number of its inputs
Fan-out is the maximum number of similar gates that a gate can
drive
Logic-Circuit Families
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Inverter Implementation Simplest implementation of the inverter
with a MOSFET and a load
Inverter implementation with complementary switches
NTUEE Electronics III 14-6
Inverter implementation with a double-throw switch
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14.2 THE CMOS INVERTER
Circuit Operation A CMOS inverter consists of an n-channel and a
p-channel MOSFET The n-channel device turns on and the p-channel
device turns off as the input level goes high The p-channel device
turns on and the n-channel device turns off as the input level goes
low The turn-on device is modeled by a resistance: VOH = VDD and
VOL = 0 for any CMOS inverter
1' )(/ tnDDnnDSN VVLWkr 1' |)|(/ tpDDppDSP VVLWkrand
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The Voltage-Transfer Characteristic The transistors go through
five different operation regions as the input goes from 0 to VDD
The operating point is obtained by making iDN = iDP
Region I: (QN off; QP tri.) Region II: (QN sat.; QP tri.) Region
III: (QN sat; QP sat) Region IV: (QN tri.; QP sat.) Region V: (Q
tri ; Q off)
DPDN ii )0(
22 )(21)|)(|()(
21
ODDODDtpIDDpDPtnInDN vVvVVvVkiVvki
22 |)|(21)(
21
tpIDDpDPtnInDN VvVkiVvki 22 |)|(
21
21)( tpIDDpDPOOtnInDN VvVkivvVvki
)0( ii
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Region V: (QN tri.; QP off) )0( DPDN ii
vO
iD
vO
iD
vO
iD
vO
iD
vO
iD
Region I Region II
Region III Region IV Region V
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Static Characteristics of the CMOS Inverter Ratioless logic: VOH
and VOL are independent of ratio of the transistors
VOH = VDD VOL = 0
Static power dissipation is zero for both states Noise margins
can be determined by the VTC The switching voltage (when vI = vO)
is defined by
where
VM increases (VTC shifts) with r1
)|(
r
VVVrV tntpDDM
nn
pp
n
p
LWLW
kk
r)/()/(
NTUEE Electronics III 14-9
VM increases (VTC shifts) with r NML increases and NMH decreases
as r increases NML decreases and NMH increases as r decreases
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The Matched Inverter A matched inverter has equivalent pull-up
and pull-down device with kn = kp and Vtn = |Vtp| = Vt The VTC is
symmetric Determine VIL from the VTC in Region II:
Determine VIH from the VTC in Region IV:
22 )(21))(()(
21
ODDODDtIDDtI vVvVVvVVv
I
OODD
I
OtIDDODDtI dv
dvvVdvdvVvVvVVv )()()(
)23(81
tDDIL VVV
NTUEE Electronics III 14-10
Determine VIH from the VTC in Region IV:
Noise margins: NMH = NML = (3VDD + 2Vt)/8 Switching voltage: VM
= VDD/2
22 )(21
21)( tIDDOotI VvVvvVv
)()( tIDDI
OO
I
OtIO VvVdv
dvvdvdvVvv
)25(81
tDDIH VVV
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14.3 DYNAMIC OPERATION OF THE CMOS INVERTER
Determining the Propagation Delay Evaluated by
charging/discharge the output capacitor C through QP and QN Average
current method:
tPHL:
)()(21 MiEiI DNDNav
2)(21)( tnDDnDN VVkEi
2
221
2)()( DDDDtnDDnDN
VVVVkMi
CCV
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tPLH:
Propagation delay: tP = (tPHL+tPLH)/2
DDn
n
av
DDPHL Vk
CI
CVt 2
where
223
47/2
DD
tn
DD
tnn V
VVV
DDp
p
av
DDPLH Vk
CI
CVt
2
where
2
2||347/2
DD
tp
DD
tpn V
VVV
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An alternative approach: Modeling the turn-on device as a
resistance Use RC charge/discharge behavior to evaluate the
propagation delay The empirical values of the resistors are given
by
tPHL= 0.69RNC tPLH= 0.69RPC
)()/(
5.12 kLW
Rn
N )()/(30 kLW
Rp
Pand
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Determining the Equivalent Load Capacitance Components
accountable for the equivalent load capacitance
Transistor parasitic capacitances Wiring capacitance or
interconnect capacitance Input capacitance of the following
stages
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wggdbdbgdgd CCCCCCCC 432121 22
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Inverter Sizing Minimum length permitted by the technology is
usually used as the length for all channels Device aspect ratio
(W/L)n is usually selected in the range 1 to 1.5 The selection of
(W/L)n is relative to (W/L)n
Matched inverter by (W/L)p : (W/L)n = n: p (W/L)p = (W/L)n:
minimum area, small propagation delay (W/L)p = 2(W/L)n: a
frequently used compromise
Transistor sizing (aspect ratios are increased by a factor of S)
versus propagation delay Load capacitance:
extext CSCCCC 0intint
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Equivalent resistance:
Propagation delay:Dynamic Power Dissipation Dynamic power
dissipation:
Peak current:
SR
SR
SRR eqPNeq
0)(21
exteqeqexteqP CRSCRCSCSR
t 00int00int0 169.0)(69.0
2DDD fCVP
2
221
tnDDnpeak VVkI
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14.4 CMOS LOGIC-GATE CIRCUITS
CMOS Logic-Gate Structure
Implementation of PDN
Implementation of PUN
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The PDN can be most directly synthesized by expressing . The PUN
can be most directly synthesized by expressing . The PDN can be
obtained from the PUN (and vice versa) using duality property.
However, duality of the PDN and PUN is not a necessary
condition.
YY
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Transistor Sizing The (W/L) ratios are chosen for a worst-case
gate delay equal to
that of the basic inverter The derivation of equivalent (W/L)
ratio is based on the equivalent
resistance of the transistors
1
21
...)/(
1)/(
1)/(Connection Series
LWLW
LW eq1)/( LWrDS
...)/()/()/(Connection Parallel 21 LWLWLW eq
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Effects of Fan-In and Fan-Out Each additional input to a CMOS
gate requires two additional transistors Increases the chip area
and the propagation delay due to excess capacitive loading The
number of NAND gate is typically limited to 4 Redesign the logic
design may be required for a higher number of inputs Advantages of
using CMOS logic: static power dissipation, ratioless design, noise
margin Disadvantage of using CMOS logic: area, complexity,
capacitive loading, propagation delay
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Examples for CMOS Logic Gates
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14.5 IMPLICATIONS OF TECHNOLOGY SCALING
Moores Law A new technology is developed for every 2~3 years due
to cost and speed requirement The trend was predicted more than 40
years ago by Gordon Moore For every new technology generation:
The minimum length is reduced by a factor of 1.414 and the area
is reduced by a factor of 2 The cost is reduced by half or the
circuit complexity is doubled Device scaling generally decreases
the parasitics and enhances the operating speed The operating power
is reduced
The current technology node advances into deep-submicron Issues
in deep-submicron technologies have to be taken into account for
circuit designs
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Issues in deep submicron technologies have to be taken into
account for circuit designs
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Scaling Implications
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Velocity Saturation Long-channel devices:
Drift velocity: vn = nE Electric field in the channel: E =
vDS/L
Short-channel devices: Velocity saturates at a critical field
Ecr with vsat 107 cm/s The vDS at which velocity saturates is
denoted by VDSsat VDSsat = EcrL = vsatL/n VDSsat is a device
parameter
The I V Characteristics
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The I-V Characteristics Long-channel devices
Saturation current: Short-channel devices
For VGS-Vt < VDSsat: same as long-channel devices For VGS-Vt
> VDSsat:
2)(21
tGSoxnD VVLWCi
221)( DSsatDSsattGSoxnDsat VVVVL
WCI
DSsattGSsatox VVVvWC 21
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Current Equation for Velocity Saturation For vGS-Vt VDSsat and
vDS VDSsat, the drain current is given by
The current is reduced from the predication of a long-channel
device The dependence on vGS is more linear rather than
quadratic
Four regions of operation: cutoff, triode, saturation and
velocity saturation Short-channel PMOS transistors undergo velocity
saturation at the same value of vsat The effects on PMOS are less
pronounced due to lower mobility and higher VDSsat
)1(21
DSDSsattGSDSsatoxnD VVVvVLWCi
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Subthreshold Conduction The device is not complete off in
deep-submicron devices as vGS < Vt The subthreshold current is
exponentially proportional to vGS: iD = Isexp(vGS/nVT) It is a
problem in digital IC design for two reasons:
Such current leads to nonzero static power dissipation for CMOS
logics May cause undesirable discharge of capacitors in dynamic
CMOS logics
The Interconnect The width of the interconnect scales down with
the CMOS technology The metal wire is no longer an ideal short
Series parasitic resistance may cause undesirable voltage drop
and excess delay
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Series parasitic resistance may cause undesirable voltage drop
and excess delay Parasitic capacitance to ground may lead to speed
degradation and additional dynamic power