Electronic Pack….. Chapter 6: Printed Circuit Board Design Slide 1 Chapter 6: Printed Circuit Board Design Example of a Printed Circuit Board – front and back side The course material was developed in INSIGTH II, a project sponsored by the Leonardo da Vinci program of the European Union
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Electronic Pack….. Chapter 6: Printed Circuit Board Design Slide 1 Chapter 6: Printed Circuit Board Design Example of a Printed Circuit Board – front and.
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• Output:–Final Schematics–Assembly Drawings–Documentation for PWB Manufacturer (”Gerber” file giving input for making PWB Manucturing Data (See Chapter 5):
• Data for Photo- or Laser Plotter for Making Photographic Films and Printing Masks
• Data for Numeric Drilling and Milling Machines• Data for Placement Machines• Data for Test Fixtures and Testing Machines
Class 0 1 2 3 5 *) 7 *)Conductor width, b 0.4 0.3 0.22 0.15 0.13 0.10Conductor separation, I 0.5 0.3 0.2 0.17 0.12 0.10Hole diameter, d 0.9 0.8/0.5 0.8/0.5 0.8/0.3 0.8/0.2 0.8/0.1Hole pad diameter,D 1.8 1.5 1.3/1.0 1.3/.65 0.6 0) 0.4 0)
Table 6.1: Examples of minimum dimension and PCB classes. The class indicates how many conductors can pass between the solder pads of a DIP package (no. of channels), and typical corresponding minimum dimensions in mm. When two figures are given for hole diameters, they are for component- and via holes respectively.
Fig. 6.4: a): Parameters in layout dimensions used in Table 6.1. b): Minimum dimensions for solder mask for surface mount PWBs. Left: Dimensions for screen printed solder mask, with one common opening for all solder lands of an IC package. Right: Photoprocessible solder mask with a "pocket" for each terminal, permitting conductors between the solder lands.
Fig. 6.8: Solder lands for SMD components should be separated from heavy copper areas by narrow constrictions. Conductors should preferably leave the solder lands of one component symmetrically.
Fig. 6.18: a): Correct position of test point, separated from solder land. b): Test points on solder lands are not recommended. c): Testing on components or component leads should be avoided.
• DL (ppm) = 1 - Y(1-T) x 106 • DL = defect level• Y = yield • T = fault coverage (One cannot test all failure modes)
• Test Methods– Functional test (Test the PCB in the system – PCB OK or not)– In-circuit test (Test at local test points – finds the exact fault)– Scan path (For logic circuits – digital output versus input)– Boundary scan (Scan path with separate test pins)– Built-in self test (Add test circuitry on the PCB)
Fig. 6.20: Mechanical strain is caused by difference in coefficient of thermal expansion (TCE), and changes in temperature. The magnitude of the corresponding stress depends on dimensions, temperature difference/change, and the elastic moduli of the materials.
Thermal DesignFig. 6.21: a): Heat flow from hole mounted and surface mounted components on a PCB. b): Relative amount of heat removed by conduction, convection and radiation, from DIP hole mounted components and SMD LLCC components - typical values.
Fig. 6.24: Cross section and thicknesses for a practical PWB with two Cu/Invar/Cu cores. The thicknesses were designed to get an over-all TCE of 7.5 [ppm/°C • m] The achieved value was measured to be 9.3 [ppm/°C • m] Calculated effective thermal conductivity in the x - y directions was 21 [W/ °C • m]
Fig. 6.29: "Microbellows cooling": A jet of water or other cooling liquid impinges on the backside of the chip. The bellow structure is necessary to accommodate thermal expansion
Fig. 6.30: Cooling by forcing liquid through microscopic, etched channels in the semiconductor chip [6.32]. The channels are approximately 400 µm deep and 100 µm wide.
Fig. 6.32: Distributed parameters in a model of a loss free transmission line. C and L are capacitance and inductance per m length.
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Lossy transmission line
• Resistive power loss• R’: the resistance along the line (per meter)• L’: the inductance along the line (per meter)• G’: the conductance shunting the line (per meter)• C’: the capacitance shunting the line (per meter)• Series components are the sum of both signal and ground.
High Frequency Design, cont• Characteristic Impedance
–V = Zo·I
• Zo characteristic impedance :
– Zo = ((R + jL)/(G + jC))1/2
– = angular frequency– R = resistance per unit length– L = inductance per unit length– C = capacitance per unit length– G = loss conductance per unit length
• In loss free medium:– Zo = (L/C)
• Reflection coefficient:– R = (Z1 - Z2)/(Z1 + Z2)
• Z1 and Z2 : characteristic impedances of media 1 and 2
CjG
LjRZ
0
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Propagation speed, v
• Dependent on electrical properties• Derived from the material properties of the
medium (Maxwell equations) –Homogenous lossless transmission line in a
uniform dielectric medium
r =1 for all non-magnetic materials is magnetic permeability
From one end of the line to the other (loss less line)
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Reflections
Fig. 6.34:Distorted signal as a function of time when the transmitter has 78 ohms impedance the same as the characteristic impedance and the receiver has different impedances as indicated. If the receiver also has 78 ohms impedance the signal at the receiver is a time delayed replica of the transmitted signal.
If RL=Z0, transmission line behave as it was infinitely long, hence no reflection
0
0
ZR
ZRR
L
L
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Termination of line reflections• Terminate by:
– Characteristic line impedance
– A 50% mismatch is acceptable
• However termination gives:– Higher power dissipation
– Which needs a higher driver capability
– Different techniques for adjust termination to the driver capability, next slide…
It should be noted that if a reflection does occur, and propagates back to the driver (source), it can reflect again off the source. The driver has an output impedance. If that output impedance is exactly equal to Zo, then there will be no further reflection from the source. But if the output impedance of the driver is different than Zo, an additional reflection will occur. The magnitude of that reflection is again determined by a reflection coefficient.
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Termination possibilities
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Reflections from other discontinuities
• In a typical PCB the characteristic impedance of the x and y wiring planes are not identical. (anisotrop media)
• Connection via forms a small inductive and capacitive discontinuity
• Other:– Connectors
– Corners and turns of the copper line• Do not use 90° turns
– Pins of IC packages
– Capacitors and terminating resistors
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Obtaining a controlled impedance
Fig. 6.35: Geometries for obtaining a controlled characteristic impedance.
See pages 6.38 and 6.39 for equations and examples
High Frequency Design, continuedFig. 6.36: Expressions for characteristic impedance, Zo,
signal propagation speed, TPD,
capacitance per unit length, Co,
and crosstalk, XTalk, in different
geometries: a) coaxial, b) microstrip c) stripline. The expression for coaxial geometry is exact, the others are approximate and valid only in certain parameter ranges.
Fig. 6.37: Dependence of the characteristic impedance on geometric dimensions, for: a) Striplineb) Microstrip. w is the signal conductor width, S is the distance between ground planes for stripline, and H the distance between signal conductor and ground plane for microstrip (please refer to Figure 6.35). Curves are shown for different signal conductor thicknesses, t.
a
b
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Cross talk
• Cross talk is the capacitive and inductive coupling of signals from one signal line to another
• Increases with board density and performance (frequency and current drive)– Distance to ground (power) plane– Smaller conductor spacing– Dielectric constant– Larger currents– Rise and fall times– Current drive
• Near End Crosstalk or reverse crosstalk If we measure the crosstalk in the sample line at the same end of the cable we inserted the signal, it is called near end or reverse/backward crosstalk.
• Far End Crosstalk or forward crosstalk If we measure the crosstalk in the sample line at the opposite end of the cable that we inserted the signal, it is called far end or forward crosstalk
Fig. 6.38: Cross talk: A signal from A to C is transmitted to the B - D line and gives noise in B (backward or near end cross talk) and in D (forward or far end cross talk).
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Cross talk
Cross talk: A signal from A to B is transmitted to the C - D line and gives noise in C (reverse or near end cross talk) and in D (forward or far end cross talk).
Fig. 6.39: Backward cross talk as a function of conductor separation in stripline geometry in different dielectrics. The effect increases with increasing r and
decreases with increasing conductor separation.
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Minimize cross-talk• Use maximum allowable spacing between signal lines• Use low dielectrics materials• Minimize spacing between signal and ground lines /
plane• Isolate clocks and critical signals form other lines with
larger line spacing or isolate with ground lines– Use twisted pair for sensitive signals (clock, reset, set, clear)
– When using ribbon cable make every other line a ground line (e.g. U-ATA (UDMA hard disk cable)
• Terminate signals lines into characteristic impedance, use low impedance drivers
– s = (ro f )1/2 / (w Zo) for skin depth s = ( / f r o)1/2 << t
– d = [o1/2 f tan ]/ c
• R = ohmic resistance per unit length
• = electrical DC resistivity in the conductor
• t = conductor thickness
• tan = dielectric loss tangent
• w =conductor width
• f = frequency and = r o = magnetic permeability
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Skin depth• With an alternating current, however, there is a delay in the magnetic field's response to the
change in current and the 'old' magnetic field tends to push the current towards the outside of the conductor. As the frequency increases, so does the effect until at very high frequencies the entire current flows in a very narrow skin on the conductor--hence the name.
• Skin depth is due to the circulating eddy currents (arising from a changing H field) cancelling the current flow in the center of a conductor and reinforcing it in the skin.
Fig. 6.41: Conductor- and dielectric losses as functions of frequency for multilayer thin film modules.
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Same simulation as in Figure 1's better eye, run once with a typical FR-4 dielectric (loss tangent = 0.02; yellow eye diagram) and once with a low-loss dielectric (loss tangent = 0.004; purple). The low-loss material makes a substantial improvement to the eye opening, but would result in a much costlier PCB.
Figure 1, run once with a 4-mil-wide trace (red eye diagram) and once with 8-mil (yellow). The wider trace has less skin-effect loss, and therefore better signal quality as indicated by the more-open eye.
Eye opening: Space between 1 and 0: See: http://bwrc.eecs.berkeley.edu/classes/icdesign/ee290c_s11/lectures/Lecture02_Link_Over_Environ_6up.pdf
• Wirebonds, package pins and PCB routing acts as inductances at high frequency
• Induced voltage/noise bounce: VL=L(dI/dt)
• Good practice:– Lower rise times– Lower output drive– Use ground and power plane– Use bypass capacitors for power– Minimize power/ground tracks (use
plane)– Use vias wisely (vias acts as a
inductance)
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Power distribution
• Simultaneous switching gives large current spikes
• High capacitance Keeps stable voltage levels
• Low inductance makes L dI/dt switching noise low
• Power distribution is also modelled as transmission lines
• Reduced supply voltage reduced signal to noise
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Practical • Use ground - power planes
– Reference planes for signal lines
– Better dynamic power distribution
• Time of flight– High packaging density
• Cross talk– Large separation between signal lines
• Want a high impedance from the driver circuit point of view: I= U/Z
• However: High impedance <=> Low packaging density
• Manufacturing tolerances
• Line width, homogeneity
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EMC - Electromagnetic compliance
• International rules for:–Radiation of electromagnetic energy–Functionality of device in an electromagnetic field
(environment)
• Noise interference with other equipment
• Immunity against external radiation
• Design with respect to EMC/EMI from the start
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EMC - Design of circuit
• Wires and current loops acts as antennas– Good PCB design– Ground and power planes
• Shielding• Basic design rules
– Ground plane– Compact design
• Reduced current loops• Minimum clock frequency
– Components with as long rise / fall time as possible– Decoupling capacitors– Shielding– Star topology– Metal case
LSots opening
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SPICE simulations
• High speed simulation difficult–Not accurate models–Stray capacitance and inductance–Skin effect–Cross talk–Power supply–Radiant effects will need wave simulation
FEM,FEA,TLM…
• No model will represent the absolute truth…
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Software simulation at Ghz
• GREATER HIGH FREQUENCY CAUSE CONCERNS
• As Wave-lengths reduce to package pattern dimensions (@ 5 GHz , l/10 = 5 mm), each trace becomes a radiating antenna :
– Radiated energy = signal loss
– Radiated energy = interference on other electric conductors
– Radiated energy = increased EMC problems
– Radiated energy = damage to living organisms
• Alternative means of conduction will have to be used, when these factors become dangerous:
– Shielded conductors (conductor surrounded by Ground conductor)
– Wave-guides
– Light strands
• Full-wave Analysis becomes absolutely necessary
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Measurements on high speed circuits
• Probe coupling– Probe impedance 8-100pF
parallel with 1-10M– Very important to include with
resonance circuits, as capacitance/inductance alters resonant frequency
Fig. 6.42: Bending of double layer flexible print with different conductor layout. The Figure shows the number of cycles before failure with 5, 10 and 20 mm bending radius and 180° angel of bending. (Data: Schoeller Elektronik). If the copper layer in the bending zone is strained 16 % or more it is likely to fail during the first cycle.
Fig. 6.43: a): Solder lands on flexible prints should be rounded in order to reduce the possibility for failures, b): The contour of the board should be rounded in order to reduce possibilities for tearing (dimensions in inches). The "rabbit ears" on the ends of the metal foil is for obtaining better adhesion to the polyimide. c): Plastic rivets should be used to avoid sharp bends in the interface between the flexible and the rigid parts of the PCB.
Fig. 6.44: Detail of a membrane switch panel. The tail with interconnections to the panel is protected with a laminated foil. Light emitting diodes may be attached with conductive adhesive. Screen printed polymer thick film series resistors may be used.
Fig. 6.45: Contact areas of membrane switch panel with back lighting and window. Examples of lighted text on a dark background and the opposite combination. If a metal dome is used the information has to be next to the key and not underneath it.
Fig. 6.46: The SUSPENS model for the different levels in an electronic system. The symbols are parameters characterising the system and different technologies of the system. They are quantified and used to compare or optimise different possible versions of the system in computer calculations.