1 Frontier Semiconductor JTG, Process Controls, May 30, 2007 www.frontiersemi.com Electrical Issues in Process Integration of SDE/Halo CMOS Junctions Michael Current Frontier Semiconductor, 199 River Oaks Parkway, San Jose, CA 95134 www.frontiersemi.com * Transistor effects of SDE/halo process choices * Junction effects for SDE/halo implants * Metrology options for SDE/halo * Process integration example for ms-anneals Key co-workers: V. Faifer, J. Halim (FSM), P. Timans (Mattson), T. Clarysse (IMEC)
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Electrical Issues in Process Integration of SDE/Halo CMOS … · 2019. 6. 6. · Key co-workers: V. Faifer, J. Halim (FSM), P. Timans (Mattson), T. Clarysse (IMEC) 2 Frontier Semiconductor
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Frontier Semiconductor
JTG, Process Controls, May 30, 2007www.frontiersemi.com
Electrical Issues in Process Integration of SDE/Halo CMOS Junctions
Michael CurrentFrontier Semiconductor, 199 River Oaks Parkway, San Jose, CA 95134
www.frontiersemi.com
* Transistor effects of SDE/halo process choices* Junction effects for SDE/halo implants* Metrology options for SDE/halo* Process integration example for ms-anneals
Key co-workers: V. Faifer, J. Halim (FSM), P. Timans (Mattson), T. Clarysse (IMEC)
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Frontier Semiconductor
JTG, Process Controls, May 30, 2007www.frontiersemi.com
CMOS Transistor: SDE/Halo/Well Dopants
Source Drain
Gate
Oxide
STI STI
SDE SDE
Well
Halo Halo
Metal Metal
Metal
Source Drain
Gate
Oxide
STI STI
SDE SDE
Well
Halo Halo
Metal Metal
Metal
p-MOS
SDE: B, BF2,B10H14, B18H22, B-clusters
PAI: Ge, Si, FCocktails: C, F, N,
C7H7, C16H10
n-MOS
SDE: As, P, SbAs4, P4,As-clusters
PAI: Ge, Si, FCocktails: C, F, N,
C7H7, C16H10
Halo: As, P, Sb,As-clusters
Halo: B, BF2, InB10H14, B18H22, B-clusters
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Frontier Semiconductor
JTG, Process Controls, May 30, 2007www.frontiersemi.com
JTG, Process Controls, May 30, 2007www.frontiersemi.com
Leakage Current Control for Low Power 65 nm
C.H Jan et al. (Intel) IEDM05But for 45 and 32 nm, “no” junction diffusion is allowed !!
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JTG, Process Controls, May 30, 2007www.frontiersemi.com
Metrology Challenges for SDE/Halo (1)Lightly-doped substratesB-doped epi on n-Si (4x1014 d/cm3)(~20 Ohm-cm)
T. Clarysse (IMEC) et al. E-MRS05
For p-USJ on lightly-doped Si:Principal effect is a decrease in Rs value with increasing loading for contact probes (4PP, VPS).
RsL
Pene
tratio
n (n
m)
IRSE
VPS
4 D
imen
s.
SSM
240
0 05
30~15
non-contact 4 probes
> 100
Con
v.4P
P
RsL
Pene
tratio
n (n
m)
IRSE
VPS
4 D
imen
s.
SSM
240
0 05
30~15
non-contact 4 probes
> 100
Con
v.4P
P
RsL
Pene
tratio
n (n
m)
IRSE
VPS
4 D
imen
s.
SSM
240
0 05
30~15
non-contact 4 probes
> 100
Con
v.4P
P
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Frontier Semiconductor
JTG, Process Controls, May 30, 2007www.frontiersemi.com
Metrology Challenges for SDE/Halo (2)Medium-doped substrates
T. Clarysse (IMEC) et al. MRS06
B
As
For p-USJ on medium-doped Si:Huge low Rs error for 4PP and VPS (SRP).RsL and micro-4PP OK to 10 nm epi.Active layer ~2 nm for 10 nm epi.
B-doped epi on medium doped n-Si (7x1017 d/cm3, ~20 um, ~14 Ohm/sq)
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JTG, Process Controls, May 30, 2007www.frontiersemi.com
RsL – Non-Contact Sheet Resistance and Leakage CurrentHow it works
Junction
Depletion
Substrate
Spreading
Modulated LED Beam
Vin Vout
Recombination
Junction
Depletion
Substrate
Spreading
Modulated LED Beam
Vin Vout
Recombination
1. Free carrier creation (by the light) and measurement of the junction photo-voltage signal.
2. Carrier spreading (proportional to Rs).
3. Carrier recombination (leakage current).
IMEC Round Robin for 10 to 100 nm Epi
4PP (WC and EM),Variable spacing 2-probeMicro-4PPRsLOnly RsL (and micro-4PP) are free of junction shorting effects.
4PPRsL
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JTG, Process Controls, May 30, 2007www.frontiersemi.com
SDE/Halo Integration: Sheet Resistance (1)
0100
200300
400500
600700
800
spike fRTPB
fRTPA
fRTPD
fRTPD+D
fRTPC
Rs,
Ohm
/sq
c-Sihalo+anneal
0100
200300
400500
600700
800
spike fRTPB
fRTPA
fRTPD
fRTPD+D
fRTPC
Rs,
Ohm
/sq
c-Sihalo+anneal
Tanneal: B<A<D<D+D<C
Ti=750°C+∆T =550°C(Tp=1300°C)fRTP D 1.5ms
Ti=750°C+∆T =600°C(Tp=1350°C)fRTP C 1.5ms
Ti=700°C+∆T=550°C(Tp=1250°C)fRTP B 1.5ms
Ti=700°C+∆T=600°C(Tp=1300°C)fRTP A 1.5ms
1050°C, 100 ppm O2 in N2Spike anneal
Ti=750°C+∆T =550°C(Tp=1300°C)fRTP D 1.5ms
Ti=750°C+∆T =600°C(Tp=1350°C)fRTP C 1.5ms
Ti=700°C+∆T=550°C(Tp=1250°C)fRTP B 1.5ms
Ti=700°C+∆T=600°C(Tp=1300°C)fRTP A 1.5ms
1050°C, 100 ppm O2 in N2Spike anneal
•B-USJ (0.5keV, 1015 cm-2 );•Ge - PAI (30keV, 1015cm-2);•As- HALO (40keV, 4*1013cm-2); ;•Halo implant annealing: 10 s at 1050C before the PAI or B implants
V. Faifer et al. Insight (USJ07)
Addition of halo profile to SDE increases Rs by ~35% (decreased Xj).
1E+14
1E+15
1E+16
1E+17
1E+18
1E+19
1E+20
1E+21
1E+22
0 100 200 300 400
Depth from Surface , A
Dop
antC
once
ntra
tion
(Ato
ms/
cm3 )
0.5 keV B
40 keV As
10 Ohm-cm p-Si
Xj for 10 Ohm-cm
Xj for halo
SRIM03
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Frontier Semiconductor
JTG, Process Controls, May 30, 2007www.frontiersemi.com
Metrology Challenges for SDE/Halo (3)
200
300
400
500
600
700
0 20 40 60 80 100 120
Probe loading (g)
Shee
t Res
ista
nce
(Ohm
/squ
are)
20 Ohm-cm wafer
RsL
4PP40 keV As haloHalo anneal
0.5 keV B1050 C / 1 s anneal
4PP, no Halo
Lightly-doped (10 ohm-cm)substrates (wide depletion,low leakage) have close agreement between RsL and 4PP measurements.
Transistors (reverse bias ~ -1 V)GenerationTrap-assisted tunneling Band tunnelingContact emissionGate leakage Sub-threshold current
J = Io(A/cm2) * (eqV/kT – 1)
RsL measures the “process dependent” (damage and doping) component of junction leakage, the recombination/ generation current amplitude, Io(A/cm2).
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Forward & Reverse Bias Leakage
1.E-08
1.E-07
1.E-06
1.E-05
1.E+16 1.E+17 1.E+18 1.E+19
Well/Halo concentration level (at/cm3)
Leak
age
curr
ent (
A/c
m2)
Reverse diodeleakageRsL leakage
RsL leakage (at +Vt) is slightly smaller than reverse bias leakage(including band-to-band tunneling), as expected.
1.1015 1.1016 1.10 17 1.10 18 1.10191.10 10
1.10 9
1.10 8
1.10 7
1.10 6
1.10 5
1.10 4
1.10 3
0.01
0.1
1
DOPING CONCENTRATION, dopants/cm3
LEA
KA
GE
CU
RR
EN
T, A
/cm
2
Nmax = 1018 traps/cm3
V= -1 V
V= -26 mV
V= +26 mV
1.1015 1.1016 1.10 17 1.10 18 1.10191.10 10
1.10 9
1.10 8
1.10 7
1.10 6
1.10 5
1.10 4
1.10 3
0.01
0.1
1
DOPING CONCENTRATION, dopants/cm3
LEA
KA
GE
CU
RR
EN
T, A
/cm
2
Nmax = 1018 traps/cm3
V= -1 V
V= -26 mV
V= +26 mV
T. Clarysse et al., Insight07 (USJ07)
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JTG, Process Controls, May 30, 2007www.frontiersemi.com
Junction Leakage in Transistors
J-P. Han et al. Infineon, IBM, Samsung Chartered, IEDM06
c-SiGe c-SiGe
c-Stress Liner
SDE SDE
Channel
40 nm p-MOS transistor
Area of SDE junction is ~2x channel area per transistor.
Junction leakage of ~10-2 A/cm2
exceeds entire operating limits for low-power devices (ITRS05).
Generation leakage currents are determined by implant residual damage and halo doping profiles, measured as recombination currents in RsL from 10-7 to >10-2 A/cm2.
10-6
10-4
10-2
1016 1017 1018
Trap concentration, cm-3
Leak
age
curr
ent d
ensi
ty A
/cm
2
RsL (+0.025 V)
Vr= -0.05V
Vr= -0.5V
Vr= -1V
10-6
10-4
10-2
1016 1017 1018
Trap concentration, cm-3
Leak
age
curr
ent d
ensi
ty A
/cm
2
RsL (+0.025 V)
Vr= -0.05V
Vr= -0.5V
Vr= -1V
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JTG, Process Controls, May 30, 2007www.frontiersemi.com