Electrical Characteristics of Logic Gates Dr. Ashraf Armoush © 2010 Dr. Ashraf Armoush.

Electrical Characteristics of Logic Gates

Dr. Ashraf Armoush

© 2010 Dr. Ashraf Armoush

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Outline

• TTL versions• Electrical Characteristics • Average maximum power dissipation• Switching Characteristics • DC Noise Immunity (Noise Margin)• DC and AC Fan-out• Speed × Power • CMOS Versions• Interfacing TTL and CMOS• Logic Gate Buffers• Open Collector Buffers© 2010 Dr. Ashraf Armoush , An-Najah National University

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TTL

• TTL : Transistor-Transistor Logic• Two transistors are used to drive each output of each chip

• Based on bipolar npn or pnp transistors

• TTL compatible: means that the inputs and outputs of the equipment follow the common rules that apply to the inputs and outputs of all TTL gates

• TTL Family: – 74---XX : commercial version [0 – 70°C] – 54---XX : military version [-55 – 125°C]

© 2010 Dr. Ashraf Armoush , An-Najah National University

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TTL Versions (subfamilies)

1. Standard TTL (74xx) [obsolete] The oldest standard version (late 1960’s) Propagation Delay = 10 ns

2. Low Power TTL (74Lxx) Low power (compared to the original TTL logic family), Very slow (Propagation Delay = 33 ns)

3. Schottky TTL (74Sxx) [obsolete] Introduced in the early 1970’s. High speed applications (Propagation Delay = 3ns)

Switching speed improvement 300% over standard TTL

Use Schottky diod between the base and collector of each transistor (prevent the transistor from going into deep saturation)

4. Low Power Schottky (74LSxx) Low power (≈1/5 supply current). Switching speed is comparable to the standard TTL (Propagation Delay =

10 ns)© 2010 Dr. Ashraf Armoush , An-Najah National University

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Electrical Characteristic

• High-level output voltage (VOH): the minimum voltage on the output pin when the input condition establish logic HIGH at the output.

• LOW-level output voltage (VOL): the maximum voltage on the output pin when the input condition establish logic LOW at the output.

• Low-level input voltage (VIL): the maximum voltage applied at the input that is recognized as a legal LOW level.

• HIGH-level input voltage (VIH): the minimum voltage that needs to be applied at the input to be recognized as a legal HIGH level.

• Output short circuit current (IOS): It is a troubleshooting technique to short a high level output to ground temporarily to verify that a circuit is working correctly

© 2010 Dr. Ashraf Armoush , An-Najah National University

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Electrical Characteristic

•

© 2010 Dr. Ashraf Armoush , An-Najah National University

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Input Output Voltage Ranges

© 2010 Dr. Ashraf Armoush , An-Najah National University

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DC Noise Immunity (Noise Margin)

© 2010 Dr. Ashraf Armoush , An-Najah National University

voltVVV

voltVVV

OLILNL

IHOHNH

3.05.08.0

7.027.2

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL ILOL

IHOH

VV

VV

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Open (floating) Pins

• If you leave a pin (floating), the gate will respond as if that pin were connected to a logic 1.

• Problem: It will act like a radio antenna. any received noise can easily cause plus-sensitive circuits (such as flip-flops) to operate incorrectly.

• Solutions:1. Connect two pins together.

Disadvantages:– Increases the load current which will decrease the fan-out.– Doubles the capacitive

2. Connect them to Vcc3. Connect them to Vcc through a pull-up resistor4. Connect the unused input to an inverter output biased high.

© 2010 Dr. Ashraf Armoush , An-Najah National University

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Open (floating) Pins

© 2010 Dr. Ashraf Armoush , An-Najah National University

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Complementary Metal-Oxide Semiconductor (CMOS) Logic Circuits

• CMOS gates uses voltage-controlled complementary n- and p-channel MOS transistor.

• The important characteristics of CMOS devices are:– high noise immunity – low static power consumption.

• Slower than TTL but with smaller area (high density)

the vast majority of modern integrated circuit manufacturing is on CMOS processes.

• CMOS Families: – Metal gate CMOS (CD40XX) has a rated working voltage of 3 – 15 – Silicon gate CMOS (74CXX) logic has a working voltage range of 2 -6V

© 2010 Dr. Ashraf Armoush , An-Najah National University

N-MOS P-MOS CMOS Inverter

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CMOS Versions (subfamilies)1. CD4000 Series

The oldest CMOS version (1968) Operate over a wide range of VCC [3-15 V] The poorest performance

2. CMOS (74Cxx) [obsolete] The first of CMOS to be pin compatible with TTL (in the mid-1970s), Twice as fast as CD4000 series

3. High Speed CMOS (74HC/HCTxx/) Introduced in the early 1980s. DC fan-out (20 CMOS or 10 TTL) 74HCT has electrical characteristic compatible to TTL (74LS) 74HCxx is 5 times faster than a 74Cxx (tPD = 9 ns) ≈ tPD for 74LSxx

4. Advanced CMOS (74AC/ACTxx) Designed to be competitive with 74AS and 74ALS (late 1980’s) Devices in this series are not pin compatible with their TTL counterparts. Switching speed is comparable to the 74ALS family (tPD = 9 ns)

74ACTxx is designed to have TTL compatible VIH and VIL © 2010 Dr. Ashraf Armoush , An-Najah National University

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Recommended Operating Conditions

• CMOS can operate over a wide range of VCC [2 to 6 V]

• Many of the data sheet tests are specified at three values of VCC [2, 4.5 and 6 V]

Ex: For VCC = 4.7V (standard) • 74HC00 has:

– VIH = 3.15V (problem with TTL interface)

– VIL = 0.9 V

• 74HCT00 has: – VIH = 2.1V (TTL compatible)

– VIL = 0.9 V

© 2010 Dr. Ashraf Armoush , An-Najah National University

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Noise Immunity

• 74HC with VCC = 4.7V– VOH = 4.1V

– VOL = 0.1 V

– VIH = 3.15V

– VIL = 0.9 V

VNH = VOH – VIH = 4.4 – 3.15 = 1.75 V

VNL = VIL – VOL = 0.9 – 0.1 = 0.8 V

Both VNH and VNL are greter than those of its TTL counterpart.

© 2010 Dr. Ashraf Armoush , An-Najah National University

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Interfacing TTL and CMOS

• Conditions for interfacing:

- VOH ≥ VIH

- VOL ≤ VIL

- |IOH| > |IIH|- |IOL|> |IIL|

© 2010 Dr. Ashraf Armoush , An-Najah National University