ELEC 301 Lab 5: Cadence Layout Tutorial 1 - HKUSTvlsi/cadence/lab5.pdfLab 5: Cadence Layout Tutorial 1 Revision: 2.0 Date: July 98 Overview ... You now have finished a pmos transistor,

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ELEC 301Lab 5: Cadence Layout Tutorial 1

Revision: 2.0Date: July 98Overview This lab shows you how to layout a simply inverter using Virtuoso Layout Editor.Virtuoso provides a hierarchical I.C. layout and verification environment that supports allI.C. design techniques, from hand crafting, to automatic placement and routing. Thistutorial will take you step-by-step through the process of handcrafting a simple inverterand perform the design rule checking (DRC) to verify the correctness of the physicaldesign. This layout will correspond to the schematic, which has been created in lab2.

Learning the command in Virtuoso Layout Editor

In virtuoso, you can always seek help from the OpenBook whenever you faced anydifficulty. To begin this lab, you are required to familiar with the virtuoso command,which will be frequently used in the following sections, by going through the OpenBook.To start the OpenBook, type “openbook” in the command window. Then select IC Tools– Layout Design – Virtuoso Layout editor help. Spend at least 15 mins to go thought all4 topics (Cellviews, The LSW, Creating Objects and the Editing Objects).

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Setting Virtuoso Layout Editor Environment

Before you can draw the layout in Virtuoso, you must first create a cellview (view namelayout in cell inv) to contain the layout data. This is done using the same procedures youused previously to create the schematic cellview.

Step 1. Open inv layout in edit mode.

1.1. When you open a layout cellview, you see both the cellview and Layer andSelection Window (LSW). The LSW will appear first along the left side ofthe screen. Next an empty Virtuoso window will appear.

At this point, you may find that the CIW window is overlapped by theEditing window. You should move the windows around so that you have agood view of the LSW window, the Editing window and the CIW. Keep youreye on the CIW messages and the status banner at the top of the Editingwindow.

1.2 The Layer and Selection Window (LSW) allow you to choose the layer onwhich you draw objects (called the “drawing” or “entry” layer).

layer Name Descriptionnwell This is the well put down in

a P-type wafer to provide atub for the PMOS transistors

active Thin oxide region whichidentify active region fortransistors.

poly Polysilicon. Used to makethe gate of the MOS device

pselect P-type implant masknselect N-type implant maskcp Contact cut between poly

and metal1metal1 First level metal. Used for

horizontal routing. E.g.Power and Ground of cells

via First to second level metalcontact cut

metal2 Second level metal. Used forvertical routing. Eg I/O pinof signal.

ca Contact cut between activeand metal1.

text Label for parts.dg Drawing for a layerpn Label the metal which is

used as a I/O pin.

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It can also be used to set the layers to selectable or visible. The detailedprocedure will be given in the following.

1.3. You will notice that there are fourquadrants in your screen. You will want todraw you layouts in the quadrant as figure.There is no specific reason for this otherthan that you will be more comfortableworking with a positive coordinate system.

The spacing between the snap points is exactly 0.2u because all of our layoutfor fabrication can have no finer resolution than 0.2um.

1.4 Before creating transistors layout, you may need to zoom out to givenecessary space for drawing. In Virtuoso, you can find command Zoom underthe menu Window.

Zoom InZoom In By 2Zoom OutZoom Out By 2

Refer to OpenBook for details of command Zoom.

Creating pmso Transistors Layout

This part covers the basic steps used to layout a pmos transistor. You'll use polygons todescribe most of the transistor geometric. The given geometry dimensions are based onthe MOSIS scalable and generic CMOS design rule with lambda = 0.4 micron. You mayneed to refer to the design rule during design process

You will start by drawing the polysilicon gate layer for the pmos transistor. The gateshould be 21λ (8.4u) in width and 2λ (0.8u) in length.

Step 2. In the LSW, click on the active (dg) box.

This refers to the Active Area drawing layer. (dg stands for drawing). Noticethat the top of the LSW now displays the selected layer name. We say thatany geometry you draw will be drawn with the selected drawing layer. Youcan change the selected drawing layer by clicking left on any of the layers inthe LSW menu.

2.1 Click on the Rectangle icon from the left menu (short cut icon),

OR - Select Create - Rectangle from the pull-down menu.

Allows you to draw a box to zoom in on aspecific area.

Zooms in on the current window image by afactor of 2.

Allows you to draw a box into which you wantthe current window image to fit.

Decreases the current window image by a factorof 2.

DrawingArea

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2.2 Drawing a rectangle 16λ (6.4u) in width and 21λ (8.4u) in height asfollowing figure. Remind that each snap point on the layout is 0.2um. To doso, you may want to use a ruler.

In Virtuoso, Select Misc – Ruler. Click on mouse left button to start a rulerand move the cursor. The end of the ruler gives you the current length. Clickagain to complete the ruler.

Anytime, you can press the Escape <ESC> key to terminateany drawing command including Ruler.

To clear the ruler, select Misc-Clear Ruler.

If you have make any mistake, you can delete the unwanted object, highlightthe unwanted object and then select Edit – Delete. In addition, you can stretchthe object if the size is incorrect. Select Edit-Stretch. Click on the edge of theobject you want to stretch, you will see the edge is highlighted. Then clickagain on the new position where the gate width is 4.4u. Hit <ESC> to exitcreates rectangle mode.

2.3. Next, click left on the poly (dg) box in the LSW window, and using Create->Rectangle, draw a poly rectangle with dimension as shown in figure below,such that it is centered on the active rectangle. (It should overlap thisrectangle by 7λ (2.8u) on each side, and the active rectangle should overlap itby 2λ (0.8u) on the top and bottom... this is to satisfy our MOSIS designrules). Congratulations! You have just created your first transistor.

Confused? Right now you are probably thinking to yourself "I don't know allthose rules, and it takes forever to look them all up". Don't worry about them,Cadence is nice enough to check our design rules for us, as we will see later.Fixing most mistakes is fairly easy. For drawing, a good rule of thumb seemsto be that most spacing rules are 0.8um (for example, overlaps, spacingbetween object of the same shape, etc.). Fixing design rule violations isnormally fairly easy.

2.4. By now, we have finished drawing a transistor, however, we haven’tspecified that it is P-Type. To do so, draw a rectangle using pselect (dg),which overlapped the active of the top transistor by 2λ (0.8u). And then, draw

8.4u (gate width)

0.8u (gate length)

2.8u

0.8u

6.4u

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another nwell (dg) overlapped the pselect. The overlap rule for this is thatnwell should overlap active by 6λ (2.4u) as figure.

2.5. We need to connect nwell to vdd!. To do so, we draw a plug for our Nwell.First, draw a 4λ x 4λ (1.6u) active rectangle. Then, place a nselect (since weare plugging an Nwell) region around the active which will overlap it by 2λ(0.8u) on all sides. Move the well plus to the position as following. StretchNwell to overlap it as figure shown.

Performing a Design Rule Check (DRC)

Although our inverter is not yet done, let’s perform a design rule check. It’s always agood practice to perform DRC periodically so that you won't finish a large design withmany errors.

Step 3. To do a DRC choose Verify-DRC, the DRC form will appear. Click on "OK".

Look in the CIW, you should see all the design rules scroll by as they arechecked. When it is done you will see something like:

******* Summary of rule violation for cell "inv layout" *******# errors Violated Rules 4 Active overlap of gate must be at least 3 2 Poly separation to active must be at least 1 6 Total errors found

If you look at your layout, you will see these errors flagged and highlight parts.Lets fix these errors now by referring to the appendix A for detail debugging.

3.1. Re-run the DRC, and make sure your design is correct. Save your design.

0.8upselect

Wellplug

nwellP substrate (i.e. layout window

nwell

S

D

G

B

SG

D

B

Cross section

p+ p+ n+

Current

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Wiring the Transistor

You now have finished a pmos transistor, which are design rule passed. As from theschematic, the pmos transistor of our inverter is connected to the power and ground lines,and the well plugs.

4.2. Let’s first create the output node. We cannot connect N-active and P-activedirectly, so we need to use metal1 to connect them.

• To do so, we need to create 8 active contacts for PMOS and then connectthose contacts with metal1. We also will route our power/ground lines inmetal1. Refer to figure for detailed position.

• To drawing an active contact, first draw a 2λ x 2λ (0.8u) rectangle of ca(dg), ca standing for contact for active.

• Instead of drawing 8 contacts by hand, lets draw one then copy it. To doso, select the contact and issue menu command Edit - Copy. Repeat copycommand for another contacts. Notice that the spacing between contactsshould be 1.2u.

• These are your contacts. MOSIS rules say that contact to metal needs to besurrounded by metal1 and active by 2λ (0.8u). Create two metal1 (dg)rectangles, which surrounds the ca (dg) on both sides of PMOS. Run aDRC to ensure this.

• For the well plug we need to add a contact also, copy and move it into theactive of well plus. It should be overlapped by 1λ (0.4u) on each side withactive.

4.4. Draw the metal1 rectangles for the Power, which should be 5u in height and atleast 10u length. Place it at the upper side of the inverter.

4.5. Stretch the metal1 to touch the power as figure and merge the two metal1.Refer to OpenBook for detail usage of merge.

4.6. By now, you have finished the upper part of the transistor, run a DRC to checkit. The complete view should be as following figure:

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Creating nmos Transistor Layout

You have just finished the pmos part of the inv. Now, you need to go on finished thenmos part also. The procedure is similar to the pmos one.

Step 5 Using the same procedure as drawing pmos transistors, draw another nmostransistor and put in below the pmos transistor with some spaces betweenthem. The gate width of nmos transistor should be 11λ (4.4u) as followingfigure.

5.1 To specify that this transistor is N-type. Draw a nselect (dg) rectangle(instead of the pselect and nwell) around the transistor. Again there shouldbe a 2λ (0.8um) overlap of the active.

5.2 Similar to well plus to the Pmos transistor, we need to connect p-typesubstrate contact to gnd!. You may want to copy the well plug you created(including the select area)and then change the nselect rectangle to pselectrantangle.

Highlight the nselect rectangle and choose Edit - Properties. The editproperties form appear.

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Notice that one property of the rectangle is its layer, in the Layer field,hold down your mouse button, and choose pselect. Click OK.

5.3 Finished wiring the nmos transistor as in pmso one and run DRC again toensure that there is no error.

Wiring the Inverter

You have now finished the two transistors for the inv. The next step is to finished theinternal and external connection for the inv.

Input connection

Step 6 Connect the two transistors’ poly to become the inverter input. To do so,we can stretch either transistor’s poly to touch the other’s one. Refer to thefollowing figure as the guideline.

6.1 In virtuoso, the two-touched poly will already be considered to be one longpoly. However, you may want to merge them to give better appearance.First click on the poly(dg) box in LSW window, highlight the long poly,then select Edit - Other - Merge. The two rectangles will now becomeone.

6.2 Create Input terminal (Signal name "A"). For external connection point,we want to using metal2 so that it can be accessed in both upward anddownward direction. Since we can’t connect poly and metal2 directly, weneed to connect poly to metal1 by using cp (dg) first and then connectmetal1 to metal2 by using via (dg)

• Draw a 0.8u x 0.8u poly contact in cp(dg). Place it between two transistors.

• Draw a poly which overlap cp 0.8u oneach sides.

4.4u

cp(dg)via(dg)

Metal1+

Metal2

Poly+

Metal1

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• Draw a 0.8u x 0.8u via (dg) on the leftside of cp, then place a metal2 (dg)which overlap via 0.4u.

• Connecting both via and cp you justcreated by metal1. It should have 0.8uoverlapping to both. Run a DRC toensure this.

Output Connection

6.3. Create the output node. Draw a rectangle in metal1 (dg) which overlapsthe two metal1 on right side of transistors. Refer to following figure fordetails.

6.4 Create Output terminal

Again, create an external connection point using metal2 and via at theoutput node.

Labeling

6.4. Create Power and Ground labels for identification.

In LSW, select text (dg).

Click on Create - Label.

Fill in "vdd!" as the label name, then place it on the top metal1 line asshown in page.

Create "gnd!" for the lower metal1 line by the same procedures.

6.5. Create labels "A" and "Out" as mentioned above. Refer to the figure forlabel position.

6.6. Run a final DRC, and save your design.

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The complete inverter layout should resemble the following diagram:

Setting Layer Visibility using the LSW

After step 6. You are basically finished the inv layout. However, you may want to checkthe transistor design in each layer. The layer and Selection Window (LSW) allow you toset particular layers selectable and visible.

Step 7. Move the cursor over the cp (dg) layer in the LSW and click the middlemouse button.

The middle mouse button toggles layer visibility. It also automatically setsinvisible layers to be unselectable.

metal1

active

poly

pselect

nselect

via

metal2

nwell

P type substratecontact

Power

label

ca

PNPTransistor

NPNTransistor

InputTerminal

well plus

Power

Partname

Layer name

Figure 1

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The contact layer colour disappears to show that the layer is invisible, andthe layer name turns gray to show that the layer is not selectable.

7.1. Select Window - Redraw in the inv window.

The inv layout is displayed without contacts, since they are drawn on thecp layer.

7.2. Click on the AV (All Visible) button in the LSW.

The coloured square showing the contact layer colour reappears, and theshading on the layer name disappears.

7.3. Select Window - Redrew in the inv window.

The inv layout is re-displayed with cp (dg).You must redraw the windowto see the effect of LSW changes. This way you can make several changesbefore you take the time to redraw a complex design.

7.4 Show you layout to T.A

7.5. Click on Window - Close, the inv layout will be closed.

End of Lab

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Appendix A: Design Rule Check (DRC) Debugging

If you find that there are lots of error appear, don’t be panics. Virtuoso provides an easyenvironment to fixe the errors. Most common errors are design rule violations, which canbe fixed by checking the CIW window.

Step 1. Look at the CIW windows for the errors.

2. Look at the Editing window for the corresponding error parts. Here, there are2 errors in contact spacing on same active. The space should be 3λ (1.2u).From the editing windows, the space between two ca (dg) is highlight thatshould correspond to the error.

3 In addition, you can select Verify-markers-find to find the error marker. Pressapply to get the first error marker and so on.

Error typedescription

Space rule inλ

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4 Select verify-markers-Explain to check for error explanation. User mouse to clickon the error marker that you want it to be explained.

5 Correct the error and re-run the DRC, make sure your design is correct. Save yourdesign.