ELEC 2200-002 Digital Logic Circuits Fall 2015 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal [email protected]Fall 2015, Nov 13 . . Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7 ELEC2200-002 Lecture 7 1
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ELEC 2200-002 Digital Logic Circuits Fall 2015 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor.
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ELEC 2200-002Digital Logic Circuits
Fall 2015Sequential Circuits (Chapter 6)
Finite State Machines (Ch. 7-10)Vishwani D. Agrawal
James J. Danaher ProfessorDepartment of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849http://www.eng.auburn.edu/~vagrawal
[email protected] 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 11
Combinational vs. Sequential CircuitsCombinational circuit:
Output is a function of input only
Contains gates without feedback
Sequential circuit:Output is a function of input and something else stored in the circuit (memory)
Contains gates and feedback
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 22
Toggling 0-1
Odd inversions Even inversions
0 or 1
SR Latch: Basic Sequential Circuit
Feedback loop with even number of inversions (no oscillation?).
Output(s): two sets of logic values from the loop.
Input functions:To control loop logic values
To set the loop in “input control” or “store” state
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 33
Adding Inputs to Feedback Loop
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Q
Q
S
R
NOR Set-Reset (SR) Latch
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 55
Q
Q
S
R
Q
Q
S
R
Q
Q
S
R
Also drawn as Symbol used in Logic schematics
States of Latch
Function S R Q Q
Set 1 0 1 0
Reset 0 1 0 1
Store(Memory)
0 0 Prev. Q Prev. Q
Uncertain 1 1 0 0
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 66
“Store or Memory” Function
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 77
Q = 1 or 0
Q = 0 or 1
S = 0
R = 0
Loop is activated; behavior is sequential.
“Set” Function
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 88
Q = 1
Q = 0
S = 1→ 0
R = 0 → 0
Behavior is combinational.
Loop is broken
“Reset” Function
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 99
Q = 0
Q = 1
S = 0 → 0
R = 1 → 0
Behavior is combinational.
Loop is broken
“Uncertain” Function
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 1010
Q = 0
Q = 0
S = 1
R = 1
Loop is broken in two places and inconsistent values inserted.
“Uncertain” Function
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 1111
Q = 0 → 1 → 0 → 1 → . . .
Q = 0 → 1 → 0 → 1 → . . .
S = 1 → 0
R = 1 → 0
Output oscillates with a period of loop delay. For unequal gatedelays, faster gate will settle to 1 and slower gate to 0. This isknown as RACE CONDITION.
Assume two gates have equal delays.
Excitation Table of SR LatchExcitation inputs
Present state
Next stateFunctionalName of
StateS R Q Q*
0 0 0 0 Store (Memory)0 0 1 1
0 1 0 0Reset
0 1 1 0
1 0 0 1Set
1 0 1 1
1 1 0 Uncertain Race condition1 1 1 Uncertain
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 1212
Characteristic Equation for SR Latch
Next-state function:Treat illegal states as don’t care
Minimize using Karnaugh map
Characteristic equation, Q* = S +RQ
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 1313
1
1 1Q
S
R
State Diagram of SR Latch
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 1414
Q = 0 Q = 1
SR = 10
SR = 01
SR = 0X SR = X0
Clocked SR Latch
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 1515
S
CK
R
Q
Q
SR-latch
Clocked Delay Latch or D-Latch
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 1616
D
CK
Q
Q
SR-latch
Setup and Hold Times of LatchSignals are synchronized with respect to clock (CK).
Operation is level-sensitive:
CK = 1 allows data (D) to pass through
CK = 0 holds the value of Q, ignores data (D)
Setup time is the interval before the clock transition during which data (D) should be stable (not change). This will avoid any possible race condition.
Hold time is the interval after the clock transition during which data should not change. This will avoid data from latching incorrectly.
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 1717
Master-Slave D-Flip-Flop
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 1818
D
CK
Q
Q
Master latch Slave latch
Master-Slave D-Flip-Flop
Uses two clocked D-latches.
Transfers data (D) with one clock period delay.
Operation is edge-triggered:Negative edge-triggered, CK = 1→0, Q = D (previous slide)
Positive edge-triggered, CK = 0→1, Q = D
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 1919
Negative-Edge Triggered D-Flip-Flop
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 2020
Clock period, T
Master openSlave closed
Slave openMaster closedCK
D
Data can change Data can changeDatastable
Time
Setup time Hold timeTriggering clock edge
Symbols for Latch and D-Flip-Flops
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . 2121
CK
D
Q (LATCH)Level sensitive
Q (DFF)Pos. Edge Triggered
Q (DFF)Neg. Edge Triggered
DCK
Q
D
CK
Q
D
CK
Q
ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7
Register (3-Bit Example)Stores parallel data
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 2222
CLRD Q
CK
CLRD Q
CK
CLRD Q
CK
CLR
CK
Q0 Q1 Q2
Parallel output
Parallel inputD0 D1 D2
Shift Register (3-Bit Example)Stores serial data (parallel output)
Delays data (serial output)
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 2323
CLRD Q
CK
CLRD Q
CK
CLRD Q
CK
CLR
DSerialinput
CK
Q0 Q1 Q2
Parallel output
Serialoutput
Two Types of Digital Circuits1. Output depends uniquely on inputs:
Contains only logic gates, AND, OR, . . . No feedback interconnects
2. Output depends on inputs and memory: Contains logic gates, latches and flip-flops May have feedback interconnects Contents of flip-flops define internal state; N flip-flops
provide 2N states; finite memory means finite states, hence the name “finite state machine (FSM)”.
Clocked memory – synchronous FSM No clock – asynchronous FSM
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 2424
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 2525
Mealy and Moore FSMMealy machine: Output is a function of input and the state.
Moore machine: Output is a function of the state alone.
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 2626
S0 S1
1/0
1/1
0/1 0/0
Mealy machine
S0/1 S1/0
1/1
0/0
0/1 1/0
Moore machine
G. H. Mealy, “A Method for Synthesizing Sequential Circuits,” BellSystems Tech. J., vol. 34, pp. 1045-1079, September 1955.E. F. Moore, “Gedanken-Experiments on Sequential Machines,” Annals ofMathematical Studies, no. 34, pp. 129-153 ,1956, Princeton Univ. Press, NJ.
Example 8.17: Robot Control
A robot moves in a straight line, encounters an obstacle and turns right or left until path is clear; on successive obstacles right and left turn strategies are used.
Define input: One bitX = 0, no obstacle
X = 1, an obstacle encountered
Define outputs: Two bits to represent three possible actions.Z1, Z2 = 00 no turn
Z1, Z2 = 01 turn right by a predetermined angle
Z1, Z2 = 10 turn left by a predetermined angle
Z1, Z2 = 11 output not used
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 2727
Example 8.17: Robot Control (Continued . . . 2)
Because turning strategy depends on the action for the previous obstacle, the robot must remember the past.
Therefore, we define internal memory states:State A = no obstacle detected, last turn was left
State B = obstacle detected, turning right
State C = no obstacle detected, last turn was right
State D = obstacle detected, turning left
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 2828
Example 8.17: Robot Control (Continued . . . 3)
Construct state diagram.
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 2929
A
D C
B
A: no obstacle, last turn was leftB: obstacle, turn rightC: no obstacle, last turn was rightD: obstacle, turn left
Input: X = 0, no obstacleX = 1, obstacle
Outputs:Z1, Z2 = 00, no turnZ1, Z2 = 01, right turnZ1, Z2 = 10, left turn
0/001/01
0/000/00
0/00
1/01
1/101/10
X Z1 Z2
Example 8.17: Robot Control (Continued . . . 4)
Construct state table.
Fall 2015, Nov 13 . . .Fall 2015, Nov 13 . . . ELEC2200-002 Lecture 7ELEC2200-002 Lecture 7 3030
A
D C
B
0/001/01
0/000/00
0/00
1/01
1/101/10
X Z1 Z2
A/00
C/00
C/00
A/00
B/01
B/01
D/10
D/10
XPresent 0 1state
A
B
C
D
Nextstate
OutputsZ1, Z2
XY1 Y2 0 1
00
01
11
10
Example 8.17: Robot Control (Continued . . . 5)
State assignment: Each state is assigned a unique binary code. Need log24 = 2 binary state variables to represent 4 states.