ELCT 501: Digital System Design - GUC

ELCT 501:

Digital System Design

Lecture 2: Memory and Programmable Logic

Dr. Mohamed Abd El Ghany,

Department of Electronics and Electrical Engineering

Memory

2 Dr. Mohamed Abd el Ghany


Random Access Memory

(RAM)

Read-Only Memory

(ROM)

Can be read and written

Static Random Access Memory

(SRAM)

Data stored so long as vdd

is applied

6-transistors per cell

Faster

Dynamic Random Access

Memory (DRAM)

Require periodic refresh

Smaller (can be

implemented by 1 or 3

transistors)

slower

A memory device in which permanent

binary information is stored

Mask ROM: The programming is done by

the semiconductor company during the

last fabrication process of the unit

PROM: Once the PROM is programmed,

it cannot be reversed

EPROM: An erasable PROM and can be

erased by exposure to UV light

EEPROM: Can be erased and

programmed with electrical pulses

Flash memory: High-density read/write

memories that are nonvolatile. They have

the ability to retain charge for years with

no applied power

ELCT 501: Digital System

Design

Block Diagram of Memory



2k words N-bit per word

Memory Unit

N-bit Data Input (for Write)

N-bit Data Output (for Read)

K-bit address lines

Read/Write

Chip Enable

N

N

K

Example: 2MB memory, byte-addressable

-N =8 (because of byte-addressability)

-K= 21 (1 word= 8-bit)


Design

Static Random Access Memory

(SRAM)



BitLine BitLine

Wordline (WL)

Typically each bit is implemented with 6 transistors (6T SRAM Cell)

During read, the bitline and its inverse are precharged to Vdd (1) before set

WL=1

During write, put the value on Bitline and its inverse on Bitline_bar before

set WL=1


Design

Dynamic Random Access Memory

(DRAM)



1-transistor DRAM cell

During a write, put value on bitline and then set WL=1

During a read, prechage bitline to Vdd (1) before assert WL to 1

Storage decays, thus requires periodic refreshing (read-sense-write)

Bitline

Wordline (WL)


Design

Memory Description



Memory # of addr # of data lines # of addr lines # of total bytes

1M x 8 1,048,576 8 20 1 MB

2M x 4 2,097,152 4 21 1 MB

1K x 4 1024 4 10 512 B

4M x 32 4,194,304 32 22 16 MB

16K x 64 16,384 64 14 128 KB

Capacity of a memory is described as

# addresses x Word size


Design

How to address Memory



1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit




0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

4x8 Memory

2-to-4 Decoder

A0

A1

CS

Chip Select


Design

How to address Memory







0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

4x8 Memory 2-to-4 Decoder

A0=1

A1=0

CS

Chip Select=1

Access address = 0x1


Design

Use 2 Decoders

9





0

1

2

3

2-to-4 Decoder Row Decoder

A1

A2

CS

1-to-2 Decoder Column Decoder

D0 D1 D2 D3

Tristate Buffer (read)

0 1

A0

Chip Select CS

Dr. Mohamed Abd el Ghany


8x4 Memory


Design

Tristate Buffer



Input Output

En

Input Output

En

Output

En

En Input

Vdd

CMOS circuit

Could amplify signal

Typically used for signal

traveling e.g. bus


Design

Bi-directional Bus using Tri-state

Buffer



Direction (control data flow for read/write)

A

B

Input/Output


Design

Read/Write Memory

12





0

1

2

3


A1

A2

CS


D0 D1 D2 D3

0 1

A0

Chip Select CS

8x4 Memory

Rd / Wr = 0


Design

Read/Write Memory

13





0

1

2

3


A0

A1

CS


D0 D1 D2 D3

0 1

A0

Chip Select=1 CS

8x4 Memory

Rd / Wr = 1


Design

Building Memory in Hierarchy



D3

D2

D1

D0

A19 A18 A17

A0

1Mx4

R/W CS

D7

D6

D5

D4

A19 A18

1Mx4

R/W CS

A17

A0 CS

Design a 1Mx8 using

1Mx4 memory chips


Design




Design a 2Mx4 using

1Mx4 memory chips

A19 A18 A17

A0

1Mx4

R/W CS

A19 A18 A17

A0

1Mx4

R/W CS

A20 1-to-2 Decoder

CS

1

0

D3

D2

D1

D0


Design


16

Design a 2Mx8 using

1Mx4 memory chips

A19 A18 A17

A0

1Mx4

CS R/W

A19 A18 A17

A0

1Mx4

CS R/W

A19 A18 A17

A0

1Mx4

CS R/W

A19 A18 A17

A0

1Mx4

CS R/W

D7

D6

D5

D4

D3

D2

D1

D0

A19 A18 A17

A0

A20 1-to-2 Decoder

CS

1

0

Dr. Mohamed Abd el Ghany

ELCT 501: Digital System Design - GUC

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