E.G.S.Pillay Engineering College, Nagapattinam Department ...

E.G.S.Pillay Engineering College, NagapattinamDepartment of Electronics and Communication Engineering

Questions and AnswersEC 6504 -Microprocessor & Microcontroller

Part -A - Unit I

1. Define Microprocessor. [APR/MAY 2011]CSE/IT]Microprocessor is a multipurpose, programmable, clock-driven, register based electronic device that

reads binary instructions from a storage device called memory, accepts binary data as input and processes dataaccording to those instructions, and provides as output.

2. Define mnemonics.The short-hand form of describing the instructions is called mnemonics. The mnemonics are given by

the manufacturers of microprocessors and programmable devices.

3. What are the basic units of a microprocessor?The basic units or blocks of a microprocessor are ALU, an array of registers and control unit.

4. What is Assembly Language?A medium of communication with a computer in which programs are written in mnemonics. Binaryinstructions are given abbreviated names called mnemonics, which form the assembly language fora given processor.

5. What is Machine Language?The binary medium of communication with a computer through a designed set of instructionsspecific to each computer.

6. List the limitations of 8 bit microprocessor:Lower Execution SpeedIt can address less memory sizeFew instructions are available.

7. List the four operations commonly performed by MPU ( Micro processing Unit)?Memory Read : Reads data (or instructions) from memory.Memory Write: Writes Data (or instructions) into memory.I/O Read: Accepts data from input devices.I/O Write: Sends data to output devices.

8. Write about RST pins in 8085.` In 8085, three RST pins are available, such as RST 7.5, RST 6.5 , RST 5.5 RST represents RestartInterrupts. These are vectored interrupts that transfer the program control to specific memory locations. Theyhave higher priorities than the INTR interrupt. Among these three, the priority order is 7.5, 6.5,5.5.

9. What is the clock frequency of microprocessor 8085?1. It can operate with 3MHZ clock frequency.2. 8085A-2 version can operate maximum of 5MHZ .

10. Draw and specify the complete bit configuration of 8085 flag Register? (M/J-2013)

D7 D6 D5 D4 D3 D2 D1 D0S Z AC P CY

S- Sign Flag . If D7 =1 , then sign flag is set, otherwise rest.

Z-Zero flag. If ALU operation results in zero, then this flag is set, Otherwise it is reset. AC-Auxilliary flag. In an arithmetic operation ,when a carry is generated by digit D3 and

passed on to digit D4, the AC flag is set. Otherwise it is reset. P-Parity Flag. If the result of an arithmetic or logic operation has an even number of 1’s

then this flag is set. Otherwise it is reset. CY-Carry Flag. If an arithmetic operation results in a carry, the carry flag is set. Otherwise

it is reset.

11. Mention the categories of instruction and give two examples for each category (or)What are the classifications of instruction set of 8085? [NOV/DEC 2008] MEE](Or) What are different types of instruction available in 8085? [APR/MAY 2008 ] IT ]

The instructions of 8085 can be categorized into the following five Data transfer MOV Rd,Rs, STA 16-bit Arithmetic ADD R DCR M Logical XRI 8-bit RAR Branching JNZ CALL 16-bit Machine control HLT NOP

12. List the control and status signals available in 8085. [NOV/DEC 2010]CSE/IT]----- ------ ----

ALE , RD, WR, IO/M, S1, S0 , ALE-Address Latch Enable

----- ----RD – Read Control Signal WR – Write Control Signal

---

IO/M - To specify I/O or memory operationS1 , S0 – Status signals

13. What is the necessary to have two status lines S1 and S0 in 8085? [APR/MAY 2008] IT]It is used to identify the current operations of the data bus. These are listed below

S1 S0 OPERATION0 0 HALT0 1 WRITE1 0 READ1 1 FETCH

14. What is the function of the Program Counter in 8085? [APR/MAY 2011] CSE/ITProgram is a sequence of instructions.Microprocessor fetches these instructions from memory and executes them sequentially. The

program counter is a special purpose register which, at a given time, stores the address of the next instructionto be fetched. It acts as a pointer to next instructions.

15. What is Stack Pointer?The stack is a reserved area of the memory in the RAM where the temporary information may be

stored. A 16-bit stack pointer is used to hold the address of the most recent stack entry.



Part -B - Unit I

1. Explain the 8086 architecture with neat sketch .

Ans:

Internal Architecture of 8086•8086 has two blocks BIU and EU.•The BIU performs all bus operations such as instruction fetching, reading and writing operands for memoryand calculating the addresses of the memory operands. The instruction bytes are transferred to the instructionqueue.•EU executes instructions from the instruction system byte queue.•Both units operate asynchronouslyto give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. Thisresults in efficient use of the system bus and system performance. •BIU contains Instruction queue, Segmentregisters, Instruction pointer, Address adder. •EU contains Control circuitry, Instruction decoder, ALU,Pointer and Index . register, Flag register.

BUS INTERFACR UNIT:•It provides a full 16 bit bidirectional data bus and 20 bit address bus.•The bus interface unit is responsible for performing all external bus operations.Specifically it has the following functions:•Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.•TheBIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. •Thisqueue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, ithas room for at least two more bytes and at the same time the EU is not requesting it to read or write operandsfrom memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.•These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches twoinstruction bytes in a single memory cycle. After a byte is loaded at the input end of the queue, itautomatically shifts up through the FIFO to the empty location nearest the output.•The EU accesses the queue from the output end. It reads one instruction byte after the other from the outputof the queue. If the queue is full and the EU is not requesting access to operand in memory.•These intervals ofno bus activity, which may occur between bus cycles are known as

Idle state. •If the BIU is already in the process of fetching an instruction when the EU request it to read orwrite operands from memory or I/O, the BIU first completes the the instruction fetch bus cycle beforeinitiating the operand read / write cycle. •The BIU also contains a dedicated

adder which is used to generate the 20bit physical address that is output on the address bus. This address isformed by adding an appended 16 bit segment address and a 16 bit offset address.•For example: The physical address of the next instruction to be fetched is formed by combining the currentcontents of the code segment CS register and the current contents of the instruction pointer IP register. •TheBIU is also responsible for generating bus control signals such as those for memory read or write and I/O reador write.

EXECUTION UNITThe Execution unit is responsible for decoding and executing all instructions. •The EU extracts instructionsfrom the top of the queue in the BIU, decodes them,generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cyclesto memory or I/O and perform the operation specified by the instruction on the operands.•During theexecution of the instruction, the EU tests the status and control flags and updates them based on the results ofexecuting the instruction.•If the queue is empty, the EU waits for the next instruction byte to be fetched andshifted to top of the queue.•When the EU executes a branch or jump instruction, it transfers control to a location corresponding toanother set of sequential instructions. •Whenever this happens, the BIU automatically resets the queue andthen begins to fetch instructions from this new location to refill the queue.

2. Briefly explain about 8086 Instruction Sets.Ans:

1. Data transfer instructionsPUSH Copy specified word to top of stack.POP Copy word from top of stack to specific location.PUSH(80186/80188 only) Copy all registers stack.POPA (80186/80l88 only) Copy words f stack to all registers.XCHG Exchange bytes or exchange words.XLAT Translate a byte in AL using a table in memory.

Simple input and output port transfer instructions:IN Copy a byte or word from specified port to accumulator.OUT Copy a byte or word from accumulator specified port.

Special address transfer instructions:LEA Load effective address of operand in specified register.LDS Load DS register and other specified register from memory.LES Load ES register and other specified register from memory.

Flag transfer instructions:LAHF Load (copy to) AH with the low byte the flag register.SAHF Store (copy) AH register to low byte of register.PUSHF Copy flag register to top of stack.POPF Copy word at top of stack to flag register

2. Arithmetic instructionsADD Add specified byte to byte or specified word to word.ADC Add byte + byte + carry flag or word + word + carry flag.INC Increment specified byte or specified by 1.AAA ASCII adjust after addition.DAA Decimal (BCD) adjust after addition.SUB Subtract byte from byte or word from word.SBB Subtract byte and carry flag from byte word and carry flag from word.

DEC Decrement specified byte or specified word by l.NEG Negate – invert each bit of a specified byte or word and add 1

(form 2’s complement).CMP Compare two specified bytes or two specified wordAAS ASCII adjust after subtraction.DAS Decimal (BCD) adjust after subtraction.

Multiplication InstructionsMUL Multiply unsigned byte by byte or unsigned word by wordIMUL Multiply signed byte by byte or signed word by wordAAM ASCII adjust after multiplication

Division Instructions

DIV Divide unsigned word by byte or unsigned double word by wordIDIV Divide signed word by byte or signed double word by wordAAD ASCII adjust before divisionCBW Fill upper byte of word with copies of sign bit of lower byteCWD Fill upper word of double word with copies of sign bit of lower word

2. Logic and Bit manipulation instructions (AND, OR, XOR) Logicinstructions:

NOT Invert each bit in a byte or wordAND AND the content of a byte or a word with another byte or wordOR OR the content of a byte or a word with another byte or wordXOR Exclusive OR the content of a byte or a word with another byte or word

Shift instructions:SHL/SAL Shift bits of word or byte left, put zero(s) in LSB(s)SHR Shift bits of word or byte right, put zero(s) in MSB(s)SAR Shift bits of word or byte right, copy old MSB into new MSB

Rotate instructions:ROL Rotate bits of byte or word left, MSB to LSB and to CFROR Rotate bits of byte or word right, LSB to MSB and to CFRCL Rotate bits of byte or word left, MSB to CF and CF to LSBRCR Rotate bits of byte or word right, LSB to CF and CF to MSB

3. String instructionsA string is a series of bytes or a series of words in sequential memory locations. A string often consists

of ASCII character codes. In the list, a ”/” is used to separate different mnemonics for the same instruction. Usethe mnemonic which most clearly describes the function of the instruction in a specific application. A ”B” In amnemonic is used to specifically indicate that a string of bytes is to be acted upon. A ”W” In the mnemonic isused to indicate that a string of words Is to be acted upon.An instruction prefix. Repeat following instruction until CX =0

REPE/REPZ An instruction prefix. Repeat instruction until CX = 0 or zero Flag ZF!=1REPNE/REPNZ An instruction prefix. Repeat until CX = 0 or ZF = 1MOVS/MOVSB/MOVSW Move byte or word from one string to anotherCOMPS/COMPSB/COMPSW Compare two string bytes or two string wordsINS/INSB/INSW (80186/80188) Input string byte or word from portOUTS/OUTSB/OUTSW (80186/80l88) output string byte or word to portSCAS/SCASB/SCASW Scan a string. Compare a string byte with a byte in AL or a string wordwith a word in AXLODS/LODSB/LODSW load string byte into AL or string word into AXSTOS/STOSB/STOSW Store byte from AL or word from AX into string

4. Program execution transfer instructionsInstructions are used to tell the 8086 to start fetching instructions from some new address, rather than continuingin sequence.Unconditional transfer instructions:

CALL Call a procedure (subprogram), save return address on stackRET Return from procedure to calling programJMP Go to specified address to get next instruction

Conditional transfer instructions:A ”/”is used to separate two mnemonics which represent the same instruction. Use the mnemonic which

most dearly describes the decision condition in a specific program. These instructions are often used after acompare instruction. The terms below and above refer to unsigned binary numbers. Above means larger in

magnitude. The terms greater than or less than refer to signed binary numbers. Greater than means morepositive.

JA/JNBE Jump if above/Jump if not below or equalJAE/JNB Jump if above or equal/Jump if not belowJB/JNAE Jump if below/Jump if not above or equalJBE/JNA Jump if below or equal/Jump if not aboveJC Jump if carry flag CF 1

JE/JZ Jump if equal/Jump if zero flag ZF = 1JG/JNLE Jump if greater/Jump if not less than or equalJGE/JNL Jump if greater than or equal Jump if not less thanJL/JNGE Jump if less than/Jump if not greater than or equalJLE/JNG Jump if less than or equal/Jump if not greater thanJNC Jump if no carry (CF = 0)JNE/JNZ Jump if not equal/lump if not ’ zero (ZF = 0)JNO Jump if no overflow (overflow flag OF = 0)JNP/JPO Jump if not parity/Jump if parity odd (PF = 0)JNS Jump if not sign (sign flag SF=0)JO Jump if overflow flag OF=1JP/JPE Jump if parity/Jump if parity even (PF =1)JS Jump if sign (SF = 1)

Iteration control instructions:These instructions can be used to execute a series of instructions some number of times. Here mnemonicsseparated by a ”/” represent the same instruction. Use the one that best fits the specific application.

LOOP Loop through a sequence of instructions until CX= 0LOOPE/LOOPZ Loop through a sequence instructions while ZF= l and CX != 0LOOPNE/LOOPNZ Loop through a sequence instructions while ZF=0 and CX != 0JCXZ Jump to specified address if CX=0

Interrupt instructions:INT Interrupt program execution call service procedureINTO Interrupt program execution OF =1IRET Return from interrupt se procedure to main program

High-level language interface instructions:ENTER (80l86/80188 only) Enter procedureLEAVE (80l86/80188 only) Leave procedureBOUND (80l86/80188 only) Check effective address within specified array bounds

5. Processor control instructionsFlag set/clear instructions:

STC Set carry flag CF to 1CLC Clear carry flag CF to 0CMC Complement the state of the carry flag CFSTD Set direction flag DF to l (decrement string pointers)CLD Clear direction flag DF to 0STI Set interrupt enable flag to 1 (enable INTR input)CLI Clear interrupt enable flag to 0 (disable INTR input)

Execution control instructions:HLT Halt (do nothing) until interrupt or resetWAIT Wait (do nothing) until signal on the test pin is lowESC Escape to external coprocessor such as 8087 or 8089LOCK An instruction prefix. Prevents another processor from taking the bus whilethe adjacent instruction executesNOP No action except fetch and decode processor

3. Explain about 8086 Addressing Modes

The 80x86 processors let you access memory in many different ways. The 80x86 memory addressingmodes provide flexible access to memory, allowing you to easily access variables, arrays, records,

pointers, and other complex data types. Mastery of the 80x86 addressing modes is the first steptowardsmastering80x86assemblylanguage.When Intel designed the original 8086 processor, they provided it with a flexible, though limited, setof memory addressing modes. Intel added several new addressing modes when it introduced the80386 microprocessor. Note that the 80386 retained all the modes of the previous processors; the newmodes are just an added bonus. If you need to write code that works on 80286 and earlier processors,you will not be able to take advantage of these new modes. However, if you intend to run your codeon 80386sx or higher processors, you can use these new modes. Since many programmers still needto write programs that run on 80286 and earlier machines, it's important to separate the discussion ofthese two sets of addressing modes to avoid confusing them.

8086 Register Addressing ModesMost 8086 instructions can operate on the 8086's general purpose register set. By specifying the nameof the register as an operand to the instruction, you may access the contents of that register. Considerthe 8086 MOv (move) instruction:

MOV destination, sourceThis instruction copies the data from the source operand to the destination operand. The eight and 16bit registers are certainly valid operands for this instruction. The only restriction is that both operandsmust be the same size. Now let's look at some actual 8086 mov instructions:

1. MOV AX, BX ; Copies the value from BX into AX2. MOV DL, AL ; Copies the value from AL into DL3. MOV SI, DX ; Copies the value from DX into SI4. MOV SP, BP ; Copies the value from BP into SP5. MOV DH, CL ; Copies the value from CL into DH6. MOV AX, AX ; Yes, this is legal!

Remember, the registers are the best place to keep often used variables. As you'll see a little later,instructions using the registers are shorter and faster than those that access memory. Throughout thischapter you'll see the abbreviated operands reg and r/m (register/memory) used wherever you may useone of the 8086's general purpose registers.In addition to the general purpose registers, many 8086 instructions (including the mov instruction)allow you to specify one of the segment registers as an operand. There are two restrictions on the useof the segment registers with the mov instruction. First of all, you may not specify cs as the destinationoperand, second, only one of the operands can be a segment register. You cannot move data from onesegment register to another with a single mov instruction. To copy the value of cs to ds, you'd have touse some sequence like:

MOV AX, CSMOV DS, AX

You should never use the segment registers as data registers to hold arbitrary values. They should onlycontain segment addresses. But more on that, later. Throughout this text you'll see the abbreviatedoperand sreg used wherever segment register operands are allowed (or required).8086 Memory Addressing ModesThe 8086 provides 17 different ways to access memory. This may seem like quite a bit at first, butfortunately most of the address modes are simple variants of one another so they're very easy to learn.And learn them you should! The key to good assembly language programming is the proper use ofmemory addressing modes.The addressing modes provided by the 8086 family include displacement-only, base, displacement plusbase, base plus indexed, and displacement plus base plus indexed. Variations on these five formsprovide the 17 different addressing modes on the 8086. See, from 17 down to five. It's not so bad afterall!The Displacement Only Addressing ModeThe most common addressing mode, and the one that's easiest to understand, is the displacement-only(or direct) addressing mode. The displacement-only addressing mode consists of a 16 bit constant thatspecifies the address of the target location. The instruction mov al,ds:[8088h] loads the al register witha copy of the byte at memory location 8088h. Likewise, the instruction mov ds:[1234h],dl stores thevalue in the dl register to memory location 1234h:

7.

The displacement-only addressing mode is perfect for accessing simple variables. Of course, you'dprobably prefer using names like "I" or "J" rather than "DS:[1234h]" or "DS:[8088h]". Well, fear not,you'll soon see it's possible to do just that.Intel named this the displacement-only addressing mode because a 16 bit constant (displacement)follows the mov opcode in memory. In that respect it is quite similar to the direct addressing mode onthe x86 processors (see the previous chapter). There are some minor differences, however. First of all,a displacement is exactly that- some distance from some other point. On the x86, a direct address canbe thought of as a displacement from address zero. On the 80x86 processors, this displacement is anoffset from the beginning of a segment (the data segment in this example). Don't worry if this doesn'tmake a lot of sense right now. You'll get an opportunity to study segments to your heart's content alittle later in this chapter. For now, you can think of the displacement-only addressing mode as a directaddressing mode. The examples in this chapter will typically access bytes in memory. Don't forget,however, that you can also access words on the 8086 processors :

By default, all displacement-only values provide offsets into the data segment. If you want to providean offset into a different segment, you must use a segment override prefix before your address. Forexample, to access location 1234h in the extra segment (ES) you would use an instruction of the formmov ax,es:[1234H]. Likewise, to access this location in the code segment you would use the instructionmov ax, cs:[1234H]. The ds: prefix in the previous examples is not a segment override. The CPU usesthe data segment register by default. These specific examples require ds: because of MASM'ssyntactical limitations.The Register Indirect Addressing ModesThe 80x86 CPUs let you access memory indirectly through a register using the register indirectaddressing modes. There are four forms of this addressing mode on the 8086, best demonstrated by thefollowing instructions:

MOV AL, [BX]MOV AL, [BP]MOV AL, [SI]MOV AL, [DI]

As with the x86 [BX] addressing mode, these four addressing modes reference the byte at the offsetfound in the BX, BP, SI, or DI register, respectively. The [BX], [SI], and [DI] modes use the DSsegment by default. The [BP] addressing mode uses the stack segment (SS) by default.You can use the segment override prefix symbols if you wish to access data in different segments. Thefollowing instructions demonstrate the use of these overrides:

MOV AL, CS:[BX]MOV AL, DS:[BP]MOV AL, SS:[SI]MOV AL, ES:[DI]

Intel refers to [BX] and [BP] as base addressing modes and bx and bp as base registers (in fact, BPstands for base pointer). Intel refers to the [SI] and [DI] addressing modes as indexed addressing modes(SI stands for source index, DI stands for destination index). However, these addressing modes arefunctionally equivalent. This text will call these forms register indirect modes to be consistent.

8.

9.Indexed Addressing ModesThe indexed addressing modes use the following syntax:

MOV AL, DISP [BX]MOV AL, DISP [BP]MOV AL, DISP [SI]MOV AL, DISP [DI]

If BX contains 1000h, then the instruction MOV CL, 20H [BX] will load cl from memory location DS:1020H. Likewise, if BP contains 2020h, MOV DH, 1000H [BP] will load dh from location SS:3020.The offsets generated by these addressing modes are the sum of the constant and the specified register. Theaddressing modes involving BX, SI, and DI all use the data segment, the DISP[BP] addressing mode uses thestack segment by default. As with the register indirect addressing modes, you can use the segment overrideprefixes to specify a different segment:

MOV AL, SS:DISP [BX]MOV AL, ES:DISP [BP]MOV AL, CS:DISP [SI]MOV AL, SS:DISP [DI]

10.

You may substitute SI or DI in the figure above to obtain the [SI+DISP] and [DI+DISP] addressingmodes.

Note that Intel still refers to these addressing modes as based addressing and indexed addressing.Intel's literature does not differentiate between these modes with or without the constant. If you look athow the hardware works, this is a reasonable definition. From the programmer's point of view, however,these addressing modes are useful for entirely different things. Which is why this text uses differentterms to describe them? Unfortunately, there is very little consensus on the use of these terms in the80x86 world.Based Indexed Addressing ModesThe based indexed addressing modes are simply combinations of the register indirect addressing modes.These addressing modes form the offset by adding together a base register (BX or BP) and an indexregister (SI or DI). The allowable forms for these addressing modes are

MOV AL, [BX][SI]MOV AL, [BX][DI]MOV AL, [BP][SI]MOV AL, [BP][DI]

Suppose that BX contains 1000h and SI contains 880H. Then the instructionMOV AL, [BX][SI]

Would load al from location DS:1880H. Likewise, if BP contains 1598h and DI contains 1004,MOV AX, [BP+DI] will load the 16 bits in ax from locations SS: 259C and SS:259D.

The addressing modes that do not involve BP use the data segment by default. Those that have BP asan operand use the stack segment by default.

You substitute DI in the figure above to obtain the [BX+DI] addressing mode.

You substitute DI in the figure above for the [BP+DI] addressing mode.Based Indexed Plus Displacement Addressing ModeThese addressing modes are a slight modification of the base/indexed addressing modes with theaddition of an eight bit or sixteen bit constant. The following are some examples of these addressingmodes:

MOV AL, DISP[BX][SI]MOV AL, DISP[BX+DI]MOV AL, [BP+SI+DISP]MOV AL, [BP][DI][DISP]

You may substitute DI in the figure above to produce The [BX+DI+DISP] addressing mode.

You may substitute DI in the figure above to produce the [BP+DI+DISP] addressing mode. SupposeBP contains 1000H, BX contains 2000H, SI contains 120H, and DI contains 5. Then MOV Al,10H[BX+SI] loads al from address DS: 2130; MOV CH,125H[BP+DI] loads CH from location SS:112A;and MOV BX,CS:2[BX][DI] loads BX from location CS:2007

4. Write notes about Assembler Directives.ASSUMEDB - Defined Byte.DD - Defined Double WordDQ - Defined Quad WordDT - Define Ten BytesDW - Define Word

ASSUME Directive - The ASSUME directive is used to tell the assembler that the name of the logical segmentshould be used for a specified segment. The 8086 works directly with only 4 physical segments: a Codesegment, a data segment, a stack segment, and an extra segment.

Example:ASSUME CS: CODE; This tells the assembler that the logical segment named CODE contains the

instruction statements for the program and should be treated as a code segment.ASUME DS: DATA; this tells the assembler that for any instruction which refers to a data in thedata segment, data will found in the logical segment DATA.DB - DB directive is used to declare a byte-type variable or to store a byte in memory location.

Example:1. PRICE DB 49h, 98h, 29h; declare an array of 3 bytes, ; named as PRICE and initialize.2. NAME DB ‘ABCDEF’; Declare an array of 6 bytes and ; initialize with ASCII code for letters3. TEMP DB 100 DUP (?) ;Set 100 bytes of storage in memory and give it the name as TEMP, but leave

the 100 bytes uninitialized. Program instructions will load values into these locations.DW - The DW directive is used to define a variable of type word or to reserve storage location of type wordin memory.Example:

MULTIPLIER DW 437Ah ; this declares a variable of type word and named it as MULTIPLIER.This variable is initialized with the value 437Ah when it is loaded into memory to run.

EXP1 DW 1234h, 3456h, 5678h ; this declares an array of 3 words and initialized with specifiedvalues.

STOR1 DW 100 DUP(0); Reserve an array of 100 words of memory and initialize all words with0000.Array is named as STOR1.

END - END directive is placed after the last statement of a program to tell the assembler that this isthe end of the program module. The assembler will ignore any statement after an END directive. Carriagereturn is required after the END directive.

ENDP - ENDP directive is used along with the name of the procedure to indicate the end of aprocedure to the assemblerExample:

SQUARE_NUM PROCE; It start the procedure; Some steps to find the square root of a numberSQUARE_NUM ENDP; Hear it is the End for the procedureEND - End ProgramENDP - End ProcedureENDS - End SegmentEQU - EquateEVEN - Align on Even Memory AddressEXTRNENDS - This ENDS directive is used with name of the segment to indicate the end of that logic

segment.Example:

CODE SEGMENT; Hear it Start the logic ;segment containing code ; Some instructions statementsto perform ;the logical operation

CODE ENDS ;End of segment named as ;CODEEQU - This EQU directive is used to give a name to some value or to a symbol. Each time the assembler

finds the name in the program, it will replace the name with the value or symbol you given to that name.Example:

FACTOR EQU 03H; you has to write this statement at the starting of your program and later in theprogram you can use this as follows

ADD AL, FACTOR; When it codes this instruction the assembler will code it as ADDAL, 03H ;Theadvantage of using EQU in this manner is, if FACTOR is used many no of times in a program and you want tochange the value, all you had to do is change the EQU statement at beginning, it will changes the rest of all.

EVEN - This EVEN directive instructs the assembler to increment the location of the counter to thenext even address if it is not already in the even address. If the word is at even

address 8086 can read a memory in 1 bus cycle. If the word starts at an odd address, the 8086 will take2 bus cycles to get the data. A series of words can be read much more quickly if they are at even address. WhenEVEN is used the location counter will simply incremented to next address and NOP instruction is inserted inthat incremented location.Example:

DATA1 SEGMENT; Location counter will point to 0009 after assembler reads; next statementSALES DB 9 DUP (?); declare an array of 9 bytesEVEN; increment location counter to 000AH

RECORD DW 100 DUP( 0 ) ;Array of 100 words will start from an even address for quicker readDATA1 ENDSGROUP - Group Related SegmentsLABLENAMEOFFSETORG - OriginateGROUP - The GROUP directive is used to group the logical segments named after the directive into

one logical group segment.INCLUDE - This INCLUDE directive is used to insert a block of source code from the named file

into the current source module.PROC - ProcedurePTR - PointerPUBLCSEGMENTSHORTTYPEPROC - The PROC directive is used to identify the start of a procedure. The term near or far is used

to specify the type of the procedure.Example:

SMART PROC FAR ; This identifies that the start of a procedure named as SMART and instructs theassembler that the procedure is far .SMART ENDPThis PROC is used with ENDP to indicate the break of the procedure.

PTR - This PTR operator is used to assign a specific type of a variable or to a label.Example:

INC [BX]; This instruction will not know whether to increment the byte pointed to by BX or a wordpointed to by BX.INC BYTE PTR [BX] ;increment the byte ;pointed to by BX This PTR operator can also be used tooverride the declared type ofvariable . If we want to access the a byte in an array WORDS DW 437Ah, 0B97h,

MOV AL, BYTE PTR WORDSPUBLIC - The PUBLIC directive is used to instruct the assembler that a specified name or label will

be accessed from other modulesExample:

PUBLIC DIVISOR, DIVIDEND; these two variables are public so these are available to all modules.If an instruction in a module refers to a variable in another assembly module, we can access that module bydeclaring as EXTRN directive.TYPE - TYPE operator instructs the assembler to determine the type of a variable and determines the numberof bytes specified to that variable.Example:

Byte type variable – assembler will give a value 1Word type variable – assembler will give a value 2Double word type variable – assembler will give a value 4 ADD BX, TYPE WORD_ ARRAY; hearwe want to increment BX toPoint to next word in an array of words.

5.explain about Linking and relocation.Ans:LINKER• A linker is a program used to join together severalobject files into one large object file.• The linker produces a link file which contains thebinary codes for all the combined modules.The linker program is invoked using the following options.C> LINK or C>LINK MS.OBJThe loader is a part of the operating systemand places codes into the memory after

reading the ‘.exe’ file• A program called locator reallocates thelinked file and creates a file for permanentlocation of codes in a standard format.

Loader->Loader is a utility program which takes object code asinput prepares it for execution and loads theexecutablecode into the memory .->Loader is actually responsible for initializing theprocess of execution.Functions of loaders:1.It allocates the space for program in the memory(Allocation)2.It resolves the code between the object modules(Linking)3. some address dependent locations in the program, address constantsmust be adjusted according to allocated space(Relocation)4. It also places all the machine instructions and data of correspondingprograms and subroutines into the memory .(Loading)Relocating loader (BSS Loader)• When a single subroutine is changed then all the subroutine needs to be reassembled.• The binary symbolic subroutine (BSS) loader used in IBM 7094 machine is relocating loader.• In BSS loader there are many procedure segments• The assembler reads one sourced programand assembles each procedure segment independently214 The output of the relocating loader is the object program• The assembler takes the source program as input;this source program may call some external routines.

SEGMENT COMBINATION:ASM-86 assembler regulating the way segments with thesame name are concatenated & sometimes they areoverlaid.Form of segment directive:Segment name SEGEMENT Combine-typePossible combine-type are:• PUBLIC• COMMON• STACK• AT• MEMORYProcedure is a part of code that can be called fromyour program in order to make some specific task.Proceduresmake program more structural andeasier to understand.• syntax for procedure declaration:

name PROC…………. ; here goes the code…………. ; of the procedure ...RETname ENDPhere PROC is the procedure name.(used in top & bottom)RET - used to return from OS. CALL-call a procedurePROC & ENDP – complier directivesCALL & RET - instructions

6.What is Interrupt service routine? Explain it with example.

Divide by zero interrupt (Type 0):When the quotient from either a DIV or IDIV is too large to fit in the result register,8086 will

automatically execute type 0 interrupt.Single step interrupt (Type 1):

The type 1 interrupt is the single step trap. In the single step mode, system will execute one instructionand wait for the further direction from user. Then user can examine the contents of register and memorylocations and if they are correct user can tell the system to execute the next instructions. This is feature is usefulfor debugging assembly language program.

An 8086 system is used in the single step mode by setting the trap flag. If the trap flag is set, the 8086will automatically execute a type 1 interrupt after execution of each instruction. But the 8086 has no suchinstruction to directly set or reset the trap flag. These operations can be performed by tasking the flag registercontents into memory, changing the memory contents so to set or reset trap flag and save the memory contentsinto flag.Non Mask able interrupt (Type 2):

As the name suggests, this interrupt cannot be disabled by any software instructions. Thos interrupt isactivated by low to high transition on 8086 NMI input pin. In response 8086 will do a type 2 interrupt.Breakpoint Interrupt ((Type 3):

The type 3 interrupt is used to implement break point function in the system. The type 3 interrupt isproduced by execution of the INT 3 instruction. Breakpoint function is often used as debugging aid in caseswhere single stepping provides more detail than wanted. When you insert a breakpoint the system executes theinstructions up to the breakpoint and then goes to the breakpoint procedure. In the breakpoint procedures youcan write a program to display register contents, memory contents and other information that is required todebug your program. You can insert as many breakpoints as you want in your program.Overflow Interrupt:

The type 4 interrupt is used as to check overflow condition after any signed arithmetic operation in thesystem. The 80867 overflow flag OF, will be represented in the destination register or memory location.

For example if you add the 8-bit signed number 0111 1000 (+120 decimal) and the 8 bit signed number0110 1010 (+106 decimal) result is 1110 0010 (-98 decimal).In signed numbers, MSB is reserved for sign andother bits represent magnitude of the numbe3r.In the previous example after addition of two 8 bit signednumbers result is negative since it is too large to fit in

7 bits. To detect this condition in the program, you can put interrupt on overflow instructions, INTOimmediately after the alu in the program. If the overflow flag is not set when the 8086 executes the INTOinstructions, the instruction will simply functions as an NOP .However if the overflow flag is set indicating anoverflow error, the 8086 will execute a type 4 interrupt after executing the INTO instructions.Software Interrupts:Type 0-255:

The interrupt INT instruction can be used to cause the 8086 to do one of the 256 possible interrupttypes. The interrupt type is specified by the number as a part of the instruction. You can use an INT2 instructionto send execution to an NMI interrupt service routine. This allows you to test the NMI routine without needingto an apply an external signal to the NMI input of the 8086.

With the software interrupts you can call the desired routines from many different programs in a systeme.g. BIOS in IBM PC has in its ROM collection routines, each performing some specific function such asreading character from keyboard writing character to CRT.This collection of routines referred to as Basic inputoutput system or BIOS.

The BIOS routines are called with INT instructions. We will summarize interrupt response and how itis serviced by going through following steps.

1. 8086 pushes the flag register on the stack.

2. It disables the single step and the INTR input by clearing the trap flag and interrupt flag in theflag register.

3. It saves the current CS and IP register contents by pushing the trap flag and interrupt flag inthe flag register.

4. It does an indirect far jump to the start of the routine by loading the new values of CS and IPregister from the memory whose address calculate by 4 to the interrupt type.

5. Once these valu3es are loaded in the CS AND IP 8086 will fetch the instructions from the newaddress which is the starting address of interrupt service routine.

6. An IRET instruction at the end of the interrupt service gets the pervious values of CS and IPby popping the CS and IP from the stack.

7. At the end the flag register contents are copied back into flag register by popping the flagregister from stack.

Mask able Interrupt:The 8086 INTR input can be used to interrupt a execution. The 8086 is provided with a mask able

handshake interrupt. This is interrupt is implemented by using two pins-INTR and INTA. This interrupt can beenabled and disabled by STI (IF=1) or CLI (IF=0), respectively. When the 8086 is reset the interrupt flag isautomatically cleared (if=0).S0o after reset INTR is disabled user has to execute STI instruction to enable INTRinterrupt

7. Writing a simple program of adding two hexadecimal numbers 23H and 84H and saving the result in

a register in assembly language is illustrated below:

Algorithm

1. Load the 1st number 23H in one register.

2. Load the 2nd number 84H in another register.

3. Add the contents of the two registers.

4. Save the result in any register.

5. End the program.

Flow Chart

The above steps can be represented in a pictorial format with the help of flowchart.

PROGRAM:

MVI A, 23H

MVI B, 84H,

ADD B

STA 4500

HLT

8. Write an ALP to add n- 8 bit numbers With algorithm.

MVI D, 00

MVI C, 05

LXI H, 8030

MOV A, M

DCR C

AHEAD INX H

ADD M

JNC LOOP-1

INR D

LOOP-1 DCR C

JNZ AHEAD

STA 8056

MOV A, D

STA 8051

HLT

9. Write an ALP to subtract 2-8 bit numbers with algorithm.

LXI H, 8501

MOV A, M

INX H

SUB M

JNC LOOP-1

INR C

LOOP-1 INX H

MOV M, A

MOV A, C

INX H

MOV M, C

10. Write an ALP to perform division of 1-8 bit number by another 8-bit number: (M/J-2013)

LXI H, 8900H

MOV A, M

INX H

MOV B, M

MVI C, FF

LOOP INR C

SUB B

JNC LOOP

ADD B

STA 8902H

MOV A, C

STA 8903H

HLT



Part -A - Unit II1. What are the modes in which 8086 can operate?

The 8086 can operate in two modes and they are minimum (or uniprocessor) mode and

maximum ( or multiprocessor) mode.

2. What is the data and address size in 8086?

The 8086 can operate on either 8-bit or 16-bit data. The 8086 uses 20 bit address to access

memory and 16-bit address to access 1/0 devices.

3. Explain the function of M/IO in 8086.

The signal M/IO is used to differentiate memory address and I/O address When the processor

is accessing memory locations M / IO is asserted high and when it is accessing 1/0 mapped devices it

is asserted low.

4. Write the flags of 8086. [APR/MAY 2011] CSE]

The 8086 has nine flags and they are

1. Carry Flag (CF) 6. Overflow Flag (OF)

2. Parity Flag (PF) 7. Trace Flag (TF)

3. Auxiliary carry Flag (AF) 8. Interrupt Flag (IF)

4. Zero Flag (ZF) 9. Direction Flag (DF)

5. Sign Flag (SF)

5. What are the addressing modes of 8086? [APR/MAY 2011] MEE]

Immediate addressing mode Direct addressing mode Register addressing mode Register indirect addressing mode Indexed addressing mode Register relative addressing mode Based indexed addressing mode Relative based indexed addressing mode Intra segment direct mode Intra segment indirect mode Inter segment direct mode Inter segment indirect mode

6. Show the bit positions of various flags in 8086?

(a) : CARRY FLAG – SET BY CARRY OUT OF MSB

(b) : PARITY FLAG – SET IF RESULT HAS EVEN PARITY

(c) : AUXILIARY CARRY FLAG FOR BCD

(d) : ZERO FLAG – SET IF RESULT = 0

(e) : SIGN FLAG = MSB OF RESULT

(f) : SINGLE STEP TRAP FLAG

(g) : INTERRUPT ENABLE FLAG

7. What are the types of instructions in instruction set of 8086?

Data copy / Transfer instructions

Arithmetic and Logical instructions

Branch instructions

Machine control instructions

Flag manipulation instructions

String instructions

8. Write the special functions carried by the general purpose registers of 8086.

The special functions carried by the registers of 8086 are the following register Special

functions are

1. AX 16-bit Accumulator

2. AL 8-bit Accumulator

3. BX Base Register

4. CX Count Register & DX .Data Register

9. How clock signal is generated in 8086? What is the maximum internal clock frequency of

8086?

The 8086 does not have on-chip clock generation circuit. Hence the clock generator chip, 8284

is connected to the CLK pin of8086. The clock signal supplied by 8284 is divided by three for internal

use. The maximum internal clock frequency of8086 is 5MHz.

10. What are the interrupts of 8086?

1. Type 0: Divide by zero interrupt

2. Type 1: Single step interrupt

3. Type 2:Non maskable interrupt

4. Type 3: Breakpoint

5. Type 4: Overflow interrupt

6. Software interrupts Type 0-255

11. Define assembler directives? [MAY/JUN 2007]

There are some instructions in the assembly language program which are not a part of processor

instruction set. These are instructions to assembler and are referred as pseudo operations or assembler

directives.

12. What are min and max mode operation of 8086 processor? [APR/MAY 2011 ]

The 8086 microprocessor can be operated in minimum mode by connecting MXMN / pin to

logic 1. In this mode all control signals are given by the microprocessor chip itself. There is only a

single microprocessor in minimum mode system.

In maximum mode, the 8086 is operated by connecting the MXMN / pin to ground. The

processor drives the status signals S1, S2 and S3. Another chip called bus controller drives the control

signals using the status information.

13. What is mean by based indexed addressing?

The based indexed addressing modes are simply combinations of the register indirect addressing

modes. These addressing modes form the offset by adding together a base register (BX or BP) and an

index register (SI or DI). The allowable forms for these addressing modes are

MOV AL, [BX][SI]

MOV AL, [BX][DI]

MOV AL, [BP][SI]

MOV AL, [BP][DI]

14. What happens when trap flag is set in 8086 microprocessor? [NOV/DEC 2010]

Trap flag is used for single stepping through a program. If set, a trap is executed after execution

of each instruction.. i.e interrupt service routine is executed which displays various registers and

memory variable contents on the displays after execution of each instruction. Thus programmer

can easily trace and correct errors in the program.

15. What are the two methods of interfacing general I / O devices?

I / O mapped I / O Memory mapped I / O



Part -B - Unit II1. Explain about 8086 Signals – Maximum and Minimum modes.

Minimum Mode 8086 System•In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping itsMN/MX pin to logic 1.•In this mode, all the control signals are given out by the microprocessor chip itself.There is a single microprocessor in the minimum mode system.•The remaining components in the system are latches, trans receivers, clock generator, memory and I/Odevices. Some type of chip selection logic may be required for selecting memory or I/O devices, dependingupon the address map of the system. •Latches are generally buffered output D-type flip-flops like 74LS373 or8282.They are used for separating the valid address from the multiplexed address/data signals and are controlled

by the ALE signal generated by 8086.•Transreceivers are the bidirectional buffers and some times they arecalled as data amplifiers. They are required to separate the valid data from the time multiplexed address/datasignals.•They are controlled by two signals namely, DEN and DT/R.•The DEN signal indicates the direction of data,i.e. from or to the processor. The system contains memory for the monitor and users programstorage.•Usually, EPROM are used for monitor storage, while RAM for users program storage. A system maycontain I/O devices. •The working of the minimum mode configuration system can be better described in terms of the timingdiagrams rather than qualitatively describing the operations. •The opcode fetch and read cycles are similar.Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle andthe second is the timing diagram for write cycle.•The read cycle begins in T1 with the assertion of addresslatch enable (ALE) signal and also M / IO signal. During the negative going edge of this signal, the validaddress is latched on the local bus.•The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IOsignal indicates a memory or I/O operation.•At T2, the address is removed from the local bus and is sent tothe output. The bus is then tristated. The read (RD) control signal is also activated in T2.•The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the validdata is available on the data bus.•The addressed device will drive the READY line high. When the processor returns the read signal to highlevel, the addressed device will again tristate its bus drivers.•A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal isagain asserted to indicate a memory or I/O operation. In T2, after sendingthe address in T1, the processor sends the data to be written to the addressed location. •The data remains onthe bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhatdelayed in T2 to provide time for floating).•The BHE and A0 signals are used to select the proper byte or bytes of memory or I/Oword to be read or write.•The M/IO, RD and WR signals indicate the type of data transfer.

Maximum mode setting

Maximum Mode 8086 System •In the maximum mode, the 8086 is operated by strapping the MN/MX pin toground.•In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controllerderives the control signal using this status information.•In the maximum mode, there may be more than one microprocessor in the system configuration.•The components in the system are same as in the minimum mode system.•The basic function of the buscontroller chip IC8288, is to derive control signals like RD and WR ( for memory and I/O devices), DEN,DT/R, ALE etc. using the information by the processor on the status lines.•The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 aredriven by CPU.•It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC andAIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems. •AEN and IOB aregenerally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN output dependsupon the status of the IOB pin.•If IOB is grounded, it acts as master cascade enable to control cascade 8259A,else it acts as peripheral data enable used in the multiple bus configurations.•INTA pin used to issue twointerrupt acknowledge pulses to the interrupt controller or to an interrupting device.•IORC, IOWC are I/Oread command and I/O write command signals respectively. These signals enable an IO interface to read orwrite the data from or to the address port.•The MRDC, MWTC are memory read command and memory writecommand signals respectively and may be used as memory read or write signals.•All these command signals instructs the memory to accept or send data from or to the bus.•For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available.•Here the only difference between in timing diagram between minimum mode and maximum mode is thestatus signals used .

2. Define about Multiprocessor – Closely & Loosely Coupled configurations.

3. With neat block diagram 8087 Numeric Data Processor. (A.U.APRIL/MAY-2011) (N/D-2011)(M/J-2013,2012) (N/D-2010)

4. What is 8089 I/O Processor? Explain with its architecture.

5. Write notes about Advanced Processors.80186

80286

80386

6. Write ALP for to find largest and smallest no in array.

LARGEST NUMBER

SMALLEST NUMBER

7. Explain the interrupts and interrupt service routine? (M/J-2012) (A/M-2008)

Divide by zero interrupt (Type 0):

When the quotient from either a DIV or IDIV is too large to fit in the result register,8086 will

automatically execute type 0 interrupt.

Single step interrupt (Type 1):

The type 1 interrupt is the single step trap. In the single step mode, system will execute one

instruction and wait for the further direction from user. Then user can examine the contents of register

and memory locations and if they are correct user can tell the system to execute the next instructions.

This is feature is useful for debugging assembly language program.

An 8086 system is used in the single step mode by setting the trap flag. If the trap flag is set,

the 8086 will automatically execute a type 1 interrupt after execution of each instruction. But the 8086

has no such instruction to directly set or reset the trap flag. These operations can be performed by

tasking the flag register contents into memory, changing the memory contents so to set or reset trap

flag and save the memory contents into flag.

Non Mask able interrupt (Type 2):

As the name suggests, this interrupt cannot be disabled by any software instructions. Thos

interrupt is activated by low to high transition on 8086 NMI input pin. In response 8086 will do a type

2 interrupt.

Breakpoint Interrupt ((Type 3):

The type 3 interrupt is used to implement break point function in the system. The type 3

interrupt is produced by execution of the INT 3 instruction. Breakpoint function is often used as

debugging aid in cases where single stepping provides more detail than wanted. When you insert a

breakpoint the system executes the instructions up to the breakpoint and then goes to the breakpoint

procedure. In the breakpoint procedures you can write a program to display register contents, memory

contents and other information that is required to debug your program. You can insert as many

breakpoints as you want in your program.

Overflow Interrupt:

The type 4 interrupt is used as to check overflow condition after any signed arithmetic

operation in the system. The 80867 overflow flag OF, will be represented in the destination register

or memory location.

For example if you add the 8-bit signed number 0111 1000 (+120 decimal) and the 8 bit signed

number 0110 1010 (+106 decimal) result is 1110 0010 (-98 decimal).In signed numbers, MSB is

reserved for sign and other bits represent magnitude of the numbe3r.In the previous example after

addition of two 8 bit signed numbers result is negative since it is too large to fit in 7 bits. To detect

this condition in the program, you can put interrupt on overflow instructions, INTO immediately after

the alu in the program. If the overflow flag is not set when the 8086 executes the INTO instructions,

the instruction will simply functions as an NOP .However if the overflow flag is set indicating an

overflow error, the 8086 will execute a type 4 interrupt after executing the INTO instructions.

Software Interrupts:

Type 0-255:

The interrupt INT instruction can be used to cause the 8086 to do one of the 256 possible

interrupt types. The interrupt type is specified by the number as a part of the instruction. You can use

an INT2 instruction to send execution to an NMI interrupt service routine. This allows you to test the

NMI routine without needing to an apply an external signal to the NMI input of the 8086.

With the software interrupts you can call the desired routines from many different programs in

a system e.g. BIOS in IBM PC has in its ROM collection routines, each performing some specific

function such as reading character from keyboard writing character to CRT.This collection of routines

referred to as Basic input output system or BIOS.

The BIOS routines are called with INT instructions. We will summarize interrupt response and

how it is serviced by going through following steps.

8. 8086 pushes the flag register on the stack.

9. It disables the single step and the INTR input by clearing the trap flag and interrupt flag

in the flag register.

10. It saves the current CS and IP register contents by pushing the trap flag and interrupt

flag in the flag register.

11. It does an indirect far jump to the start of the routine by loading the new values of CS

and IP register from the memory whose address calculate by 4 to the interrupt type.

12. Once these valu3es are loaded in the CS AND IP 8086 will fetch the instructions from

the new address which is the starting address of interrupt service routine.

13. An IRET instruction at the end of the interrupt service gets the pervious values of CS

and IP by popping the CS and IP from the stack.

14. At the end the flag register contents are copied back into flag register by popping the

flag register from stack.

Mask able Interrupt:

The 8086 INTR input can be used to interrupt a executiuon.The 8086 is provided with a mask

able handshake interrupt. This is interrupt is implemented by using two pins-INTR and INTA.This

interrupt can be enabled and disabled by STI (IF=1) or CLI (IF=0), respectively. When the 8086 is

reset the interrupt flag is automatically cleared (if=0).S0o after reset INTR is disabled user has to

execute STI instruction to enable INTR interrupt.

8. Write an assembly language program in 8086 to find the sum of numbers in the array.

.model small

.data

ARRAY DB 12H,24H,26H,63H,25H,86H,2FH,33H,10H,35H

SUM DW 0

.code

START: MOV AX,@data ; [ Initialise

MOV DS,AX ; data segment ]

MOV CL,10 ; Initialise counter

XOR DI,DI ; Initialise pointer

LEA BX,ARRAY ; Initialise array base pointer

BACK: MOV AL,[BX+DI] ; Get the number

MOV AH,00H ; Make higher byte 00h

ADD SUM,AX ; SUM = SUM + number

INC DI ; Increment pointer

DEC CL ; Decrement counter

JNZ BACK ; if not 0 go to back

MOV AH,4CH

INT 21H

END START

9. Write an assembly language program in 8086 to search a numbers in the array.

.model small

.stack 100

.data

ARRAY DB 63H,32H,45H,75H,12H,42H,09H,14H,56H,38H ; Array of ten numbers

SER_NO DB 09H ; Number to be searched

SER_POS DB ? ; Position of the searched number

.code

START: MOV AX,@data ; [ Initialises

MOV DS,AX ; data segment ]

MOV ES,AX

MOV CX,000AH ; Initialise counter

LEA DI,ARRAY ; Initialise base pointer for array

MOV AL,SER_NO ; Get the number to be searched in AL

CLD ; Clear direction flag

REPNE SCAS ARRAY ; Repeat until match occurs or CX = 0

MOV AL,10 ; [ Find the searched number position in the array

SUB AL,CL ; if SER_POS is 0 number is not in array; otherwise

MOV SER_POS,AL ; SER_POS gives the position of number in the array ]

END START

10. Write an assembly language program in 8086 to search a numbers in the array.

.model small

.stack 100

.data

ARRAY DB 63H,32H,45H,75H,12H,42H,09H,14H,56H,38H ; Array of ten numbers

MAX DB 0 ; Maximum number

.code

START: MOV AX,@data ; Initialises

MOV DS, AX ; data segment ]

XOR DI,DI ; Initialise pointer

MOV CL,10 ; Initialise counter

LEA BX,ARRAY ; Initialise base pointer for array

MOV AL,MAX ; Get maximum number

BACK: CMP AL,[BX+DI] ; Compare number with maximum

JNC SKIP

MOV DL,[BX+DI] ; If number > MAX

MOV AL,DL ; MAX = number ]

SKIP: INC DI ; Increment pointer

DEC CL ; Decrement counter

JNZ BACK ; IF count = 0 stop; otherwise go BACK

MOV MAX,AL ; Store maximum number

END START



Part -A - Unit III1. What is meant by key bouncing? (A.U.APRIL/MAY-2008)

Microprocessor must wait until the key reach to a steady state; this is known as Key bounce.

2. Write the function of crossbar switch?

The crossbar switch provides the inter connection paths between the memory module and the

processor. Each node of the crossbar represents a bus switch. All these nodes may be controlled by

one of these processors or by a separate one altogether.

3. What is a data amplifier?

Transceivers are the bi-directional buffers are sometimes they are called as data amplifiers.

They are required to separate the valid data from the time multiplexed address data signal. They are

controlled by 2 signals i.e DEN & DT/R.

4. What are the different inter connection topologies?

Shared bus

Multiport Memory

Linked Input/output

Bus window

Crossbar Switching.

5. What are the configurations used for physical interconnections?

Star Configuration

Loop configuration

Complete interconnection

Regular topologies

Irregular topologies

6. Give the instruction set of 8087?

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Comparison Instructions.

4. Transcendental Operations.

5. Constant Operations.

6. Coprocessor Control Operations.

7. Write the advantages of loosely coupled system over tightly coupled systems? (M/J-2012)

1. More number of CPUs can be added in a loosely coupled system to improve the system

performance

2. The system structure is modular and hence easy to maintain and troubleshoot.

3. A fault in a single module does not lead to a complete system breakdown.

8. What is the different clock frequencies used in 80286?

Various versions of 80286 are available that run on 12.5MHz, 10MHz and 8MHz clock

frequencies.

9. Define swapping in?

The portion of a program is required for execution by the CPU, it is fetched from the secondary

memory and placed in the physical memory. This is called ‘swapping in’ of the program.

10. What are the different operating modes used in 8086? (A.U.MAY/JUNE-2007)

The 80286 works in two operating modes

1. Real addressing mode

2. Protected virtual address mode.

11. What are the CPU contents used in 80286?

The 80286 CPU contains almost the same set of registers, as in 8086

Eight 16-bit general purpose register

Four 16-bit segment registers

Status and control register

Instruction pointer.

12. What is status flag bit?

The flag register reflects the results of logical and arithmetic instructions. The flag register

digits D0, D2, D4, D6, D7 and D11 are modified according to the result of the execution of logical

and arithmetic instruction. These are called as status flag bits.

13 What is a control flag?

The bits D8 and D9 namely, trap flag (TF) and interrupt flag (IF) bits, are used for controlling

machine operation and thus they are called control flags.

14. What is instruction pipelining?

Major function of the bus unit is to fetch instruction bytes from the memory. In fact, the

instructions are fetched in advance and stored in a queue to enable faster execution of the instructions.

This concept is known as instruction pipelining.

15. What are the status register in 8087?



Part -B - Unit III

1. Explain the closely coupled multiprocessor configurations. (A/M-2008)

2. Explain the loosely coupled multiprocessor configurations.(N/D-2006) (A/M-2008)

3. Explain briefly about salient features of 8087 coprocessor units with architecture.

(A.U.APRIL/MAY-2011) (N/D-2011) (M/J-2013,2012) (N/D-2010)

4. What are the different data types supported by 8087?

5. Explain the architecture of 8089 I/O processor. (A/M-2011,2010) (M/J-2012)

6. Explain the architecture of 8089.(M/J-2013)

7. Discuss the communication between IOP 8089 and CPU 8086.

8. Explain the architecture of 8087 math coprocessor.

9. Describe the signals of 8087.

10. Explain briefly about coprocessor configuration.



Part -A - Unit IV1. What is the use of 8251 chip?

Intel’s 8251A is a universal synchronous asynchronous receiver and transmitter compatible withIntel’s Processors. This may be programmed to operate in any of the serial communication modes builtinto it. This chip converts the parallel data into a serial stream of bits suitable for serial transmission.It is also able to receive a serial stream of bits and converts it into parallel data bytes to be read by amicroprocessor.2. What are the different types of methods used for data transmission?

The data transmission between two points involves unidirectional or bi-directional transmission ofmeaningful digital data through a medium. There are basically there modes of data transmission

(a) Simplex(b) Duplex(c) Half DuplexIn simplex mode, data is transmitted only in one direction over a single communication

channel.For example, a computer (CPU) may transmit data for a CRT display unit in this mode. Induplex mode, data may be transferred between two transreceivers in both directions simultaneously.

In half duplex mode, on the other hand, data transmission may take pace in either direction,but at a time data may be transmitted only in one direction. For example, a computer may communicatewith a terminal in this mode. When the terminal sends data (i.e. terminal is sender). The message isreceived by the computer (i.e the computer is receiver). However, it is not possible to transmit datafrom the computer to terminal and from terminal to the computer simultaneously.3. What are the various programmed data transfer methods?

ii) Synchronous data transferiii) Asynchronous data transferiv) Interrupt driven data transfer

4. What is synchronous data transfer?It is a data method which is used when the I/O device and the microprocessor match in speed. To

transfer a data to or from the device, the user program issues a suitable instruction addressing thedevice. The data transfer is completed at the end of the execution of this instruction.5. What is asynchronous data transfer?

It is a data transfer method which is used when the speed of an I/O device does not match with thespeed of the microprocessor. Asynchronous data transfer is also called as Handshaking.6. What are the functional types used in control words of 8251a?

The control words of 8251A are divided into two functional types.1. Mode Instruction control word2. Command Instruction control wordMode Instruction control word :-This defines the general operational characteristics of 8251A.Command Instruction control word:-The command instruction controls the actual operations

of the selected format like enable transmit/receive, error reset and modem control.7. What are the basic modes of operation of 8255?

There are two basic modes of operation of 8255, viz.1. I/O mode.2. BSR mode.

In I/O mode, the 8255 ports work as programmable I/O ports, whileIn BSR mode only port C (PC0-PC7) can be used to set or reset its individual port bits. Under the IOmode of operation, further there are three modes of operation of 8255, So as to support different typesof applications, viz. mode 0, mode 1 and mode 2.

Mode 0 - Basic I/O modeMode 1 - Strobed I/O modeMode 2 - Strobed bi-directional I/O

8. Write the features of mode 0 in 8255?1. Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and lower) areavailable. The two 4-bit ports can be combined used as a third 8-bit port.2. Any port can be used as an input or output port.3. Output ports are latched. Input ports are not latched.4. A maximum of four ports are available so that overall 16 I/O configurations are possible.

9. What are the features used mode 1 in 8255?Two groups – group A and group B are available for strobed data transfer.

1. Each group contains one 8-bit data I/O port and one 4-bit control/data port.2. The 8-bit data port can be either used as input or output port. The inputs and outputs bothare latched.3. Out of 8-bit port C, PC0-PC2 is used to generate control signals for port B and PC3=PC5are used to generate control signals for port A. The lines PC6, PC7 may be used as independentdata lines.

10. What are the signals used in input control signal & output control signal?Input control signalSTB (Strobe input)IBF (Input buffer full)INTR(Interrupt request)Output control signalOBF (Output buffer full)ACK (Acknowledge input)INTR(Interrupt request)

11. What are the features used mode 2 in 8255?The single 8-bit port in-group A is available.

1. The 8-bit port is bi-directional and additionally a 5-bit control port is available.2. Three I/O lines are available at port C, viz PC2-PC0.3. Inputs and outputs are both latched.4. The 5-bit control port C (PC3=PC7) is used for generating/accepting handshake signals forthe 8-bit data transfer on port A.

12. What are the modes of operations used in 8253? (A.U.NOV/DEC-2006)Each of the three counters of 8253 can be operated in one of the following six modes of operation.

1. Mode 0 (Interrupt on terminal count)2. Mode 1 (Programmable monoshot)3. Mode 2 (Rate generator)4. Mode 3 (Square wave generator)5. Mode 4 (Software triggered strobe)6. Mode 5 (Hardware triggered strobe)

13. What are the different types of write operations used in 8253?There are two types of write operations in 8253

(1) Writing a control word register(2) Writing a count value into a count register

The control word register accepts data from the data buffer and initializesthe counters, as required. The control word register contents are used for

(a) Initializing the operating modes (mode 0-mode4)(b) Selection of counters (counter 0- counter 2)(c) Choosing binary /BCD counters (d) Loading of the counter registers.The mode control register is a write only register and the CPU cannot read its contents.

14. Give the different types of command words used in 8259a?The command words of 8259A are classified in two groups

1. Initialization command words (ICWs)2. Operation command words (OCWs)

15. Give the operating modes of 8259a?(a) Fully Nested Mode(b) End of Interrupt (EOI)(c) Automatic Rotation(d) Automatic EOI Mode(e) Specific Rotation(f) Special Mask Mode(g) Edge and level Triggered Mode(h) Reading 8259 Status(i) Poll command(j) Special Fully Nested Mode(k) Buffered mode(l) Cascade mode



Part -B - Unit IV1. Draw 8051 Architecture and explain its pin description.

2. Explain about 8051 I/O Ports.

3. Define 8051 Addressing Modes with examplesThe eight addressing modes are: Immediate Register Direct Indirect Relative Absolute Long Indexed

Immediate AddressingIf the operand is a constant then it can be stored in memory immediately after the opcode. Remember,values in code memory (ROM) do not change once the system has been programmed and is in use in theeveryday world. Therefore, immediate addressing is only of use when the data to be read is a constant.For example, if your program needed to perform some calculations based on the number of weeks in theyear, you could use immediate addressing to load the number 52 (34H) into a register and then performarithmetic operations upon this data.MOV R0, #34The above instruction is an example of immediate addressing. It moves the data 34H into R0. Theassembler must be able to tell the difference between an address and a piece of data. The has symbol (#)is used for this purpose (whenever the assembler sees # before a number it knows this is immediateaddressing).This is a two-byte instruction.

Register AddressingOften we need to move data from a register into the accumulator so that we can perform arithmeticoperations upon it. For example, we may wish to move the contents of R5 into the accumulator.MOV A, R5This is an example of register addressing. It moves data from R5 (in the currently selected register bank)into the accumulator.ADD A, R6

The above is another example of register addressing. It adds the contents of R6 to the accumulator, storingthe result in the accumulator. Note that in both examples the destination comes first. This is true of allinstructions.

Direct AddressingDirect addressing is used for accessing data in the on-chip RAM. Since there are 256 bytes of RAM (128bytes general storage for the programmer and another 128 bytes for the SFRs). That means the addressesgo from 00H to FFH, any of which can be stored in an 8-bit location.MOV A, 67The above instruction moves the data in location 67H into the accumulator. Note the difference betweenthis and immediate addressing. Immediate addressing uses the data, which is immediately after theinstruction. With direct addressing, the operand is an address. The data to be operated upon is stored inthat address. The assembler realises this is an address and not data because there is no hash symbol beforeit.

ADD A, 06

The above instruction adds the contents of location 06H to the accumulator and stores the result in theaccumulator. If the selected register bank is bank 0 then this instruction is the same as ADD A, R6.

Indirect AddressingRegister addressing and direct addressing both restrict the programmer to manipulation of data in fixedaddresses. The address the instruction reads from (MOV A, 30H) or writes to (MOV 30H, A) cannot bealtered while the program is running.There are times when it is necessary to read and write to a number of contiguous memory locations. Forexample, if you had an array of 8-bit numbers stored in memory, starting at address 30H, you may wish toexamine the contents of each number in the array (perhaps to find the smallest number). To do so, youwould need to read location 30H, then 31H, then 32H and so on.This can be achieved using indirect addressing. R0 and R1 may be used as pointer registers. We can useeither one to store the current memory location and then use the indirect addressing instruction shownbelow.MOV A, @RiwhereRi is either R0 or R1.Now, we can read the contents of location 30H through indirect addressing:MOV R0, #30HMOV A, @R0

The first instruction is an example of immediate addressing whereby the data 30H is placed in R0. Thesecond instruction is indirect addressing. It moves the contents of location 30H into the accumulator.

If we now wish to get the data in location 31H we use the following:INC R0MOV A, @R0Once we see how to write a loop in assembly language, we will be able to read the entire contents of thearray.Relative AddressingRelative addressing is used only with certain jump instructions. The system executes a jump by changingthe contents of the PC to the address of the next instruction to be executed. For example, if we wished tojump to the instruction stored at location 4EH in code memory, the PC would be loaded with 4EH. Then,during the next execution cycle the contents of the PC (4EH) are placed on the address bus and theinstruction at 4EH is retrieved.A relative address (or offset) is an 8-bit signed value, which is added to the PC to form the address of thenext instruction to be executed.With 8-bit signed numbers, the MSB is used to determine whether the number is positive or negative. Ifthe MSB is 0 then the number is positive, while if the MSB is 1 the number is negative.The instruction below shows how to jump six locations ahead.SJMP 06HSJUMP is an unconditional jump and is a 2-byte instruction. The number following it is an offset address.If this instruction were stored in code memory at locations 100H and 101H, as shown below:100H80H101H06HThe opcode for SJMP is 80H. The operand is the offset address. If this instruction were

executed the PC would get the value 108H. This is what happens: The PC contains 100H, therefore the instruction 80H is read into the IR. The instruction is decoded as the 2-byte SJMP instruction. The PC is incremented so that the operand may be retrieved. The operand is read from code memory and the PC is incremented again (because this is a 2-byeinstruction).

The operand (06H) is added to the PC (102H + 06H = 108H). The next instruction (at 108H) is executed.Once we deal with 2's compliment and how negative numbers are dealt with in the CPU, we will look at abackward jump.The S in SJMP stands for short. The range of signed 8-bit numbers is -127 to 128. (Click here to see howsigned numbers are stored in a microcontroller.) Therefore, using SJMP allows us to jump 127 locationsforward or 128 locations backward. Hence the name short jump.When writing assembly programs we do not need to calculate the offset when using SJMP. Instead, weuse labels. If we wished to jump to the instruction at 108H we would simply label the instruction with anappropriate name, for example THERE. We would then write the assembly code SJMP THERE. Theassembler does the work of replacing the label with the correct offset.

Absolute AddressingAbsolute addressing is only used with the ACALL and AJMP instructions.ACALL - subroutine call (2 byte instruction)AJMP - unconditional jump (2 byte instruction)These instructions allow you to move to any instruction within the same 2K of memory.We will look at the AJMP instruction only (at a later date, when we begin dealing with subroutines we willdeal with the ACALL instruction).

The operation of the AJMP instruction is detailed below:AJMP address(PC) <- (PC) + 2(PC10-PC0) <- address10 - address0

Note that only the eleven least significant bits of the PC are altered. The five most significant bits remainthe same. This means the AJMP will only allow you to jump to a location in the same 2K page as theinstruction directly after the jump.

For example:

If the label THERE represents an instruction at address 0F46H and the instruction AJMP THERE is in memory atlocations 0900H and 0901H, the assembler will encode the instruction as11100001 1st byte (A10 - A8 + opcode)010001102nd byte (A7 - A0)The underlined bits are the low-order 11 bits of the destination address, 0F46H = 0000111101000110B.The upper five bits in the program counter will not change when this instruction executes. Note that boththe AJMP instruction and the destination are within the 2K page bounded by 0800H and 0FFFH, andtherefore have the upper five address bits in common.

Note: it is not important to remember the different kinds of addressing modes and which instructionsbelong to which mode. It is far more important to understand how to get data from one place to anotherand how to perform operations upon the data. You will never be asked to memorise a processor'sinstruction set. This will always be provided. However, as we shall see when we start writing programs, itis important to be able to use the instruction set.Most of our early programs will deal with moving data into and out of the accumulator, performingarithmetic operations and jumping to different parts of the program.

4.Explain about 8051 Instruction Set with examples.1. ACALL: Absolute Call2. ADD, ADDC: Add Accumulator (With Carry)3. AJMP: Absolute Jump4. ANL: Bitwise AND5. CJNE: Compare and Jump if Not Equal6. CLR: Clear Register7. CPL: Complement Register8. DA: Decimal Adjust9. DEC: Decrement Register10. DIV: Divide Accumulator by B11. DJNZ: Decrement Register and Jump if Not Zero12. INC: Increment Register13. JB: Jump if Bit Set14. JBC: Jump if Bit Set and Clear Bit15. JC: Jump if Carry Set16. JMP: Jump to Address17. JNB: Jump if Bit Not Set18. JNC: Jump if Carry Not Set19. JNZ: Jump if Accumulator Not Zero20. JZ: Jump if Accumulator Zero21. LCALL: Long Call22. LJMP: Long Jump23. MOV: Move Memory24. MOVC: Move Code Memory25. MOVX: Move Extended Memory26. MUL: Multiply Accumulator by B27. NOP: No Operation28. ORL: Bitwise OR29. POP: Pop Value From Stack30. PUSH: Push Value Onto Stack31. RET: Return From Subroutine32. RETI: Return From Interrupt33. RL: Rotate Accumulator Left34. RLC: Rotate Accumulator Left Through Carry35. RR: Rotate Accumulator Right36. RRC: Rotate Accumulator Right Through Carry37. SETB: Set Bit38. SJMP: Short Jump39. SUBB: Subtract From Accumulator With Borrow40. SWAP: Swap Accumulator Nibbles41. XCH: Exchange Bytes42. XCHD: Exchange Digits43. XRL: Bitwise Exclusive OR44. Undefined: Undefined Instruction

5. Define Memory Organization of 8051.

8051 Memory Organisation

Internal ROMThe 8051 has 4K (4096 locations) of on-chip ROM. This is used for storing the system program. 212 = 4096,therefore the internal ROM address bus is 12 bits wide and internal ROM locations go from 000H to FFFH.

Internal RAM

There are 256 bytes of internal RAM on the 8051. 28 = 256, therefore the internal RAM address bus is 8 bitswide and internal RAM locations go from 00H to FFH.

The first 128 locations (00H to 7FH) of internal RAM are used by the programmer for storing data while thesecond 128 locations (80H to FFH) are the Special Function Registers (SFRs) which we will deal with later.

The diagram below is a summary of the 8051 on-chip RAM.

Register BanksThere are four register banks from 00H to 1FH. On power-up, registers R0 to R7 are located at 00H to 07H.However, this can be changed so that the register set points to any of the other three banks (if you change toBank 2, for example, R0 to R7 is now located at 10H to 17H).

Bit-addressable LocationsThe 8051 contains 210 bit-addressable locations of which 128 are at locations 20H to 2FH while the rest arein the SFRs. Each of the 128 bits from 20H to 2FH have a unique number (address) attached to them, asshown in the table above. The 8051 instruction set allows you to set or reset any single bit in this section ofRAM.With the general purpose RAM from 30H to 7FH and the register banks from 00H to 1FH, you may only reador write a full byte (8 bits) at these locations.However, with bit-addressable RAM (20H to 2FH) you can read or write any single bit in this region by usingthe unique address for that bit. We will later see that this is a very powerful feature.

6. Explain about Special function registers.

7. Differentiate between Memory Mapped I/O and I/O Mapped I/O.

(A.U. NOV/DEC-2003)

8. Draw the Block diagram and explain the operations of 8251serialcommunication interface.(A.U.MAY/JUNE-2007)

9. Draw the Block diagram and explain the operations of 8255 parallel communicationinterface. (A.U.APRIL/MAY 2003,2004,2005) (A.U.NOV/DEC-2010)

10. Draw the Block diagram of 8279 and explain the functions of each block.(A.U.MAY/JUNE-2003),(A.U.NOV/DEC-2007,2008) (M/J-2013)



Part -A - Unit V1. What is mean by microcontroller?

A device which contains the microprocessor with integrated peripherals like memory, serial

ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC,DAC is

called microcontroller.

2. Explain the function of the pins PSEN of 8051.

PSEN: PSEN stands for program store enable. In 8051 based system in which an external ROM

holds the program code, this pin is connected to the OE pin of the ROM.

3. Explain the function of the pins EA of 8051.

EA: EA stands for external access. When the EA pin is connected to Vcc, program fetched to addresses

0000H through 0FFFH are directed to the internal ROM and program fetches to addresses 1000H

through FFFFH are directed to external ROM/EPROM. When the EA pin is grounded, all addresses

fetched by program are directed to the external ROM/EPROM.

4. Explain the DPTR of 8051.(A.U.MAY/JUNE-2007)

DPTR:

DPTR stands for data pointer. DPTR consists of a high byte (DPH) and a low byte (DPL). Its

function is to hold a 16-bit address. It may be manipulated as a 16-bit data register or as two

independent 8-bit registers. It serves as a base register in indirect jumps, lookup table instructions and

external data transfer.

5. Explain the 16-bit register SP of 8051.

SP:

SP stands for stack pointer. SP is a 8- bit wide register. It is incremented before data is stored

during PUSH and CALL instructions. The stack array can reside anywhere in on-chip RAM. The stack

pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H.

6. Name the special functions registers available in 8051.(A.U.MAY/JUNE-2009)

Accumulator

B Register

Program Status Word.

Stack Pointer.

Data Pointer.

Port 0

Port 1

Port 2

Port 3

Interrupt priority control register.

Interrupt enable control register.

7. List the features of 8051 microcontroller?

The features are

Single supply +5 volt operation using HMOS technology.

4096 bytes program memory on chip(not on 8031)

128 data memory on chip.

Four register banks.

Two multiple mode,16-bit timer/counter.

Extensive Boolean processing capabilities.

64 KB external RAM size

32 bidirectional individually addressable I/O lines.

8 bit CPU optimized for control applications.

8. What are SFRs? .(A.U.MAY/JUNE-2009)

The SFRs(Special Function Register) are internal registers of microcontroller dedicated for

specific functions. These registers can be used only for their specified/ defined functions and cannot

be used for an other functions. In microcontrollers the SFRs are mapped as internal data memory and

can be accessed by direct addressing.

9. What are the register banks of 8051?(A.U.MAY/JUNE-2007)

The register banks are internal RAM locations of 8051 which can be used as general purpose

registers or scratch pad registers. The first 32 bytes of internal RAM of 8051 are organized as register

banks with each bank consisting of 8 locations. At any one time the processor can work with only one

register bank depending on the value of bits RS0 and RS1 in the PSW register.

10. How stack is implemented in 8051?

The 8051 supports LIFO (Last in First Out) stack and the stack can reside anywhere in the

internal RAM. The 8051 has 8-bit stack pointer to indicate the top of stack. The stack can be accessed

using PUSH and POP instructions. During PUSH the SP is automatically incremented by one and

during POP the SP is automatically decremented by one.

11. Compare Microprocessor and Microcontroller. (N/D-06) (A/M-08,10) (N/D-11)

S.No Microprocessor Microcontroller

1

Microprocessor contains

ALU,general purpose

registers,stack pointer, program

Microcontroller contains the circuitry of

microprocessor and in addition it has

built- in ROM, RAM, I/O devices, timers

and counters.

12. State the function of RS1 and RS0 bits in the flag register of intel 8051 microcontroller?

(A.U.APRIL/MAY-2004) (M/J-2013)

RS1, RS0 – Register bank select bits

RS1 RS0 Bank Selection

0

0

1

1

0

1

0

1

Bank 0

Bank 1

Bank 2

Bank 3

13. Give the alternate functions for the port pins of port3?

RD WR T1 T0 INT1 INT0 TXD RXD

RD – Read data control output.

WR – Write data control output.

T1 – Timer / Counter1 external input or test pin.

T0 – Timer / Counter0 external input or test pin.

INT1- Interrupt 1 input pin.

INT 0 – Interrupt 0 input pin.

TXD – Transmit data pin for serial port in UART mode.

RXD - Receive data pin for serial port in UART mode.

14. What are the operating modes of the timer of 8051?

The operating modes of the timers of 8051 are mode-0, mode-1, mode-2 and mode-3. In mode-

counter, clock timing circuit and

interrupt circuit.

2It has many instructions to move

data between memory and CPU.

It has one or two instructions to move data

between memory and CPU.

3It has one or two bit handling

instructions.

It has many bit handling instructions.

4Access times for memory and I/O

devices are more.

Less access times for built-in memory and

I/O devices.

5

Microprocessor based system

requires more hardware.

Microcontroller based system requires

less hardware reducing PCB size and

increasing the reliability.

0 the timers will function as 13-bit timers and in mode-1 the timers will function as 16-bit timers will

function as 16- bit timers. In mode-2 the timers will function as 8-bit timers with auto reload feature.

The timer-0 alone can work in mode-3 and in this mode the TL0 will function as 8-bit timer controller

by standard timer-0 control bits and TH0 will function as 8-bit timer controlled by the timer-1 control

bits.

15. Explain the register IE format of 8051.

EA - ET2 ES ET1 EX1 ET0 EX0

EA- Enable all control bit.

ET2- Timer 2 interrupt enable bit.

ES – Enable serial port control bit.

ET1 – Enable Timer1 control bit.

EX1- Enable external interrupt1 control bit.

ET0 – Enable Timer0 control bit.

EX0- Enable external interrupt0 control bit.



Part -B - Unit V

1. With neat sketch explain the architecture of 8051 Microcontroller.(or)(A.U.MAY/JUNE-2007,2008,2010,2011)

Draw the pin configuration of 8051 and explain the function of each pin in detail.(A.U.NOV/DEC-2006) (M/J-12) (M/J-2013)

FIG 2.1a : BLOCK DIAGRAM OF 8051

FIG 2.1b : 8051 PROGRAMMING MODEL

2. Briefly explain the Input / Output Pins OF 8051 Microcontroller

3. Write short notes on external memory of 8051 Microcontroller.

4. Explain the Timer / Counter in 8051Microcontroller. (A.U.APRIL/MAY-2003,2005)(N/D-08)

5. Briefly explain the different modes of operation by serial port in 8051Microcontroller?(A.U.NOV/DEC-2004),(APRIL/MAY-2005) (M.J-2013)

6. With neat sketch explain the Interrupt structure of 8051Microcontroller.(A.U.NOV/DEC-2006)

OVERVIEW OF INTERRUPT STRUCTURE

7. Explain briefly about keyboard interfacing. (M/J-12) (M/J-2013)

Code received from the input port.

8. Explain briefly about interfacing with ADC.

9. Explain briefly about interfacing with DAC (A/M-11)(M/J-2013)

10.Explain briefly about LCD interfacing. (M/J-12) (M/J-2013)

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