Efficient Implementation of N by N Bit Integer Division

GODAVARI INSTITUTE OF ENGINEERING AND TECHNOLOGY

PPT ON Efficient VLSI Implementation of N/N Integer Division

PRESENTED BY: Z.VAMSI KRISHNA ECE III/IV B.VAMSI KRISHNA ECE III/IV

CONTENTS

INTRODUCTION

OVERVIEW

MAGNITUDE BOUNDS ON QUOTIENT & RESIDUAL

PROPOSED DIVIDER

OPTIMAL PARTITIONS

CONCLUSIONS

INTRODUCTIONMost works in division are directed towards 2N/N bit floating point divisionThese iterative algorithms are implemented sequentially and many optimization techniques can be used to reduce the number of division cycles requiredBut VLSI DSP implementations make use of N/N bit divisions that are realized combinationallyTherefore optimization techniques for sequential implementations of division are not applicableIn this paper we present an efficient combinational implementation of the non-restoring division algorithm for N/N divisions by exploiting the magnitude of the divisor

Overview

Let X be an N bit dividend and D be the N bit divisor

Dividing X by D produces a N bit quotient Q with N bit remainder R

X=QD+R

If the dividend has a width of 2N-bit and the quotient has a width of N-bit, and is referred to as the 2N/N bit division

But in such divisions there is a possibility for quotient to overflow

Here in our N/N bit division there is no case for overflow

In a general radix-r shift-subtract division algorithm, the quotient is comprised of radix-r digits where and each quotient digit is selected based on the shift-and-subtract recurrence relation

where p is the residual and j is the recurrence stepHere the division begins with a residual of

And a quotient digit is selected at each recurrence of (2) until all the quotient digits are obtained

The type of shift-subtract division algorithm determines the quotient digit selection process

Radix-2 non- restoring division algorithm

The quotient and the remainder are obtained as:-

Q=quotient q=quotient digit R=remainderN/b=recurrences P=residual

Magnitude bounds on quotient and residual

Now considering non-restoring division algorithm using a non-redundant quotient digit-set, the magnitudes of the quotient and the residual are bounded by the magnitude of the divisor as

Let if zero has non redundant digit set and 1(z) be the leading non-zero bit position of Z, where the least significant bit is the 0-th bit, then the fallowing property is true

Then the quotient and divisor uses the above property and we get

Property 1 states that the minimum number of leading zeros in the quotient that is determined directly from the magnitude of the divisor

In a sequential divider, where the quotient digits are computed sequentially, this property is implicitly exploited when the divisor and dividend are normalized

This reduces the number of sequential cycles needed to complete the division

Property 2 states that the maximum number of non-zero bits in the residuals can be determined directly from the magnitude of the divisor

PROPOSED DIVIDERBy using property 1 it enables us to skip the number of subtractions

But in some cases when the divisor has the smallest magnitude, no subtractions can be skipped

By using property 2 it enable us to reduce the size (word length) of the subtractions

But in some cases when the divisor has the largest magnitude, no size reduction can be made

Here simplifying effects of the two properties are complementary with respect to the magnitude of the divisor

So overall savings can be achieved if both properties are exploited

Let us suppose that we can configure the circuit to skip the first three unnecessary trial subtractions, as allowed by Property 1

Then we can avoid the adder propagation delay in the first three stages realize a savings of 25% in adder-cell delay

suppose that l(D) < 3 and circuit to perform subtractions of at most 3-bit wide, as allowed by Property 2

we can avoid the carry propagation of adder cells beyond bit 2 in the stages again realizing a savings of 25% in adder-cell delay

In effect, we have partitioned the divider array at bit 3 into two configurations

the divider operates using one of the two configurations, depending on the magnitude of the divisor

Therefore this example has achieved an overall savings of 25% in adder cell delay

OPTIMAL PARTITIONS In the above example we have partitioned once so we have an adder

delay savings of 25%

we can expect additional savings as we introduce more partitions to the array

We will perform the delay analysis in the context of carry ripple subtractions by counting the number of adder cells in the critical paths

CONCLUSIONS

We have presented an efficient implementation of an N/N combinational divider using the non-restoring shift-subtract algorithm

By exploiting the relationship between the magnitude bounds of the divisor, the dividend, and the residual

Practically delay reduction of 25%-35% can easily be achieved

THANK YOU

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