Efficient Identification of Hot Data for Flash Memory Storage Systems ACM Transaction on storage, Feb. 2006 JenWei Hsieh (National Taiwan Univers ity), LiPin Chang (National Chiao-Tung Univ ersity), and TeiWei Kuo (National Taiwan Unive rsity) Speaker: Soyoon Lee
14
Embed
Efficient Identification of Hot Data for Flash Memory Storage ...
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Efficient Identification of Hot Data for Flash Memory Storage Systems
- garbage collection- performance of the flash memory access- longer lifetime ( wear leveling)
A Multihash-Function Framework- use independent multiple hash functions- reduce the chances of false identification of hot data- on-line- provide excellent performance- reduce the hash table space
Highly Efficient Method On-line Hot Data Identification!
• Freeze a counter once it reaches the maximum positive values
• Right-shift all counters for 1 bit whenever any counter is overflowed
• Exponential decaying
• When? : per decay period
• How? : the values of all counters divided by two Right-shift all counters
Count Overflow Decaying of count
The hot data identification of an LBA
Hot data identifier
FTLx
Logical Block Address x
f1(x)
f2(x)
f3(x)
f4(x)
K-dimensionalHashing Table
Hash Functions
H Most Significant Bits
block write ( LBA , size ) from File
System
Hot data H MSB of every counter of hashed values contain a
nonzero bit value
X is not hot data
Experimental setup• A Multihash-Function Framework setup
- The number of hash functions: 2 (the division method, the multiplication method)- Each counter for a hash table entry: 4 bits - hash table size: 1~8 KB
• Flash memory size: 512MB
• Traces of data access: the Hard disk of a mobile PC (a 20GB hard disk, 384MB RAM, Intel Pentium-III 800MHz)
• Comparison method- direct address method*M.L Chiang, C.H. Paul, and R.C. Chang, “Manage flash memory in personal communicate devices,” Procee
dings of International Symposium on Consumer Electronics,1997.
- two-level LRU*CHANG,L.P. AND KUO, T. W. “An adaptive striping architecture for flash memory storage systems of embed
ded systems. In Proceedings of the 8th IEEE Real-Time and Embedded Technology and Applications Symposium, 2002.
The locality in data access
• Direct address method• No false hot data identification• Decay period: 5117 writes• hot data threshold on the number of writes to an LBA: 4
Performance EvaluationHash table size vs False Identification
1 KB: basic
1 KB: enhanced
2 KB : basic
2KB enhanced,4KB basic,
8 KB enhanced
• basic: multi-hash function framework• enhanced: the framework with an enhanced counter update policy
512 flash memory, 2KB hash table 0.871% !!
Performance Evaluation
Decay period (setup: 5117 writes)
6396 writes
Performance Evaluation
Runtime Overheads
CPU Cycles per Operation (Unit: CPU Cycles)
The runtime overheads on the maintenance of the hash table (i.e., the decay process) is also limited
(e.g.,3,565 CPU cycles per 5,117 writes over 512MB flash memory).
Two – level LRU
Two-level LRU: hot data 512, candidate data 1024 nodes