Efficient Embedding of Deterministic Test Data Mudassar Majeed 1, Daniel Ahlström 1, Urban Ingelsson 1, Gunnar Carlsson 2 and Erik Larsson 1 1 Department.

Efficient Embedding of Deterministic Test Data

Mudassar Majeed1, Daniel Ahlström1, Urban Ingelsson1,

Gunnar Carlsson2 and Erik Larsson1

1Department of Computer and Information Science, Linköping

University, Sweden

2Ericsson AB BU Networks SE-164 80 Stockholm

Sweden

2

Purpose Printed Circuit Boards (PCBs) include an increasing number of

integrated circuits (ICs), often of the same type

Example:

Ericsson telecommunication systems contain PCBs with 36 ICs where 4 ICs are of type A, 8 ICs of type B, 8 ICs of type C and 16 ICs of type D

In-field testing is needed due to harsh environment

For in-field test, the problem is to deliver test data to the system

Straight forward solution is to store test data in the system

Drawbacks:

High memory requirements

Inflexibility in applying different tests

The proposed solution uses an embedded test controller to manipulate test data by exploiting structural information of the system

Benefits: Reduces memory requirements and provides flexibility

Efficient Embedding of Deterministic Test Data

3

Outline Introduction

Proposed Solution

Experiments and Results

Conclusions

MARKERINGSYTA FÖR BILDER

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4

Need for Remote System Test

System at Remote Location

Flexibility in applying commands Embedded test solution

Test Engineer at Office

Comm

and 1

:

Test A

ll Com

ponents

Comm

and 2

:

Test O

nly C

omponen

t A

Introduction

5

Embedded Test Solution

Command 1:

Test All Components

Command 2:

Test Only Component A

Embedded

Test

Solution

PCB

Components

A B B

Test

Data

Test

Resp.

Introduction

6

IEEE 1149.1 Standard

ICs connected serially (IEEE 1149.1)

B BA

IEEE 1149.1 Standard for PCB testing Supports testing core logic Instructions INTEST, BYPASS

Introduction

7

IC Under Test Using IEEE 1149.1 Standard

IEEE 1149.1

1.IR-scan: Set instruction

2.DR-scan: Apply (execute)

IR-scan defines the length of the 1149.1 chain

Introduction

A

BYPASS A

Bypass component A

1 bit

A

INTEST A

Test component A

4 bits

Stimuli:

Instruction:

INTESTBYPASS

8

System Under Test Using IEEE 1149.1 Std.

B BA

Command 1:

Test All Components

Command 2:

Test Only Component A

INTEST A INTEST B INTEST B

B BA

INTEST A BYPASS B BYPASS B

Introduction

Test Vectors

9

Naive Embedded Test Controller

Embedded Test Solution

CPU

Memory

Command 1:

Test All Components

(INTEST A INTEST B INTEST B)

Command 2:

Test Only Component A

(INTEST A BYPASS B BYPASS B)

High memory requirements and inflexibility in applying the tests

Introduction

10

Outline Introduction

Proposed Solution

Experiments and Results

Conclusions

MARKERINGSYTA FÖR BILDER

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11

Key Idea

Embedded Test Solution

Concatenator

Memory

Command 1: Test All Components INTEST A INTEST B INTEST B

Command 2:Test Only Component A INTEST A BYPASS B BYPASS B

StructuralInformation

Provides flexibility in applying the tests

Type A

Type B

Command

Command 1:1 2

3

Proposed Solution

Command 2:

12

1. Memory Requirements

MemoryMemory

Reduces memory requirements

Naive approach Proposed concatenation approach

Comparison

Proposed Solution

13

2. Structural Information

B BA

Structural Information

- Types of components

- Order of components in the system

- Instruction Register Length

- Data Register Length

- Instructions

Proposed Solution

14

3. Concatenator

B BA

Steps for a given command:

1. Read structural information

2. Read component specific test stimuli

3. Concatenate the stimuli

4. Scan in instruction vector (if required)

5. Scan in and apply test vector

6. Scan out test response

7. Compare with expected response

8. If exit condition met, then terminate

9. Else repeat step 2

Proposed Solution

15

Outline Introduction

Proposed Solution

Experiments and Results

Conclusions

MARKERINGSYTA FÖR BILDER

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16

Objectives

To show that the approach works:

We used a PC as test controller and an FPGA as system under test

To see how memory requirements are reduced:

Naive Approach vs Proposed Concatenation Approach (for test command: “test all components”)

We created systems using industrial circuits as ICs

Experiments and Results

% Reduction in

Memory Requirements=

17

Industrial Circuits

CircuitLength of Test Patterns (bits)

Number of Test Patterns

Test Data Volume (MBs)

ckt-1 11256 3768 5.51ckt-2 22216 2636 6.98ckt-3 9628 4927 5.65ckt-4 43414 1528 7.91ckt-5 26970 4899 15.75ckt-6 80000 2859 27.27ckt-7 20000 18027 42.98ckt-8 110000 18142 237.9

Z. Wang and K. Chakrabarty. Test data compression for IP embedded cores using selective encoding of scan slices. In Proc. International Test Conference (ITC), pp. 581--590, 2005.

Experiments and Results

18

Industrial Circuits

Experiments and Results

# of Multiplications

2

3

20

ckt-1 ckt-2 ckt-3 ckt-4 ckt-5 ckt-6 ckt-7 ckt-8

Design

2

3

20

2

3

20

1

2

8

Set

19

Results

Experiments and Results

Number of Multiplications

Per

cent

age

Red

uctio

n in

Mem

ory

Req

uire

men

ts

Average

Set 1 (ckt-1)

Set 2 (ckt-2)

Set 3 (ckt-3)

Set 4 (ckt-4)Set 5 (ckt-5)

Set 6 (ckt-6)

Set 7 (ckt-7)

Set 8 (ckt-8)

Set 7 (ckt-7)

Set 8 (ckt-8, 237.6 MBs)

Average

Set 1 (ckt-1)

5.51

6.98

5.65

7.91

15.75

27.27

42.98

237.9

MBs

20

Conclusions Printed Circuit Boards (PCBs) include an increasing number of

integrated circuits (ICs), often of the same type

Systems fail in operation and require in-field testing

Test data volume requires huge memory

The proposed solution exploits,

Structural Information of the system

The fact that multiple components of the same type require same test data

The test data manipulation via an embedded test controller

The reduction in memory requirements depends upon the number of components of the same type

Example:

Ericsson telecommunication systems contain PCBs with 36 ICs where 4 ICs are of type A, 8 ICs of type B, 8 ICs of type C and 16 ICs of type D

Efficient Embedding of Deterministic Test Data

Mudassar Majeed1, Daniel Ahlström1, Urban Ingelsson1,

Gunnar Carlsson2 and Erik Larsson1

1Department of Computer and Information Science, Linköping

University, Sweden

2Ericsson AB BU Networks SE-164 80 Stockholm

Sweden