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Microelectronics Reliability 53 (2013) 2043–2051
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability
journal homepage: www.elsevier .com/locate /microrel
Effect of solder pads on the fatigue life of FBGA memory modules
underharmonic excitation by using a global–local modeling
technique
0026-2714/$ - see front matter � 2013 Elsevier Ltd. All rights
reserved.http://dx.doi.org/10.1016/j.microrel.2013.06.018
⇑ Corresponding author. Address: PREM, Department of Mechanical
Engineering,Hanyang University, 17, Haengdang-dong, Seondong-gu,
Seoul 133-791, Republic ofKorea. Tel.: +82 2 2220 0431; fax: +82 2
2292 3406.
E-mail address: [email protected] (G. Jang).
Yusuf Cinar a, Jinwoo Jang a, Gunhee Jang a,⇑, Seonsik Kim b,
Jaeseok Jang ba Department of Mechanical Engineering, Hanyang
University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791,
Republic of Koreab Memory Division, Samsung Electronics Co. Ltd.,
San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701,
Republic of Korea
a r t i c l e i n f o a b s t r a c t
Article history:Received 19 June 2012Received in revised form 29
May 2013Accepted 15 June 2013Available online 22 July 2013
This paper investigates the effect of solder pad size on the
fatigue life of fine-pitch ball grid array (FBGA)solder joints in
memory modules due to harmonic excitation by using a global–local
modeling technique.Finite element analysis of a memory module
requires enormous computer memory and computationaltime because
some components such as solder balls are very small relative to the
overall size of the mem-ory module. The global–local modeling
technique has been suggested as an alternative approach
withreasonable accuracy. A finite element model of the memory
module with simplified solder joints wasdeveloped as a global
model, and the natural frequencies and modes were calculated and
verified byexperimental modal testing. Displacement variations were
calculated from the global model due to vibra-tion excitation using
the mode superposition method. A finite element model of a part of
the memorymodule, which is composed of a package, PCB, and detailed
solder joints, was developed as a local model.Calculated
displacements from the global model were then substituted along the
boundary of the localmodel in order to detect vulnerable parts of
solder joints under vibration. Utilizing the global–local mod-eling
technique, the interface between the solder ball and pad near the
PCB was found to be the most vul-nerable part, and the effect of
solder pad size on the fatigue life of the memory module was
determinedby using the Basquin equation and Miner’s rule. It was
experimentally verified that the solder pad size insolder joints
affects fatigue life as well as the reliability of solder joints
under harmonic excitation.
� 2013 Elsevier Ltd. All rights reserved.
1. Introduction
As electronic devices become smaller, faster and thinner,
inte-grated circuit (IC) packages with high input/outputs (I/Os)
becomedenser. Fine-pitch ball grid array (FBGA) which is a
surface-mounted IC package is ideal for packaging devices with
highdensities and I/Os and small sizes and weights. FBGAs are
widelydeployed in space-conscious applications,
microprocessors/micro-controllers, dynamic random access memories
(DRAMs), and con-sumer electronics. DRAMs account for about one
fifth of theworldwide semiconductor market [1]. DRAM memory
modulesused in personal computers, workstations, and servers are
com-posed of a number of packages mounted on a printed circuit
board(PCB). Packages, which are integrated circuits of DRAM,
aremounted on PCBs through solder joints as shown in Fig. 1.
Solderjoints are further used to provide the electrical signals
betweenpackage chips and the PCB. Memory modules are exposed to
vibra-tion over various frequency ranges [2], which may cause
productsto malfunction. The US Air Force states that the failures
of
electronic equipment in operating environments are due
tohandling, vibration, shock and thermal cycling, and 20% of the
fail-ures are related to vibration and shock [2]. The reliability
and per-formance of memory modules are standardized by the
JointElectron Devices Engineering Council (JEDEC). The
performanceand fatigue life of memory modules mostly depend on the
solderjoints, and high reliability and performance of solder joints
undervibration is demanded by customers and the electronics
manufac-turing industry.
Once vibration was identified to be one of the dominant
failuremechanisms for electronic components, the electronic
packagingindustry took interest in understanding this failure
mechanismand increasing reliability of solder joints under
vibration. Cheet al. [3] used the global–local modeling technique
to investigatethree cases including plastic ball grid array (PBGA)
assembly sub-jected to thermal cycling, flip chip on board assembly
subjectedto vibration and very thin profile quad flat non leaded
assemblysubjected to bending. Zhu et al. [4] also studied the
solder jointreliability in a printed wiring board assembly under
bending byusing the global–local modeling technique. Wu [5]
utilized the glo-bal–local modeling concept to calculate the von
Mises stress in sol-der joints of interest under random vibration
loading and thenpredicted the fatigue life of solder joints using a
damage modelcalled the Basquin power-law relation. Che and Pang [6]
studied
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Fig. 1. Section view of a solder joint.
2044 Y. Cinar et al. / Microelectronics Reliability 53 (2013)
2043–2051
flip chip solder joints under an out-of-plane sinusoidal
vibrationload with constant and varying amplitudes, and they used
Miner’scumulative damage law to estimate the fatigue life of flip
chip sol-der joints. Using Miner’s rule and Basquin relation, Grieu
et al. [7]assessed the random vibration durability of packages
including,Ceramic Interposer Grid Array, Plastic Leaded Chip
Carrier andFBGA components. Yoon et al. [8] evaluated Pb-free
solders for var-ious packages including FBGA in terms of mechanical
solder jointreliability. Solder joint reliability was tested at 5 G
(10–500 Hz)and 10 G (501–1500 Hz) for vibration during 60 min. and
all 30samples with FBGA showed no failure. Yu et al. [9] showed
thatreducing the pad size was found to increase the thermal fatigue
lifeof FBGA. Mercado et al. [10] also found that the solder pad
size af-fects solder joint reliability in flip chip PBGA packages
under ther-mal cycling tests. Liguore et al. [11] studied design
variables thataffect the reliability of solder joints for surface
mount technology(SMT) subjected to vibration. They found that
vibration fatigue ofSMT solder joints is highly dependent on chip
carrier type, size,and the position of the chip mounted on the PCB
and solder joint.Yang et al. [12] also investigated the vibration
reliability character-ization of a PBGA assembly. They found that
mounting PBGA mod-ules on a PCB increased the stiffness of the PCB.
Qi et al. [13] carriedout experiments to improve the reliability of
PBGA packages undervarious manufacturing and multiple environmental
loading condi-tions. They performed board-level temperature
cycling, vibration,and combined temperature cycling and vibration
testing to quan-tify the reliability. They showed that underfilling
is the mostimportant factor to improve solder joint reliability
under vibration.Yang and Chen [14] studied the fatigue
characteristics of a PBGAassembly under random vibration. Their
results showed that largerchips improve the fatigue life of PBGA
integration systems, and sol-der balls with tin–lead are more
reliable in high cycle fatigue situ-ations. Xueli et al. [15]
studied the effect of solder joint parameterson vibration fatigue
reliability. Their simulation results showedthat solder joints with
larger diameter and smaller height have im-proved reliability.
Cinar et al. [16] also investigated failure mecha-nisms of FBGA
solder joints of memory modules under harmonicexcitation. They
showed that failure occurs due to the relative dis-placement
between the PCB and package, and the most vulnerablepart of the
memory module under vibration was found to be thesolder joint near
the PCB. However, the reliability of FBGA solderjoints under
vibration has not been thoroughly investigated; priorresearch did
not investigate the effect of solder pad size on solderjoint
reliability under high vibration level either by simulation
orexperimental method. Solder pad size has not been studied as
asingle design variable under vibration to improve the
reliabilityof FBGA solder joints.
This paper investigates the effect of solder pad size on the
fati-gue life of FBGA solder joints of a memory module with
double-
sided packages due to harmonic excitation using a
global–localmodeling technique. A finite element model of the
memory mod-ule presented by the global–local model was developed,
and calcu-lated displacements from the global model were
substituted alongthe boundary of the local model in order to detect
vulnerable partsof solder joints under vibration. The effect of
solder pad size on thefatigue life of the memory module was
investigated using the Bas-quin equation and Miner’s rule. Fatigue
life of the memory mod-ules with different pad size is estimated by
using solder materialfatigue constants in the literature. It was
experimentally verifiedthat reliability and fatigue life of memory
module was affectedby solder pad size on PCB side.
2. Analysis model
Fig. 2 shows the double-data-rate three synchronous
dynamicrandom access memory (DDR3 SDRAM) type memory module usedin
this study. It is composed primarily of a PCB, packages,
packageregisters, and Sn–3.0Ag–0.5Cu (SAC305) solder joints. The
PCB iscomposed of ten layers of copper conductor and FR-4, and
thepackages and package registers are composed of many
integratedcircuits, whereas solder joints are composed of a solder
ball andsolder pads. This memory module has 36 packages and 2
packageregisters. Table 1 shows the mechanical dimensions of the
PCB,package, and package register shown in Fig. 2. Two types of
solderballs are used in the packages and the package register. The
BGAsof the package and package register have different patterns,
asshown in Fig. 3. The red square in the package and package
registerin Fig. 3 indicates their orientations in the memory module
inFig. 2. Dimension of solder joints in Fig. 1 for analysis model
is pre-sented as design 1 shown in Table 2. The diameter and height
ofthe solder balls are represented by x2 and y2, respectively. The
sol-der joints are composed of two types of solder pads placed on
thepackage and PCB sides as shown in Fig. 1. The diameter and
heightof the solder pad on the package side are represented by x4
and y3,whereas those of the solder pad on the PCB side are
represented byx1 and y1, respectively. The diameter of solder ball
on the packageside is presented as x3.
3. Finite element analysis by a global–local modeling
technique
3.1. Global model analysis
Finite element analysis of a memory module requires
enormouscomputer memory and computational time because some
compo-nents such as solder balls are very small relative to the
overall sizeof the memory module. The global–local modeling
technique hasbeen suggested as an alternative approach with
reasonable accu-racy. In this study, the submodeling technique was
used as a glo-bal–local modeling technique [17]. The cut boundary
is theboundary of the local model (submodel), which represents a
cutthrough the global model (coarse model). Displacements
calcu-lated on the cut boundary of the global model are specified
asboundary conditions for the local model. The accuracy of the
sub-modeling technique depends on the cut boundaries, which
shouldbe far from the stress concentration region.
A finite element model of the memory module with
simplifiedsolder joints was developed as a global model, as shown
in Fig. 4.Table 3 shows the material type and properties of each
component.The PCB, packages, package registers, and solder balls
are modeledby the linear brick elements with eight nodes, and each
node hasthree degrees of freedom. In this global model, a solder
ball is mod-eled as an octagonal structure with 16 elements. The
total numberof elements was 289,916. In the finite element model,
PCB, pack-ages, and solder balls were connected by node sharing.
DDR type
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Fig. 2. A DDR3 SDRAM type memory module: (a) front view, (b)
back view, and (c) side view.
Table 1Dimensions of bare PCB and packages of a memory
module.
Components Number ofcomponents (EA)
Dimensions in mm (L �W � H)
Bare PCB 1 133.35 � 30.00 � 1.295Package 36 11.00 � 7.50 �
0.77Package register 2 13.50 � 8.00 � 0.779
Table 2Major design variables of solder joints for design 1 and
2.
Variable Design 1 (mm) Design 2 (mm) Difference (%)
x1 0.330 0.350 6.1x2 0.5046 0.5090 0.87x3 0.420 0.420 –x4 0.520
0.520 –y1 0.045 0.045 –y2 0.3369 0.3352 �0.51y3 0.015 0.015 –
Y. Cinar et al. / Microelectronics Reliability 53 (2013)
2043–2051 2045
memory modules are usually inserted in a slot in a motherboard
sothat the finite element model has a fixed boundary condition
oftwo short sides and one long side and a free boundary
condition
Fig. 3. BGA patterns of a package and package register: (a)
package and (b) packageregister.
of one long side by assuming that the boundary condition of
thememory module in the slot is totally fixed. The natural
frequenciesand mode shapes were calculated using ANSYS.
Experimental modal testing was performed to verify the pro-posed
simulated results. Fig. 5 shows the experimental setup forthe modal
testing. An impact hammer was used to excite a mem-ory module. The
responses on the memory module were measuredat 18 points using a
laser Doppler vibrometer (sensor) and PULSE3560C (signal analyzer).
The mode shapes were determined usingthe STAR modal system. Table 4
shows the comparison betweenthe undamped simulated and experimental
natural frequenciesof the memory module. Fig. 6 shows the
comparison betweenthe simulated and experimental mode shapes of
vibration modes1, 2, and 3 of the memory module.
Modal damping ratios of a memory module were calculatedfrom a
plot of its frequency response function using the bandwith(half
power) method for its three modes [18]. The modal dampingratios are
listed in Table 4. These were inputted into the finite ele-ment
model of the memory module.
Fig. 7 shows the finite element model for the forced
vibrationanalysis. Two short sides and one long side of the finite
elementmodel were rigidly coupled with a nodal mass. The
dynamic
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Fig. 4. Finite element model of a memory module: (a) front view,
(b) back view, and (c) side view.
Table 3Material properties of each component of a memory
module.
Component Material type Density (kg m�3) Young’s modulus (MPa)
Poisson’s ratio [�] Element type Element number
Bare PCB FR4 2,200.5 23,000 0.40 Brick 151,060Package – 1,920.5
12,000 0.40 Brick 77,184Package register – 2,389.1 12,000 0.40
Brick 13,928Solder ball SAC305 7,094.0 44,113 0.36 Brick 47,744
Fig. 5. Experimental setup for modal testing.
Table 4Simulated, measured natural frequencies and damping
ratios of the memory module.
Mode number Simulation Experiment Error (%) Damping ratio (%)f
(Hz) f (Hz)
Mode 1 926.65 943 1.764 2.160Mode 2 1364.5 1290 �5.460 2.805Mode
3 2087.7 2000 �4.201 1.484
2046 Y. Cinar et al. / Microelectronics Reliability 53 (2013)
2043–2051
response of a memory module subjected to harmonic excitationwas
investigated using mode superposition. JEDEC requires a
loga-rithmic swept sine test to evaluate the qualification of
electroniccomponents in electrical equipment. The harmonic
excitationforce, p(t) in Eq. (1) was applied in the out-of-plane
direction (Zdirection) to the nodal mass in order to simulate the
base excita-tion with an integration time step of 2.5 � 10�5
seconds [19].
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Fig. 6. Comparison of simulated and experimental results of
three modes (a) mode1, (b) mode 2, and (c) mode 3.
Fig. 7. Finite element model of a mem
Y. Cinar et al. / Microelectronics Reliability 53 (2013)
2043–2051 2047
pðtÞ ¼ p_ðtÞ 60xs
S lnð2Þ ð23:3219St=60 � 1Þ þ b
� �ð1Þ
where p_¼ Mna0g, and Mn, a0, and g are the nodal mass,
applied
acceleration corresponding to JEDEC service condition 1 (20
G),and gravitational acceleration, respectively. xs is the starting
fre-quency, S is the sweep rate in decades per minute (defined as
onedecade/minute in JEDEC service condition 1), and b
representsphase. Forced vibration analysis was performed around the
firstnatural frequency because prior research [16] showed that the
firstmode is the most destructive mode up to 2 kHz.
3.2. Local model analysis
First, the cut boundary for the local model needs to be
verifiedto be sure that it is far enough from the stress
concentration regionbecause the accuracy of the submodeling
technique depends onthe cut boundaries. A finite element model of a
part of the memorymodule, which is composed of a package, PCB, and
detail solderjoints, was developed as a local model with a verified
cut boundarysize as shown in Fig. 8. The local model has the same
element typeas the global model, with 233,168 total elements. Table
5 comparesthe number of elements for global and local models.
Pre-test results also showed that the packages near the
fixedboundary of the memory module in Fig. 7 are the most failed
pack-ages due to the relative displacement as explained in
reference[16]; therefore, the local model was analyzed for one of
these pack-ages (P13), and its symmetric package (P31) shown in
Fig. 2 bysubstituting displacement variation along its cut boundary
in orderto detect vulnerable parts of solder joints under
vibration. Fig. 9shows the von Mises stress distribution for the
P13-N6 solder joint.As shown, the maximum stress is concentrated at
the interface be-tween the solder ball and pad near the PCB.
4. Effect of solder pads on the fatigue life of solder joints
andexperimental verification
4.1. Fatigue life estimation of a memory module with different
pad size
Relative displacement between PCB and package under vibra-tion
is the main source of deformation which causes stress to in-crease
[16]. Since stress due to relative deformation wasconcentrated at
the interface between the solder ball and pad nearthe PCB as shown
in Fig. 9, solder pads on the PCB side were se-lected to
investigate their effect on the fatigue life of FBGA solderjoints
in order to increase the stiffness of solder joints at the
inter-face with the PCB. The solder pad diameter (x1) on the PCB
side isincreased approximately by 6.1%, while the rest of the
design vari-ables are assumed to be constant. However, the diameter
(x2) andheight (y2) of the solder ball change slightly by 0.87% and
�0.51%,respectively, for the proper solder joint production. Table
2 showsmajor design variables of the solder joint for design 1 and
2 whosestructures are shown in Fig. 1.
The model with solder joints of design 2 was analyzed
bysubstituting displacement variation from the global model
along
ory module for harmonic analysis.
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Fig. 8. Finite element model of a local model.
Table 5Comparison of the number of elements for global and local
models.
Component Element number (EA)
Global model Local model
Bare PCB 151,060 41,856Package 77,184 46,544Solder ball 47,744
104,832Solder pad – 39,936
2048 Y. Cinar et al. / Microelectronics Reliability 53 (2013)
2043–2051
its cut boundary. Fig. 10 compares the variation in
volume-aver-aged von Mises stress concentrated on the interface
between thesolder joint and PCB in the frequency range of 880–973
Hz, whichis 5% around mode 1 of 926.65 Hz. The difference in the
von Misesstress between the design 1 (34.57 MPa) and design 2
(33.81 MPa)for the P13 package is around 2.2%.
The fatigue life of memory modules with different pad sizes
canbe estimated by the stress-based approach for high cycle
fatigue,called the Basquin equation, as follows:
ra ¼ r0f ð2Nf Þb ð2Þ
where ra is the stress amplitude, r0f is the fatigue strength
coeffi-cient, b is the fatigue strength exponent, and 2Nf is the
reversalsto failure (one reversal = ½ cycle). The material
constants r0f and bcan be found from the literature [2,20–23]. The
material constantsused to calculate the fatigue life of memory
modules are summa-
Fig. 9. von Mises stress distribution for a P13-N6 solder joint:
(a) s
rized in Table 6. The fatigue life can be calculated using Eq.
(2) fordifferent stress amplitudes ranging from 880 Hz to 973 Hz
aroundmode 1. Damage for variable stress levels can then be
superposedby the linear damage rule known as Miner’s rule [24].
Dtotal ¼Xki¼1
niNi
ð3Þ
where k is the total number of various stress magnitudes
applied, niis the actual number of cycles under a specific stress
amplitude, andNi is the total number of cycles to failure under a
specific stressamplitude. Miner’s rule states that failure occurs
when the totaldamage Dtotal is equal to 1. The number of cycles to
failure was cal-culated for different material constants from the
literature usingEqs. (2) and (3). Table 7 shows simulated number of
cycles to failurefor different material constants. Our goal in this
research is not toobtain a material constant, but to estimate the
percentage differ-ence for fatigue life between memory modules with
different padsizes, which vary from 9.6% to 24.9% as shown in Table
7. Note thatthe frequency range of 880 Hz and 973 Hz around mode 1
is onlyconsidered in the estimation of the fatigue cycle for
memorymodels.
4.2. Experimental observation of fatigue life
The fatigue life of solder joints in the memory module must
beobserved experimentally to verify the simulation result. The
fati-gue life of the solder joints can be observed by monitoring
the
ection view of the solder joint, (b) solder ball and solder
pads.
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Fig. 10. Comparison of the variation in volume-averaged von
Mises stressconcentrated on the solder joint/PCB interface around
mode 1 as a function offrequency.
Table 6Material constants for fatigue life estimation.
Reference No. [1] [19] [20] [21] [22]
Set 1 Set 2Material type Sn/Pb Sn/Pb Sn/Pb Sn/Pb SAC305
SAC405
r0f (MPa) 109.6 66.3 177.15 75.1 64.8 152.2b �0.1 �0.12 �0.2427
�0.12 �0.1443 �0.2079
Table 7Simulated number of cycles to failure for different
material constants (cycle).
Reference No. [1] [19] [20] [21] [22]
Set 1 Set 2Material type Sn/Pb Sn/Pb Sn/Pb Sn/Pb SAC305
SAC405
Design 1 239,268.2 475.4 1,129.4 1,343.1 145.3 1,853.1Design 2
298,879.7 572.2 1,237.8 1,616.6 169.6 2,062.4Difference (%) 24.9
20.4 9.6 20.4 16.7 11.3
Fig. 11. Experimental setup used to monitor the fatigue life of
memory modules.
Fig. 12. Variation in the acceleration input of JEDEC service
condition 1.
Y. Cinar et al. / Microelectronics Reliability 53 (2013)
2043–2051 2049
resistance increase of the memory module with a daisy
chainassembly because cracks increase resistance. There are 36
pack-ages and 2 package registers on each memory PCB as shown
inFig. 2. All the packages on top and bottom were assembled in
daisychain and then the daisy chained packages on the top and
bottomwere connected in series. The total resistance of the memory
mod-ule daisy chain was measured to be around 35–40 Ohm. A failure
ofthe solder joint is assumed to occur when the total resistance
isgreater than 100 Ohm [16,25].
The experimental setup shown in Fig. 11 was used to determinethe
fatigue life of the memory modules. An EDS50-150 type
elec-tro-dynamic shaker was used to excite the memory module
fixedon a jig. The variation in the input acceleration profile was
mea-sured with an accelerometer on top of the shaker, and was
con-trolled by VibrationVIEW software, as shown on the right side
ofFig. 11. A potential of 2.5 V was supplied from a power supply
tothe memory module with the daisy chain assembly. Variations
inacceleration on top of the shaker, current, and voltage were
mea-sured simultaneously in real time, and acceleration and
resistance(voltage/current) were then obtained using an
oscilloscope. Threesides of the memory module were fixed to the jig
mounted onthe top of a shaker (shown in Fig. 11) to maintain the
same bound-ary conditions as in the simulation of the forced
vibration analysis.
The memory modules in this study were excited by the
JEDECservice condition [26]. Fig. 12 shows the variation of input
forcein terms of acceleration. The harmonic excitation was applied
tothe memory module for a constant peak displacement (1.5 mm)from
20 Hz to 80 Hz (cross-over frequency). A constant accelera-tion
level was then applied between 80 Hz and 2000 Hz. A com-plete sweep
of the test frequency range (from 20 Hz to 2000 Hzand back to 20
Hz) was repeated in a logarithmic manner everyfour minutes. The
sweep rate was one decade/minute. Harmonicexcitation was applied in
the out-of-plane direction (Z direction).
Numbers of test modules are six for modules with design 1
andeight for modules with design 2. It is found that only one of
sixmodules with design 1 had crack on solder ball near package
sidewhile two of eight modules with design 2 had crack on solder
ballnear package side. There is not enough data to investigate
thecause of the crack occurrence on solder ball near package
side,but inappropriate manufacturing process is suspected to be a
causeof the crack. Table 8 shows experimental times to failure for
thesolder joints of design 1 and 2 in five different memory
moduleswhose failure locations were at the interface between solder
jointand PCB. Experimental results show that the fatigue life of
thememory module with solder joints of design 2 increases
rapidly,and the reliability of the memory module is greatly
affected bythe solder pad size on the PCB side, which increases the
fatigue lifeof the five memory modules with solder joints of design
2 by anaverage of about 32.7%. The discrepancy between
simulation
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Table 8Experimental times to failure for five memory modules
(min).
Sample No. 1 2 3 4 5 Average Number of cycles to failure (cycle)
Difference (%)
Design 1 94 91 94 114 97 98 118,320.3 32.7Design 2 129 133 143
123 122 130.0 156,955.5
Fig. 13. Major failure location for design 1: (a) N6 solder
joint of package 13 and (b)A6 solder joint of package 1.
Fig. 14. Major failure location for design 2: (a) A6 solder
joint of package 28 and (b)A1 solder joint of package 10.
2050 Y. Cinar et al. / Microelectronics Reliability 53 (2013)
2043–2051
results in Table 7 and experimental ones in Table 8 was mainly
af-fected by two factors. First, the forced vibration response in
the 5%frequency range around mode 1 (the most destructive mode)
isonly considered in the calculation of fatigue life while mode 1,
2,and 3 of memory modules are excited in the frequency range
be-tween 20 and 2000 Hz in the experiment. Second, the material
typeand properties used in this research are different from ones
foundin references [2,20–22] and set 2 of reference [23], so that
thematerial constants found in the literature [2,20–23] are not
thesame as those of SAC305 solder joints of FBGA memory
modules.Therefore, failure mechanism in the above literatures could
be dif-ferent from the one occurred in this research. However the
com-parison in Table 8 shows that fatigue life of memory
moduleunder vibration increases with the increase of solder pad
size onPCB side.
5. Failure analysis
Failure analysis was performed to detect the failure site in
sol-der joints. The electrical resistance of each daisy chained
packagewas measured using a multimeter. Electrical open circuit or
veryhigh resistance was measured from failed packages. Of the
22packages near the fixed boundary of the memory module, morethan
half failed after the experiments were performed. None ofthe
packages near the free edge of the memory modules failed.We
concluded that the position of the package on the PCB
undervibration is important, which is consistent with other
research[11,14]. It was determined experimentally that packages
mountedvertically on a PCB are more prone to failure than those
mounted
horizontally. This is probably because of two reasons. The
firstone is that distance from the edge of PCB to the edge of
packageis different as shown in Fig. 2. The distance for packages
mountedvertically is 5.95 mm while the distance for those mounted
hori-zontally is 6.70 mm. Therefore, packages mounted vertically
arecloser to the fixed boundary than those mounted
horizontally,which increases the relative displacement between the
PCB andpackage [16]. The second reason is that there are 13 solder
ballsin horizontally-mounted packages near the fixed
boundary,whereas there are only 6 solder balls in
vertically-mounted pack-ages near the fixed boundary, so the stress
of the solder balls inthe horizontally-mounted packages is
distributed over a greaternumber of balls, and therefore each ball
experiences less stresson average than those in the
vertically-mounted packages.
Destructive failure analysis was carried out by
cross-sectioningfor several failed packages. Fig. 13 shows the
cross-section of typ-ical failed solder joints for the memory
modules with solder jointsof design 1. The crack was generally
observed to initiate at theinterface between the solder joint and
PCB, and propagatedthrough the PCB. Fig. 14 shows cross-sections of
typical solderjoints for the memory modules with solder joints of
design 2. Thereare two types of failure locations. As shown in Fig.
14a, one is quitesimilar to the one shown in Fig. 13, and the other
is on the solderball just below the solder pad on the package side
shown inFig. 14b. It is found that only one of six modules with
design 1had crack on solder ball near package side while two of
eight
-
Y. Cinar et al. / Microelectronics Reliability 53 (2013)
2043–2051 2051
modules with design 2 had crack on solder ball near package
side.There is not enough data to investigate the cause of the
crackoccurrence on solder ball near package side, but
inappropriatemanufacturing process is suspected to be the cause of
the crackoccurrence on solder ball near package side.
6. Conclusion
This paper investigated the effect of solder pad size on
FBGAsolder joints of memory modules due to harmonic excitation
byusing a global–local modeling technique. A finite element modelof
the memory module was developed as a global model, and thenatural
frequencies and modes were calculated and verified byexperimental
modal testing, and forced vibration analysis was per-formed to
determine the displacement variation around the firstnatural
frequency under harmonic excitation. Calculated displace-ments from
the global model were substituted along the boundaryof the
developed local model in order to detect vulnerable parts ofsolder
joints under vibration. The interface between the solder balland
pad near the PCB was found to be the most vulnerable part ofthe
memory module under vibration, so an increase in the diame-ter of
the solder pad on the PCB side was investigated for FBGA sol-der
joints in memory modules in order to increase the stiffness
ofsolder joints at the interface with the PCB.
Fatigue life was also calculated with material constants fromthe
literature for memory modules with different pad sizes.
Thepercentage difference in fatigue life for memory modules with
dif-ferent pad sizes varied from 9.6% to 24.9%. The solder joint
param-eters of design 2 were applied for the five different
memorymodules with a daisy chain assembly to experimentally
determinethe fatigue life of the solder joints. It was
experimentally verifiedthat the size of the solder pad in solder
joints affects the fatigue lifeas well as the reliability of solder
joints under harmonic excitation.The average fatigue life of the
design 2 was increased by about32.7%. Two types of failure location
were observed from destruc-tive failure analysis. The first was
crack initiation at the interfacebetween the solder joint and PCB,
which propagates through thePCB for the design 1 and most of the
design 2. The other was failureoccurring on the solder ball just
below the solder pad on the pack-age side. Since the main failure
location is at the interface betweenthe solder ball and pad near
the PCB, solder pad on PCB side wasmajor design variable to
increase stiffness at this location as wellas fatigue life of
memory modules.
Acknowledgements
This research was supported by Samsung Electronics, and Y.Cinar
thanks the Korean National Institute for International Educa-tion
(NIIED) for a scholarship supporting his Ph.D. work.
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Effect of solder pads on the fatigue life of FBGA memory modules
under harmonic excitation by using a global–local modeling
technique1 Introduction2 Analysis model3 Finite element analysis by
a global–local modeling technique3.1 Global model analysis3.2 Local
model analysis
4 Effect of solder pads on the fatigue life of solder joints and
experimental verification4.1 Fatigue life estimation of a memory
module with different pad size4.2 Experimental observation of
fatigue life
5 Failure analysis6 ConclusionAcknowledgementsReferences