Effcient Mapping of Digital Signal Processing Applications

EFFCIENT MAPPING OF DIGITAL SIGNAL PROCESSING APPLICATIONS ON THE BRICK RECONFIGURABLE ARRAY Juan Fernando Eusse Giraldo Department of Electrical Engineering University of Brasilia Brasília/DF, Brazil [email protected] Ricardo Pezzuol Jacobi Department of Computer Science University of Brasilia Brasília/DF, Brazil [email protected] Abstract – BRICK IS an Expression Grain Reconfigurable Architecture designed for digital signal and image processing applications. This paper presents its structure and components and evaluates its architecture through the mapping of three signal processing applications, a 3x3 2-D convolution, a 16-Tap FIR filter and an 8-point FFT in a 4x4 Reconfigurable Array. A performance simulation analysis study is developed comparing the BRICK reconfigurable array VHDL implementation to a MIPS and a SPARC V8 simulators in order to validate the Reconfigurable Array proposal. Considerable gains up to an order of magnitude are obtained and important design issues and challenges were discovered when developing this work. Keywords – Reconfigurable Computing, Expression Grain, Application Mapping, Signal Processing. I. INTRODUCTION Nowadays electronic systems are required to have a great amount of flexibility due to the everyday development of new technologies, standards and the high costs of production of today silicon technologies make electronic products have a very short lifetime. The area and power consumption are main concerns as well, as more and more of these devices are portable and require an increased autonomy in order to satisfy customer requirements. In the past, FPGA emerged as the obvious solution to the flexibility and performance issue, but still had many drawbacks with respect to reconfiguration time and power consumption [1]. Through the past decade, a lot of research has been focused on a new family of reconfigurable computing devices, which aim at solving problems of specific application domains, mainly signal and image processing working with different word sizes (8, 16 and 32-bit). They are based on Coarse Grain architectures and, typically, implement a regular array of functional units which perform a set of word-wide operations. This regular array of functional units is connected by an intercommunication structure which can vary greatly among devices, going from Nearest-Neighbor Connections trough complex Network-On-Chip systems [2-15]. During our research we have developed BRICK [19] , an Expression Grain Reconfigurable Array focused mainly on the image processing application domain that allows efficient mapping of complex expressions and the implementation of a wide variety of applications. To evaluate its architecture, we have successfully mapped inside BRICK a 3x3 convolution used in edge detection in image processing, a FIR filter used in digital communications applications and a Fast Fourier Transform used in signal processing algorithms. Since its focus is on the acceleration of software tasks, the performance of BRICK is compared to MIPS and SPARC V8 implementations of the algorithms, showing considerable gains in execution time. This paper is organized as follows. Section 2 shows the related work in the area of reconfigurable computing. Section 3 shows the BRICK architecture. Section 4 shows the main characteristics of the BRICK Reconfigurable Array. In Section 5 we show the mapping process and results for the three tested applications and Section 6 shows the conclusions and future work. II. RELATED WORK References [3-6][10][12][14], present a survey of the recent research in the field of reconfigurable computing, were several architectures are described. They may have significant variations in terms of granularity, reconfigurability, interconnection and mapping methodologies. Their basic funcionality is implemented, in general, by a multifunctional ALU which is configured to operate with a fixed number of inputs (generally two). Configuring an ALU takes much less time than configuring look-up tables, but reconfiguration time is still a hot topic in current research. Multi-context architectures are frequently used to reduce or even hide reconfiguration times. The large area of the interconnection structures, the DISO (Dual Input, Single Output) nature of the processing elements and the implementation of control oriented algorithms into the reconfigurable arrays are other problems under current research. SmartCell [9] is recent work that focus on data streaming applications. It is composed by a bi-dimensional array of cells, each one with 4 multifunctional ALUs, interconnected by a Network-On-Chip, introducing a degree of flexibility while enabling the communication of any of the cells of the array with each other. The Expression Grained Reconfigurable Arrays (EGRAs) [2] consists of a processing element composed by a reconfigurable datapath which groups a number of heterogeneous ALUs to implement complex expressions as an instruction set extension for a reconfigurable processor. The datapath also provides two optionally registered outputs to implement even more complex expressions divided into pipelining schemes. RoSa [11][16] is a VLIW-like coprocessor in which complex expressions can be mapped through a memory mapped

Effcient Mapping of Digital Signal Processing Applications

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