EECS150 Homework 3 Solutions Fall 2008 Page 1 of 20 1.) The BCD Counter (a) To write C1 in minterm form, we use the rows of the truth table that yield C1=1. For each row, we write the minterm as a product of the inputs ABCD; if the input is a 0 in that row, use the complemented form in the minterm. We get: C1 (A, B, C, D) = m (0, 1, 2, 3, 4, 7, 8, 9) = A B C D A B C D A B CD A B CD A BC D A BCD AB C D AB C D The implementation of C1 in canonical SoP form is shown in Figure 1-1. To write C1 in maxterm form, we use the rows of the truth table that yield C=0. The maxterm is the sum of the inputs A+B+C+D; if the variable is a 1 in that row we use the complemented form in the maxterm. This yields the expression:
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EECS150 Homework 3 Solutions Fall 2008
Page 1 of 20
1.) The BCD Counter
(a) To write C1 in minterm form, we use the rows of the truth table that yield C1=1. For each row,
we write the minterm as a product of the inputs ABCD; if the input is a 0 in that row, use the
complemented form in the minterm. We get:
C1 (A, B, C, D) = m (0, 1, 2, 3, 4, 7, 8, 9)
=
ABCDABCDABCDABCDABCDABCDABCDABCD
The implementation of C1 in canonical SoP form is shown in Figure 1-1.
To write C1 in maxterm form, we use the rows of the truth table that yield C=0. The maxterm is the sum
of the inputs A+B+C+D; if the variable is a 1 in that row we use the complemented form in the maxterm.
This can be implemented directly using two levels (three if you count the inverters needed to invert inputs) of logic (circuit drawn by Logisim):
EECS150 Homework 3 Solutions Fall 2008
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EECS150 Homework 3 Solutions Fall 2008
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b. It is a little bit harder to implement this with only two-input gates given to us. However, we can apply DeMorgan’s Law a few times on our boolean expressions to make it easier to implement using only the gates given to us. This is very tedious, which is why we no longer asked you to go for the minimum gate count. The following implementation uses all NAND gates (drawn by Logisim):
EECS150 Homework 3 Solutions Fall 2008
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d) CLD2: 7.2
This question asks for a counter that is self-starting, composed of 3 flip-flops, and of a non-usual
pattern. By self-starting, the question means that if the counter were to initialize to an arbitrary 3-bit
state, it would be able to get back on track and continue counting its sequence. By 3 flip-flops, the
question means that the state of the counter should be stored in 3 bits of information.
Because the counter counts in a non-trivial pattern, we will represent the counter as a finite
state machine that non-conditionally transitions from state to state with the rising edge of the clock.
With appropriate transition logic, this state machine will accomplish exactly what a normal counter
would. In fact, all counters can be thought of as finite state machines in this way. We start with a high
level bubble-arc diagram as shown below:
000
[000]
001
[001]
011
[011]
110
[110]
100
[100]
111
[111]
010
[010]
Notice that by how we have encoded our states, the output for a given state is the same as the state
encoding. This simplifies the process of computing the outputs: the outputs are just the current state!
Also notice that we have specified a Moore machine. This is because our counter need not change its
outputs based on the current state and the inputs, but rather just the current state. When we can, we
should always use Moore machines as having synchronous outputs with the clock greatly reduces the
chance to have timing violations in our design.
The next step in the design process is to specify the state transition table. This will allow us to
construct a Sum of Products or Product of Sums canonical representation for our next state logic. Note
that you were not required to simplify the Boolean expressions resulting from this step. Karnaugh
maps, which we will soon cover, will designate a relatively simple way to perform this simplification.
EECS150 Homework 3 Solutions Fall 2008
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Our table is inferred directly from our bubble-arc diagram (CS is the current state and NS is the
next state):
CS NS
000
010
111
100
110
011
001
101
010
111
100
110
011
001
000
000
Notice that we have added the 101 state to our table, and that it transitions to state 000. This handles
the self-starting requirement. Specifically, if our circuit initializes to 101, which our counter does not
ever transition to and from naturally, return to 000, which is a legal state, and continue from there. Self-
starting circuits are useful for recovering from unexpected initialization problems, but can also lead to
circuits (which should have broken because of a large bug) seemingly running as expected. This is a
potential trap, and making a circuit self-starting should be done with care.
The next step is to generate a canonical form expression from the above transition table. We will use Sum of Products, however, Product of Sums can also be used. In this problem, as we have to specify the input for 3 different flip-flops, we must construct 3 different canonical form expressions (we will denote the state bits by index; i.e. if NS = 110, then NS[0] = 0, NS[1] = 1 and NS[2] = 1):
]0[]1[]2[
]0[]1[]2[
]0[]1[]2[
]2[
CSCSCS
CSCSCS
CSCSCS
NS
]0[]1[]2[
]0[]1[]2[
]0[]1[]2[
]0[]1[]2[
]1[
CSCSCS
CSCSCS
CSCSCS
CSCSCS
NS
EECS150 Homework 3 Solutions Fall 2008
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]0[]1[]2[
]0[]1[]2[
]0[]1[]2[
]0[
CSCSCS
CSCSCS
CSCSCS
NS
Again, you were not required to simplify these expressions.
The last step is to transform the above Boolean expressions into a combinational logic block that computes the next state. This inferred directly from the above equations. The complete counter, with this combinational logic block and the flip-flops that store the counter’s state, are shown below:
CS[2] CS[1] CS[0] !CS[2] !CS[1] !CS[0]
CS[2]
CS[1]
CS[0]
Count[2]
Count[1]
Count[0]
Clock
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5.) Digikey Problem
The best way to approach this problem is not to make up random numbers (we can tell – we’re
that good), but to sit down in front of a computer and learn how to use the Digi-Key catalogue. This
company is one of the leading US suppliers of various electronic and other components for large-scale
manufacture. Unlike most other suppliers, however, you can also buy things in very small quantities
from this store at nearly reasonable prices. Besides showing you where hardware comes from, this
problem is meant to give you a real estimate of how expensive/inexpensive hardware can be. We
encourage you to shuffle through the catalogue, find some of the parts used in the Calinx or your
computer’s motherboard. Understanding which design choices are expensive and which aren’t is an
important skill to an engineer.
That said, if you took this problem seriously, you probably found it more challenging than
expected: Digi-Key sells thousands upon thousands of similar components, yet does not allow sorting
search results by price. If you do not know exactly what you’re looking for, you may have a hard time
finding the cheapest part. Also important is the fact that Digi-Key lists parts it does not actually have.
Out-of stock parts may be difficult (or impossible) to purchase. When designing a system, you may want
to make sure you can actually buy your components and that the parts you chose have not been
obsolete for a year.
The following are essential when looking for a component:
Availability – is the item in stock? Being able to actually buy the item you want is
helpful.
Unit price – how much is one of these going to cost you?
Minimum quantity – unless you’re prepared to pay 1000x for a crate of these components,
you should pay attention to this number. For this problem, the
minimum order quantity should be 1.
Note : It’s not a problem if you have not found the absolute cheapest part. We’re looking for a sign of
effort, and will accept a broad range of prices found.
As it turns out, there was some ambiguity in this problem: part a specified that the user wanted
to create a shift register; parts b and c didn’t specify anything. For parts b and c, we just wanted you to
find the syntax errors in each Verilog fragment. The fragments didn’t necessarily do anything
interesting. The errors in b and c were either straight up compiler errors, or Verilog “pitfalls” that you
will always want to avoid (see Always.pdf and Reg.pdf).
In the following parts, code fragments indicate corrections to the original code fragments in red,
and make a comment about the correction in blue.
a) The first part is trying to represent a shift register. Instead, what the original code fragment produces is a series of parallel flip-flops. Always.pdf refers to this example explicitly: when you
want to infer registers, you must follow the rules for the always@(posedge Clock) block, namely that every reg assignment should be made with non-blocking (<=) statements. This
ensures that at the positive edge of the Clock, every reg gets set at exactly the same instant. If instead of using non-blocking assignments we use blocking assignments, what we actually get is: RegisterD = RegisterC = RegisterB = Input. This is because when
RegisterB gets set to Input, RegisterC gets set to RegisterB’s new value (by definition of the blocking (=) statement. RegisterB’s new value is Input. This same problem propagates down the flip-flop chain, and the result is either parallel flip-flops or a single
flip-flop whose output is split four-ways between RegisterB, RegisterC, and
RegisterD.
Part a: Errors and corrections
wire Input;
reg RegisterB, RegisterC, RegisterD;
always @(posedge Clock) begin
RegisterB <= Input; // from =
RegisterC <= RegisterB; // from =
RegisterD <= RegisterC; // from =
end
b) This part is an arbitrary Verilog segment. It doesn’t do anything intelligent. The errors in this part were merely syntactical, and specifically wire vs. reg issues. See Nets.pdf for more information. There are multiple ways to fix the bugs in this segment. We will discuss the two mainstream ways.
First, consider the actual bugs in the code fragment, reproduced below: