Page 1
EECS 713 HOMEWORK ASSIGNMENT #2 (170 POINTS)
Design a pseudorandom noise (PN) generator with length 127 Using each of the following technologies (data sheets provided), design a pseudorandom noise generator with a sequence length of 127.
1. FACT (National Semiconductor Advanced CMOS: 74AC devices in DIP package) 2. FAST TTL (Texas Instruments F series TTL: 74F devices in DIP package) 3. 100K ECL (Fairchild 300 series ECL: DIP package) 4. 10G GaAs (GigaBit Logic 10G series: the fastest version in type “C” package) 5. UPG GaAs (NEC Logic)
For each design, provide: a timing diagram for all signals (10 points per technology 5 technologies) estimates of currents from each supply source, a complete list of materials (parts
list), a list of all assumptions made (10 points per technology 5 technologies) For the CMOS and ECL designs (only), provide: a complete schematic showing all pin connections
(10 points per technology 2 technologies) For each technology, determine (10 points per technology 5 technologies) if high-speed design rules should be applied, and the maximum usable clock
frequency. Assumptions used throughout include- for CMOS (FACT) and TTL (FAST) assume a 2-ns risetime (Tr) each trace is 2 inches in length; printed-wiring board (PWB) composed of FR-4 in stripline configuration; assume the worst case timing for all devices, over all temperatures.
Be sure to include the propagation delay through the traces in the timing analysis
Basic circuit arrangement
Page 2
Technology
Item Points possible
CMOSFACT
TTLFAST
ECL100K
GaAs10G
GaAsUPG TOTALS
Timing diagram 5 X 10 each
Current estimatesList of materials, assumptions
5 X 10 each
Schematics 2 X 10 each
High-speed design rules apply ?Maximum usable clock frequency
5 X 10 each
TOTAL 170
Page 3
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Page 5
TL�F�11553
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Page 10
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paga
tion
Del
ay1.
152.
751.
152.
751.
153.
00ns
t PH
LD
ata
to F
t TLH
Tra
nsiti
on T
ime
0.35
1.20
0.35
1.20
0.35
1.20
nst T
HL
20%
to 8
0%, 8
0% to
20%
Page 12
© 2
000
Fai
rchi
ld S
emic
ondu
ctor
Cor
pora
tion
DS
0098
80w
ww
.fairc
hild
sem
i.com
July
198
8
Rev
ised
Aug
ust 2
000
100341 Low Power 8-Bit Shift Register
1003
41L
ow
Po
wer
8-B
it S
hif
t R
egis
ter
Gen
eral
Des
crip
tio
nT
he 1
0034
1 co
ntai
ns e
ight
edg
e-tr
igge
red,
D-t
ype
flip-
flops
with
ind
ivid
ual
inpu
ts (
Pn)
and
out
puts
(Q
n) f
or p
aral
lel
oper
atio
n, a
nd w
ith s
eria
l inp
uts
(Dn)
and
ste
erin
g lo
gic
for
bidi
rect
iona
l sh
iftin
g.
The
fli
p-flo
ps
acce
pt
inpu
t da
ta
ase
tup
time
befo
re t
he p
ositi
ve-g
oing
tra
nsiti
on o
f th
e cl
ock
puls
e an
d th
eir
outp
uts
resp
ond
a pr
opag
atio
n de
lay
afte
rth
is r
isin
g cl
ock
edge
.
The
circ
uit
oper
atin
g m
ode
is d
eter
min
ed b
y th
e S
elec
tin
puts
S0
and
S1,
whi
ch a
re i
nter
nally
dec
oded
to
sele
ctei
ther
“pa
ralle
l en
try”
, “h
old”
, “s
hift
left”
or
“shi
ft rig
ht”
asde
scrib
ed i
n th
e T
ruth
Tab
le.
All
inpu
ts h
ave
50 k
Ω p
ull-
dow
n re
sist
ors.
Fea
ture
s■
35%
pow
er r
educ
tion
of th
e 10
0141
■20
00V
ES
D p
rote
ctio
n
■P
in/fu
nctio
n co
mpa
tible
with
100
141
■V
olta
ge c
ompe
nsat
ed o
pera
ting
rang
e =
−4.2
V to
−5.
7V
■A
vaila
ble
to in
dust
rial g
rade
tem
pera
ture
ran
ge
Ord
erin
g C
od
e:
Dev
ices
als
o av
aila
ble
in T
ape
and
Ree
l. S
peci
fy b
y ap
pend
ing
the
suffi
x le
tter
“X”
to th
e or
derin
g co
de.
Lo
gic
Sym
bo
l
Pin
Des
crip
tio
ns
Co
nn
ecti
on
Dia
gra
ms
24-P
in D
IP/S
OIC
28-P
in P
LC
C
Ord
er N
um
ber
Pac
kag
e N
um
ber
Pac
kag
e D
escr
ipti
on
1003
4SC
M24
B24
-Lea
d S
mal
l Out
line
Inte
grat
ed C
ircui
t (S
OIC
), J
ED
EC
MS
-013
, 0.3
00 W
ide
1003
41P
CN
24E
24-L
ead
Pla
stic
Dua
l-In-
Line
Pac
kage
(P
DIP
), J
ED
EC
MS
-010
, 0.4
00 W
ide
1003
41Q
IV
28A
28-L
ead
Pla
stic
Lea
d C
hip
Car
rier
(PLC
C),
JE
DE
C M
O-0
47, 0
.450
Squ
are
1003
41Q
CV
28A
28-L
ead
Pla
stic
Lea
d C
hip
Car
rier
(PLC
C),
JE
DE
C M
O-0
47, 0
.450
Squ
are
Indu
stria
l Tem
pera
ture
Ran
ge (
−40°
C to
+85
°C)
Pin
Nam
esD
escr
ipti
on
CP
Clo
ck In
put
S0,
S1
Sel
ect I
nput
s
D0,
D7
Ser
ial I
nput
s
P0–
P7
Par
alle
l Inp
uts
Q0–
Q7
Dat
a O
utpu
ts
ww
w.fa
irchi
ldse
mi.c
om2
100341
Tru
th T
able
H=
HIG
H V
olta
ge L
evel
L=
LOW
Vol
tage
Lev
elX
= D
on’t
Car
e=
LOW
-to-
HIG
H T
rans
ition
Lo
gic
Dia
gra
m
Fu
nct
ion
Inp
uts
Ou
tpu
ts
D7
D0
S1
S0
CP
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Load
Reg
iste
rX
XL
LP
7P
6P
5P
4P
3P
2P
1P
0
Shi
ft Le
ftX
LL
HQ
6Q
5Q
4Q
3Q
2Q
1Q
0L
Shi
ft Le
ftX
HL
HQ
6Q
5Q
4Q
3Q
2Q
1Q
0H
Shi
ft R
ight
LX
HL
LQ
7Q
6Q
5Q
4Q
3Q
2Q
1
Shi
ft R
ight
HX
HL
HQ
7Q
6Q
5Q
4Q
3Q
2Q
1
Hol
dX
XH
HX
Hol
dX
XX
XH
No
Cha
nge
Hol
dX
XX
XL