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Slides developed in part by Profs. Austin, Brehob, Falsafi, Hill, Hoe, Lipasti, Slides developed in part by Profs. Austin, Brehob, Falsafi, Hill, Hoe, Lipasti,
Lecture 17 Slide 1EECS 470
Shen, Smith, Sohi, Tyson, and Vijaykumar of Carnegie Mellon University, Shen, Smith, Sohi, Tyson, and Vijaykumar of Carnegie Mellon University, Purdue University, University of Michigan, and University of Wisconsin. Purdue University, University of Michigan, and University of Wisconsin.
2 Parts to Modern VM VM provides each process with the illusion of aVM provides each process with the illusion of a large, private, uniform memory
Part A: Protectioneach process sees a large, contiguous memory segment without holeseach process’s memory space is private, i.e. protected from access by other processesot e p ocesses
Part B: Demand Pagingcapacity of secondary memory (swap space on disk)at the speed of primary memory (DRAM)
Based on a common HW mechanism: address translationt “ i t l” “ ff ti ” dduser process operates on “virtual” or “effective” addresses
HW translates from virtual to physical on each referencecontrols which physical locations can be named by a processll d l f h l b k ( )
Lecture 17 Slide 5EECS 470
allows dynamic relocation of physical backing store (DRAM vs. HD)VM HW and memory management policies controlled by the OS
Evolution of Protection MechanismsEarliest machines had no concept of protection and address translation
no need‐‐‐single process, single userautomatically “private and uniform” (but not very large)programs operated on physical addresses directlyp g p p y y
no multitasking protection, no dynamic relocation (at least not very easily)
base and bound registersIn a multi‐tasking systemIn a multi tasking systemEach process is given a non‐overlapping, contiguous physical memory region, everything belonging to a process must fit in that region
Wh i d i OS t b t th t t f th ’When a process is swapped in, OS sets base to the start of the process’s memory region and bound to the end of the region
HW translation and protection check (on each memory reference)
PA = EA + base
provided (PA < bound), else violations
⇒ Each process sees a private and uniform address space (0 .. max)
segmented addressing gives each process multiple segmentsinitially, separate code and data segments
‐ 2 sets of base‐and‐bound reg’s for inst and data fetch‐ allowed sharing code segments
became more and more elaborate: code, data, stack, etc.beca e o e a d o e e abo ate code, data, stac , etcalso (ab)used as a way for an ISA with a small EA space to address a larger physical memory space
Segmented addressing creates fragmentation problemsSegmented addressing creates fragmentation problems, a system may have plenty of unallocated memory locationsthey are useless if they do not form a contiguous region of a ffi i isufficient size
In a Paged Memory System:
PA i di id d i fi d i ( 4kb )PA space is divided into fixed size segments (e.g. 4kbyte), more commonly known as “page frames”
EA is interpreted as page number and page offsetEA is interpreted as page number and page offset
To Virtual pages that map to the same physical pageTo Virtual pages that map to the same physical pagewithin the same virtual address spaceacross address spaces
VA1
VA2
PA
Using VA bits as IDX PA data may reside in different sets in cache!!
Lecture 17 Slide 21EECS 470
Using VA bits as IDX, PA data may reside in different sets in cache!!
Synonym (or Aliasing)When VPN bits are used in indexing, two virtual addresses that map to the same physical Virtual Pg No. (VPN) p p yaddress can end up sitting in two cache lines
Tag Index Page OffsetIndex BO
g ( )
In other words, two copies of the same physical memory location
D-cache
i ba
may exist in the cache
⇒modification to one copy won’t be visible in the other
PPND t
p
pPPNwon t be visible in the other=
DataHit/Miss
pPPNfromTLB
Lecture 17 Slide 22EECS 470
If the two VPNs do not differ in a then there is no aliasing problem
R10000’s Virtually Index Caches32KB 2‐Way Virtually‐Indexed L1
needs 10 bits of index and 4 bits of block offset page offset is only 12‐bits ⇒ 2 bits of index are VPN[1:0]p g y [ ]
Direct‐Mapped Physical L2 L2 is Inclusive of L1VPN[1:0] is appended to the “tag” of L2
Given two virtual addresses VA and VB that differs in a and both map to the same physical address PAmap to the same physical address PA
Suppose VA is accessed first so blocks are allocated in L1&L2What happens when VB is referenced?1 VB i d t diff t bl k i L1 d i1 VB indexes to a different block in L1and misses2 VB translates to PA and goes to the same block as VA in L23. Tag comparison fails (VA[1:0]≠VB[1:0])4 L2 detects that a synonym is cached in L1⇒ VA’s entry in L1 is
Lecture 17 Slide 24EECS 470
4. L2 detects that a synonym is cached in L1 ⇒ VA s entry in L1 is ejected before VB is allowed to be refilled in L1
paired: each entry maps 2 consecutive VPNs to 2 different PPNssoftware managed
7‐instruction page table walk in the best caseTLB Write Random: chooses a random entry for TLB replacementOS can exclude some number of TLB entry (low range) to be excluded from the random selection, to hold translations that cannot miss or should not miss
TLB entry
N h bl
VPN20 ASID6 06PPN20 ndvg 08
R2000
N: noncacheableD: dirty (actually a write‐enable bit)V: valid
**must hold at least N PTE’s for a system with 2N physical pagesHW table walk
table base +
y p y p gHW table walkVPN hashes into a PTE group of 88 PTEs searched sequentially for tag matchf f d f h dif not found in first PTE group search a second PTE groupif not found in the 2nd PTE group, trap to software handler
Hashed table structure also used for EA to VA mapping in 64‐bit
Lecture 17 Slide 32EECS 470
Hashed table structure also used for EA to VA mapping in 64 bit implementations
V i bl i d t d EA t VAVariable sized segmented EA to VA
A diff i iA different twist on protectioneveryone else: limit what can be named by a process
In PowerPC, OS controls what VA can be reached by a process by controlling h ’ i h iwhat’s in the segment registers
HP‐RISC: rights‐based access controlUser controls segment registers, i.e., user can generate any VA it wantsEach virtual page has an access ID (not related to ownership by processes) assigned by the OSEach process has 8 active protection ID in special HW registers controlled by the OS
Lecture 17 Slide 33EECS 470
the OSA process can only access a page if it has the key (PID) that fits the lock (AID)