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EECS 141: FALL 2008 – MIDTERM 2 1/10
University of California College of Engineering
Department of Electrical Engineering and Computer Sciences
E. Alon Thursday, November 6, 2008 6:30-8:00pm
EECS 141: FALL 2008—MIDTERM 2
For all problems, you can assume that all transistors have a
channel length of 100nm and the following parameters (unless
otherwise mentioned): NMOS: VTn = 0.2V, µn = 400 cm2/(V·s), Cox =
1.125 µF/cm2, vsat = 1e7 cm/s, λ = 0 PMOS: |VTp| = 0.2V, µp = 200
cm2/(V·s), Cox = 1.125 µF/cm2, vsat = 1e7 cm/s, λ = 0
NAME Last First
GRAD/UNDERGRAD
Problem 1: _____/ 18
Problem 2: _____/ 30
Problem 3: _____/ 20
Total: _____/ 68
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EECS 141: FALL 2008 – MIDTERM 2 2/10
PROBLEM 1. (18 pts) SRAMs and Wires In this problem, we will be
looking at a 256 x 256 SRAM, where each 6T cell is 2µm wide and
1.5µm tall. All of the devices in the SRAM cell are minimum length
(L = 0.1µm), and you can assume that both the NMOS access
transistors and the NMOS pull-down transistors are 0.25µm wide, and
that the PMOS transistors are 0.12µm wide. The bitline wires are
0.2µm wide. You can also assume that VDD = 1.2V, CG = CD = 1fF/µm,
and that the wires have the following characteristics: Cpp =
100aF/µm2, Cfr = 50aF/µm/edge, and Rsq,w = 0.1Ω/.
a) (6 pts) What is the total capacitance loading each bitline in
this memory?
b) (7 pts) If we were reading to or writing from the SRAM array,
what is the worst-
case RC delay due to the bitline wire? You can assume that the
input is a ramp (i.e., tp = τElmore).
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EECS 141: FALL 2008 – MIDTERM 2 3/10
c) (5 pts) If the VDD of the SRAM was raised to 1.3V, would the
RC delay of the bitline wire increase, decrease, or stay the same?
You don’t need to do any calculations, but you do need to explain
your answer.
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EECS 141: FALL 2008 – MIDTERM 2 4/10
PROBLEM 2. (30 pts) Activity Factors and Sensitivity Analysis.
This problem will deal with the circuit shown below; throughout
this problem you can assume that CD = 0.
a) (6 pts) Assuming that all of the inputs A, B, C, and D have
equal probability of being a 1 or a 0, what are the activity
factors (i.e., α0 1) at each of the nodes of the circuit (i.e., n0
– n3)?
Node α0 1
n0
n1
n2
n3
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EECS 141: FALL 2008 – MIDTERM 2 5/10
b) (6 pts) Assuming the circuit operates with a supply voltage
VDD and a clock frequency f, what is the total dynamic power
consumed by this circuit as a function of Cin, C1, C2, and Cload
(as labeled above)? Note that you should include the power
dissipated by driving the A, B, C, and D inputs. If you aren’t sure
about your answers for part a), please assume that all of the
activity factors are 1/8 (which is not the correct answer to part
a).
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EECS 141: FALL 2008 – MIDTERM 2 6/10
c) (4 pts) Assuming that A is the critical input (i.e., the last
one to transition) and that the transistors are quadratic
long-channel, what is the delay of the decoder (in units of tinv)
as a function of Cin, C1, C2, and Cload?
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EECS 141: FALL 2008 – MIDTERM 2 1/9
University of California College of Engineering
Department of Electrical Engineering and Computer Sciences
E. Alon Thursday, November 5, 2009 6:30-8:00pm
EECS 141: FALL 2009—MIDTERM 2
For all problems, you can assume that all transistors have a
channel length of 100nm and the following parameters (unless
otherwise mentioned): NMOS: VTn = 0.2V, µn = 400 cm2/(V·s), Cox =
1.125 µF/cm2, vsat = 1e7 cm/s, λ = 0 PMOS: |VTp| = 0.2V, µp = 200
cm2/(V·s), Cox = 1.125 µF/cm2, vsat = 1e7 cm/s, λ = 0
NAME Last First
GRAD/UNDERGRAD
Problem 1: _____/ 14
Problem 2: _____/ 30
Problem 3: _____/ 14
Total: _____/ 58
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EECS 141: FALL 2008 – MIDTERM 2 4/9
PROBLEM 2. (30 pts) Decoder Energy-Delay Tradeoffs. This problem
will deal with the final decoder circuit shown below. This final
decoder is used inside of a 32x32 SRAM, where A and B are outputs
from the predecoders. Throughout this problem you can assume that
CG = 2fF/µm, CD = 0, Rsqn = Rsqp/2 = 10kΩ, that the transistors are
long-channel from the standpoint of calculating logical effort, and
that subthreshold leakage current is negligible.
a) (6 pts) In units of tinv and as a function of W1, W2, and
Cwl/CG, what is the delay of the final decoder from A or B rising
to WL rising?
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EECS 141: FALL 2008 – MIDTERM 2 5/9
b) (11 pts) Assuming that the SRAM operates at a clock frequency
of f, what is the average power consumed by this final decoder? You
do not need to include the power consumed by driving the A, B, and
En inputs, and you can assume that the En signal is a clock, but
that it is only high 20% of the clock cycle. For simplicity you can
also assume that the VOL of the ratioed gate is ~0V, and that the
IDSAT of a PMOS transistor is equal to VDD/(Rsqp*L/W).
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EECS 141: FALL 2009 – MIDTERM 1 1/9
University of California College of Engineering
Department of Electrical Engineering and Computer Sciences
E. Alon Tuesday, October 6, 2009 6:30-8:00pm
EECS 141: FALL 2009—MIDTERM 1
For all problems, you can assume that all transistors have a
channel length of 90nm and the following parameters (unless
otherwise mentioned): NMOS: VTn = 0.2V, µn = 400 cm2/(V·s), Cox =
1.125 µF/cm2, vsat = 1e7 cm/s, λ = 0 PMOS: |VTp| = 0.2V, µp = 200
cm2/(V·s), Cox = 1.125 µF/cm2, vsat = 1e7 cm/s, λ = 0
NAME Last First
GRAD/UNDERGRAD
Problem 1: _____/ 30
Problem 2: _____/ 20
Problem 3: _____/ 20
Total: _____/ 70
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EECS 141: FALL 2009 – MIDTERM 1 2/9
PROBLEM 1. Logical Effort and Gate Sizing (30 points)
a) (6 pts) What is the path effort from In to Out?
b) (2 pts) What EF/stage minimizes the delay of this chain of
gates?
c) (8 pts) Size the gates to minimize the delay from In to
Out.
Size Value (fF)
a
b
c
d
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EECS 141: FALL 2009 – MIDTERM 1 3/9
d) (6 pts) While maintaining the same logical functionality and
without changing Cin, can you improve the delay of this chain of
gates (repeated below) by changing the number and/or types of
gates? Please draw an improved schematic for the new chain of
gates; you don’t need to provide gate sizes.
Original chain:
Improved chain:
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EECS 141: FALL 2009 – MIDTERM 1 4/9
e) (8 pts) Now let’s imagine that you are working in a new
technology where the γ (= CD/CG) of the transistors is 100. Now how
would you redesign the chain of gates in order to improve its
delay? Please draw an improved schematic for the new chain of
gates; you don’t need to provide gate sizes. (You will receive
partial credit if you can explain in general how γ should affect
the design of the chain.)
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EECS 141: FALL 2010 – MIDTERM 2 1/10
University of California College of Engineering
Department of Electrical Engineering and Computer Sciences
E. Alon Thursday, November 4, 2010 6:30-8:00pm
EECS 141: FALL 2010—MIDTERM 2
For all problems, you can assume that all transistors have a
channel length of 100nm and the following parameters (unless
otherwise mentioned): NMOS: VTn = 0.3V, µn = 400 cm2/(V·s), Coxn =
1 µF/cm2, vsat = 1e7 cm/s, λ = 0 PMOS: |VTp| = 0.3V, µp = 200
cm2/(V·s), Coxp = 0.75 µF/cm2, vsat = 1e7 cm/s, λ = 0
NAME Last First
GRAD/UNDERGRAD
Problem 1: _____/ 24
Problem 2: _____/ 18
Problem 3: _____/ 24
Total: _____/ 66
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EECS 141: FALL 2010 – MIDTERM 2 2/10
PROBLEM 1. (24 pts) Wires, Delay, and Ratioed Logic For this
problem, you should assume that all of the transistors are minimum
channel length (L=0.1µm) and have the following characteristics: CG
= CD = 2fF/µm and Rsqn = Rsqp/2 = 10kΏ/□. For the wires, you should
assume that Cwpp = 0.05fF/µm2, Cwfringe = 0.075fF/µm/edge, and Rsqw
= 0.1Ώ/□
a) (6 pts) For the circuit shown above, size the PMOS pull-up
transistor (i.e., choose Wp) so that the pull-up resistance of the
gate is equal to 4 times the worst-case pull-down resistance.
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EECS 141: FALL 2010 – MIDTERM 2 3/10
b) (10 pts) Assuming that you found that Wp = 1.25um in order
for the pull-up resistance to be 4 times larger than the worst-case
pull-down resistance (as shown above – note that this may or may
not be the right answer to part a) ), what is the worst-case ramp
delay of the circuit?
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EECS 141: FALL 2010 – MIDTERM 2 4/10
c) (8 pts) Assuming that every time you add another input to the
circuit an additional
200um of wire is added as well (as shown above for 3 inputs),
and that the pull-up transistor is always resized to make its
resistance 4 times that of the worst-case pull-down resistance,
what is the worst-case ramp delay of the circuit as a function of
the number of inputs (Nin)?
MidtermReview2-141_F08_mid2_solMidtermReview2-141_F09_mid2_solMidtermReview2-141_MT1-F09-solMidtermReview2-141_MT2-F10_sol