EECE476 Lecture 7: Single-Cycle CPU Instruction Processing & Control Chapter 5, Sections 5.3, 5.4 The University of British ColumbiaEECE 476© 2005 Guy.

EECE476

Lecture 7: Single-Cycle CPUInstruction Processing & Control

Chapter 5, Sections 5.3, 5.4

The University ofBritish Columbia EECE 476 © 2005 Guy Lemieux

2

Missing Pieces: Instruction Fetching

• Where does the Instruction come from?– From instruction memory, of course!

– Recall: stored-program concept• Alternatives? How about hard-coding wires and switches…?

This is how ENIAC was programmed!

• How to branch?– BEQ rs, rt, Imm16

3

Instruction Processing

• Fetch instruction• Execute instruction

• Fetch next instruction• Execute next instruction

• Fetch next next instruction• Execute next next instruction

• Etc…

• How to maintain sequence? Use a counter!• Branches (out of sequence) ? Load the counter!

4

Instruction Processing

• Program Counter– Points to current instruction

– Address to instruction memory• Instr ← InstrMem[PC]

– Next instruction: counts up by 4• Remember: memory is byte-addressable, instructions are 4 bytes

• PC ← PC + 4

– Branch instruction: replace PC contents

5

Step 1: Analyze Instructions• Register Transfer Language…

op | rs | rt | rd | shamt | funct = InstrMem[ PC ]

op | rs | rt | Imm16 = InstrMem[ PC ]

Instr Register Transfers

ADDU R[rd] ← R[rs] + R[rt]; PC ← PC + 4

SUBU R[rd] ← R[rs] – R[rt]; PC ← PC + 4

ORI R[rt] ← R[rs] + zero_ext(Imm16); PC ← PC + 4

LOAD R[rt] ← MEM[ R[rs] + sign_ext(Imm16)]; PC ← PC + 4

STORE MEM[ R[rs] + sign_ext(Imm16) ] ← R[rt]; PC ← PC + 4

BEQ if ( R[rs] == R[rt] ) then PC ← PC + 4 + { sign_ext(Imm16)] || b’00’ } else

PC ← PC + 4

6

Steps 2 and 3: Datapath Components & Assembly

• PC: a register– Counter, counts by +4– Provides address to Instruction Memory

Add

Readaddress

InstructionMemory

Instruction[31:0]

PC

Instruction[31:0]

4

7

Steps 2 and 3: Datapath Components & Assembly

Add AddAdd

result

Readaddress

InstructionMemory

Instruction[31:0]

PC

0Mux1

Sign/Zero

Extend

Instruction[25:21]

Instruction[20:16]

Instruction[15:11]

Instruction[15:0] (Imm16)

16 32

PCSrcShiftLeft 2

4

PC: a register• Counter, counts by +4• Sometimes, must add

SignExtend{Imm16||b’00’} for branch instructionsNote: the sign-extender for Imm16

is already in the datapath(everything else is new)

ExtOp

8

Steps 2 and 3: Add Previous Datapath

Add Add

ALU

Addresult

ALUresult

Zero

Readaddress

InstructionMemory

Instruction[31:0]

RegisterFile

DataMemory

PC

Addr-ess

Readdata

Writedata

0Mux1

1Mux0

0Mux1

0Mux1

ALUControl

Sign/Zero

Extend

Writereg.

Readreg. 1

Readreg. 2

Readdata 2

Readdata 1

Writedata

Instruction[25:21]

Instruction[20:16]

Instruction[15:11]

Instruction[15:0] (Imm16)

Instruction[5:0] (funct)

16 32

RegWrite

RegDst

ALUSrc

MemWrite

PCSrc

MemtoReg

ALUOp

ShiftLeft 2

4

ExtOp

9

What have we done?

• Created a simple CPU datapath– Control still missing (next slide)

• Single-cycle CPU– Every instruction takes 1 clock cycle

– Clocking ?

10

One Clock Cycle• Clock Locations

– PC, REGFILE have clocks

• Operation– On rising edge, PC will get new value

• Maybe REGFILE will have one value updated as well– After rising edge

• PC and REGFILE can’t change• New value out of PC• Instruction out of INSTRMEM• Instruction selects registers to read from REGFILE• Instruction controls ALUop, ALUsrc, MemWrite, ExtOp, etc• ALU does its work• DataMem may be read (depending on instruction)• Result value goes back to REGFILE• New PC value goes back to PC• Await next clock edge

Lots to do in only1 clockcycle !!

11

Missing Steps?• Control is missing (Steps 4 and 5 we mentioned earlier)

– Generate the green signals• ALUsrc, MemWrite, MemtoReg, PCSrc, RegDst, etc

– These are all f(Instruction), where f() is a logic expression– Will look at control strategies in upcoming lecture

• Implementation Details– How to implement REGFILE?

• Read port: tristate buffers? Multiplexer? Memory?• Two read ports: two of above?• Write port: how to write only 1 register?

– How to control writes to memory? To register file?

• More instructions– Shift instructions– Jump instruction– Etc

12

1-Cycle CPU Datapath

Add Add

ALU

Addresult

ALUresult

Zero

Readaddress

InstructionMemory

Instruction[31:0]

RegisterFile

DataMemory

PC

Addr-ess

Readdata

Writedata

0Mux1

1Mux0

0Mux1

0Mux1

ALUControl

Sign/Zero

Extend

Writereg.

Readreg. 1

Readreg. 2

Readdata 2

Readdata 1

Writedata

Instruction[25:21]

Instruction[20:16]

Instruction[15:11]

Instruction[15:0] (Imm16)

Instruction[5:0] (funct)

16 32

RegWrite

RegDst

ALUSrc

MemWrite

PCSrc

MemtoReg

ALUOp

ShiftLeft 2

4

ExtOp

13

1-cycle CPU Datapath + Control

PCSrc

Instruction[25:21]

Instruction[20:16]

Instruction[15:11]

Instruction[15:0]

Instruction[5:0]

Instruction[31:26]

Sign/Zero

Extend

DataMemory

Addr-ess

Readdata

Writedata

ALUALU

result

Zero

Readaddress

InstructionMemory

Instruction[31:0]

Add

PC

4

AddAdd

resultShiftLeft 2

RegisterFile

Writereg.

Readreg. 1

Readreg. 2

Readdata 2

Readdata 1

Writedata

RegDst

BranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite

ALUcontrol

Con-trol

14

Input or Output Signal Name R-format Lw Sw Beq

Inputs

Op5 0 1 1 0

Op4 0 0 0 0

Op3 0 0 1 0

Op2 0 0 0 1

Op1 0 1 1 0

Op0 0 1 1 0

Outputs

RegDst 1 0 X X

ALUSrc 0 1 1 0

MemtoReg 0 1 X X

RegWrite 1 1 0 0

MemRead 0 1 0 0

MemWrite 0 0 1 0

Branch 0 0 0 1

ALUOp1 1 0 0 0

ALUOp0 0 0 0 1• Also: I-type instructions (ORI) & ExtOp (sign-extend control), etc.

1-cycle CPU Control(Just a Simple Lookup Table)

15

1-cycle CPU + Jump Instruction

Error in TextFig 5.24Instruction

[31:26]

Instruction[25:0]

PC + 4 [31..28]

Jump address [31..0]

Instruction[25:21]

Instruction[20:16]

Instruction[15:11]

Instruction[15:0]

Instruction[5:0]

16

1-cycle CPU Problems?

• Every instruction 1 cycle• Some instructions “do more work”

– Eg, lw must read from DATAMEM

• All instructions must have same clock period…

Many instructions run slower than necessary

• Tricky timing on MemWrite, RegWrite(?) signals– Write signal must come *after* address is stable

• Need extra resources…– PC+4 adder, ALU for BEQ instruction, DATAMEM+INSTRMEM

17

Performance!

• Single-Cycle CPU Performance– Execute one instruction per clock cycle (CPI=1)– Clock cycle time? Note dataflow includes:

– INSTRMEM read– REGFILE access– Sign extension– ALU operation– DATAMEM read– REGFILE/PC write

– Not every instruction uses all resources (eg, DATAMEM read)– Can we change clock period for each instruction?

• No! (Why not?)

– One clock period: the worst case!– This is why a single-cycle CPU is not good for performance