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EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British Columbia EECE 476 © 2005 Guy Lemieux
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EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

Dec 22, 2015

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Page 1: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

EECE476: Computer Architecture

Lecture 0: Computer Architecture

Chapter 1

The University ofBritish Columbia EECE 476 © 2005 Guy Lemieux

Page 2: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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What is this ?

Page 3: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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64 kBData

Cache

64 kBInstr.Cache

Load/Store

ExecutionUnit

Fetch ScanAlign

Micro-code

BusUnit

HyperTransport DDR Memory Interface

1 MB UnifiedInstruction/DataLevel 2 Cache

Floating-Point Unit

Memory Controller

What is this ?

This is an

AMD Operton CPU

Total Area: 193 mm2

Look at the relative

sizes of each block:

50% cache50% cache

23% I/O

20% CPU logic

+ extra stuff

CPUs dedicate > 50% area for cache memorycache memory.

In this course, you will learn how to build a CPU like this!

Page 4: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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What is Computer Architecture?

Page 5: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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What is Computer Architecture?

• Historic definition

Computer Architecture =

Instruction Set Architecture +

Computer Organization

• Term coined by IBMer: Frederick Brooks (~1957)

Page 6: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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What isInstruction Set Architecture?

• Important acronym: ISA– Instruction Set Architecture

• The low-level software interface to the machine– Language of the machine– Must translate any programming language into this language– Examples: IA-32 (Intel instruction set), MIPS, SPARC, Alpha,

PA-RISC, PowerPC, …

• Visible to programmer (if desired)!

Page 7: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Instruction Set Architecture

I/O systemInstr. Set Proc.

Compiler

OperatingSystem

Application

Digital DesignCircuit Design

Instruction Set Architecture

Firmware

Datapath & Control

Layout

Software

Hardware

Page 8: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Instruction Set Architecture

• Original definition:

… the attributes of a [computing] system as seen by the programmer,

i.e. the conceptual structure and functional behavior,

as distinct from the organization of the data flows

and controls the logic design, and the physical implementation.”

• Amdahl, Blaaw, Brooks, 1964

Page 9: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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What is Computer Organization?

• Computer organization is the implementation of the machine, consisting of two components:– High-level organization

• Memory system widths, bus structure, CPU internal organization, …

– Hardware• Precise logic and circuit design, mechanical packaging, …

• Many implementations are possible for an ISA !!!– Intel i386, i486, Pentium, Pentium II, …– Performance, complexity, cost differences….

• Invisible to the programmer (mostly)!

Page 10: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Computer Organization• Example of internal CPU organization

Page 11: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Your Background

• You took:– EECE 256 – Intro to digital logic– EECE 259 – Intro to microcomputers– EECE 353/379 – Advanced digital systems

• Plus, you know how to write software….

• Now you’re ready to design an entire computer system!– Come up with an ISA– Design the CPU to run it (organization + hardware)

Page 12: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Designing a Computer System

• Now you’re ready to design an entire computer system!– But wait, there are many trade-offs:

• Cost• Complexity• Performance• Power Consumption

• The goal of this course is to expose you to these trade-offs so you can make intelligent design decisions!!!– Focus on Cost, Complexity, Performance

• THIS COURSE – focus “inside the CPU”• EECE465 will look “outside the CPU”

Page 13: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Computing History – Volume 1

• Sticks, stones, strings, …– Ancient counting and measuring devices

• Abacus (~3000BC)

• Napiers bones (1617)

• Slide Rule (1625)– Arithmetic aids (e.g., addition, multiplication)

Page 14: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Computing History – Volume 2

• Charles Babbage (1791-1871)– “Grandfather of Computing”

– Designed mechanical computers using gears• Difference Engine (1822-1833)

– Tabulated polynomials using the difference method– Didn’t work, limited tolerances in gear-making technology

• Analytical Engine (1833-1842)– More general, programmable (punch cards!)– Never built due to financing (& failures with D.E.)

• In 1855, Swedish family built an operational D.E. !!!

– http://en.wikipedia.org/wiki/Charles_Babbage

Page 15: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Computing History – Volume 2

• Augusta Ada King, Countess of Lovelace (1815-1852)

– The world’s “First Computer Programmer”

– Designed programs to run on Babbage’s Analytical Engine• Some controversy over her exact role

– Defined an algebra engine• Could operate on symbols as well as numbers

– http://en.wikipedia.org/wiki/Ada_Lovelace

– See also programming language “Ada” (1980)• http://en.wikipedia.org/wiki/Ada_programming_language

Page 16: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Computing History – Volume 3<1946 ENIAC

– Univ. of Pennsylvania– 18,000 vacuum tubes– 30 tons, 80’ x 8.5’

1949 ESDAC– Cambridge University– Stored-program computer

1949 Mark I– Harvard University– Harvard Architecture

• Separate instr. and data memory• vs. von Neumann / Princeton

1949 BINAC– Eckert-Mauchly Computer Corp.– First Commercial Computer

1951 UNIVAC-1– Remington-Rand– $1,000,000 each– Sold 48 systems

1952 IBM 701– Sold 19 systems

1964 IBM System/360– $5,000,000,000 invested– Computer family, all use same

instructions– Computer architecture is born!

1965 DEC PDP-8– First minicomputer– Spawns MULTICS, UNIX, C

1971 Intel 4004– First microprocessor– 2,300 transistors

Page 17: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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The Transistor (1947)

• Invented in 1947 at Bell Labs– Bardeen, Brattain, and Shockley

• Important because vacuum tubes are unreliable!

Page 18: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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The Integrated Circuit (1958-9)

• Invented in Texas and California– Robert Noyce, Fairchild Semiconductor– Jack Kilby, Texas Instruments– Noyce was first to patent the idea….

• Now, multiple transistors can be placed in one piece of silicon!!!

Page 19: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Moore’s Law and Intel CPUs

• Source: Intel

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Moore and moore transistors…• Moore’s Law (1965)

– Gordon Moore, Fairchild Semiconductor– Noticed 2x number of transistors every 12-18 months

"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain for nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000.”

"I believe that such a large circuit can be built on a single wafer."

• 1968: Robert Noyce and Gordon Moore left Fairchild– Founded Intel (short for “INTegrated ELectronics”)

• 1971: Intel 4004, the world’s first microprocessor!

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More and more transistors…

• Increasing number of transistors makes it possible to build more complex implementations– eg, i386 to i486 to Pentium ….

• Complexity allows improved computer organization with higher processing throughput– Really, it is mostly due to improved CPU organization– Modern term for CPU organization

• CPU Microarchitecture

Page 22: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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Computer Architecture

• Modern definition

Computer Architecture =

Instruction Set Architecture +

CPU Microarchitecture +

Computer Organization• [definition by me!]

EECE476(inside the CPU)

EECE465(outside the CPU)

Page 23: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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CPU Microarchitecture

• CPU Microarchitecture– Detailed internal CPU implementation of an ISA

• Logical organization of CPU internals, including– Cache sizes, organization– Pipeline depth– Number of functional units

• Methods for enhancing/detecting parallelism during execution– Dependence checking, parallel dispatch, out-of-order completion– Branch prediction, speculation

– Another view• How to use a 1,000,000,000 transistor budget

– Responsible for high-performance in modern CPUs

Page 24: EECE476: Computer Architecture Lecture 0: Computer Architecture Chapter 1 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

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ISA & CPU Family Tree