EECC550 - Shaaban EECC550 - Shaaban #1 Lec # 5 Winter 2005 1-10-200 Major CPU Design Steps Major CPU Design Steps 1. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. – This provides the the required datapath components and how they are connected to meet ISA requirements. 2. Select required datapath components, connections & establish clock methodology (e.g clock edge-triggered). 3. Assemble datapath meeting the requirements. 4. Identify and define the function of all control points or signals needed by the datapath. – Analyze implementation of each instruction to determine setting of control points that affects its operations and register transfer. 5. Design & assemble the control logic. – Hard-Wired: Finite-state machine implementation. – Microprogrammed. (Chapter 5.5)
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EECC550 - Shaaban #1 Lec # 5 Winter 2005 1-10-2006 Major CPU Design Steps 1. Analyze instruction set operations using independent RTN ISA => RTN => datapath.
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4. Identify and define the function of all control points or signals needed by the datapath.– Analyze implementation of each instruction to determine setting of control points that affects its operations and
register transfer.
5. Design & assemble the control logic.– Hard-Wired: Finite-state machine implementation.– Microprogrammed.
Reducing Cycle Time: Multi-Cycle DesignReducing Cycle Time: Multi-Cycle Design• Cut combinational dependency graph by inserting registers / latches.• The same work is done in two or more shorter cycles, rather than one long
cycle.
storage element
Acyclic CombinationalLogic
storage element
storage element
Acyclic CombinationalLogic (A)
storage element
storage element
Acyclic CombinationalLogic (B)
=>
Place registers to:• Get a balanced clock cycle length• Save any results needed for the remaining cycles
Example Multi-cycle DatapathExample Multi-cycle Datapath
PC
Nex
t P
C
Ext
ALU Reg
. F
ile
Mem
Acc
ess
Dat
aM
em
AL
Uct
r
Reg
Dst
AL
US
rc
Ext
Op
Bra
nch,
Jum
p
Reg
Wr
Mem
Wr
Mem
Rd
IR
A
B
R
M
RegFile
Mem
ToR
eg
Equ
al
Registers added: All clock-edge triggered (not shown register write enable control lines)
IR: Instruction registerA, B: Two registers to hold operands read from register file.R: or ALUOut, holds the output of the main ALUM: or Memory data register (MDR) to hold data read from data memoryCPU Clock Cycle Time: Worst cycle delay = C = 2ns (ignoring MUX, CLK-Q delays)
Instruction Fetch (IF) 2ns
Instruction Decode (ID) 1ns
Execution (EX) 2ns
Memory (MEM) 2ns
Write Back (WB) 1ns
To Control Unit
Assuming the following datapath/control hardware components delays:Memory Units: 2 ns ALU and adders: 2 nsRegister File: 1 ns Control Unit < 1 ns
Single-Cycle CPU:CPI = 1 C = 8nsOne million instructions take = I x CPI x C = 106 x 1 x 8x10-9 = 8 msec
Multi-Cycle CPU:CPI = 3 to 5 C = 2nsOne million instructions take from 106 x 3 x 2x10-9 = 6 msecto 106 x 5 x 2x10-9 = 10 msecdepending on instruction mix used.
8ns (125 MHz)
Assuming the following datapath/control hardware components delays:Memory Units: 2 ns ALU and adders: 2 nsRegister File: 1 ns Control Unit < 1 ns
Finite State Machine (FSM) Control ModelFinite State Machine (FSM) Control Model• State specifies control points (outputs) for Register Transfer.• Control points (outputs) are assumed to depend only on the current state
and not inputs (i.e. Moore finite state machine)• Transfer (register/memory writes) and state transition occur upon exiting
Control Specification For Multi-cycle CPUControl Specification For Multi-cycle CPUFinite State Machine (FSM) - State Transition DiagramFinite State Machine (FSM) - State Transition Diagram
•Shared instruction/data memory unit• A single ALU shared among instructions• Shared units require additional or widened multiplexors• Temporary registers to hold data between clock cycles of the instruction:
• Additional registers: Instruction Register (IR), Memory Data Register (MDR), A, B, ALUOut
The Effect of The 1-bit Control Signals Signal Name
RegDst
RegWrite
ALUSrcA
MemRead
MemWrite
MemtoReg
IorD
IRWrite
PCWrite
PCWriteCond
Effect when deasserted (=0)
The register destination number for thewrite register comes from the rt field(instruction bits 20:16).
None
The first ALU operand is the PC
None
None
The value fed to the register write data input comes from ALUOut register.
The PC is used to supply the address to thememory unit.
None
None
None
Effect when asserted (=1)
The register destination number for thewrite register comes from the rd field(instruction bits 15:11).The register on the write register inputis written with the value on the Write data input.
The First ALU operand is register A (I.e R[rs])
Content of memory specified by the address input are put on the memory data output.
Memory contents specified by the address input is replaced by the value on the Write data input.
The value fed to the register write data input comes from data memory register (MDR).
The ALUOut register is used to supply the the address to the memory unit.
The output of the memory is written into Instruction Register (IR)
The PC is written; the source is controlled by PCSource
The PC is written if the Zero output of the ALU isalso active.
High-Level View of Finite State High-Level View of Finite State Machine ControlMachine Control
• First steps are independent of the instruction class• Then a series of sequences that depend on the instruction opcode• Then the control returns to fetch a new instruction.• Each box above represents one or several state.