EEC-553 CAD OF ELECTRONICS LAB FILE

INDEX

S.NO

1.

2.

3.

4.

5.

6.

7.

8.

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10.

11.

EXPERIMENT NAME

Transient analysis and simulation of CMOS inverter.

Transient and simulation analysis of NAND gate.

Transient and simulation analysis of CMOS nor gate..Transient analysis and simulation of NMOS inverter..Transient analysis and simulation of BJT inverter.

Design of 4:1 multiplexer using “with” statement.

Design of 4:1 multiplexer using “when” statement.

Design of 4:1 multiplexer using “case” statement.

Design D flip-flop with “reset using VHDL”.

Design full adder using half adder for structural modelling.

Design of 4-bit ripple carry adder using full adder as a component for structural modelling.

EXPERIMENT 01

Object- Transient analysis and simulation of CMOS inverter.

Software used- orcade Lite-9.1.

Theory - CMOS inverters (Complementary NOSFET Inverters) are some of the most widely used and adaptable MOSFET inverters used in chip design. They operate with very little power loss and at relatively high speed.

A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal, were VIN is connected to the gate terminals and VOUT is connected to the drain terminals.(See diagram)

The circuit below is the simplest CMOS logic gate.

• When a low voltage (0 V) is applied at the input, the top transistor (P-type) is conducting (switch closed) while the bottom transistor behaves like an open circuit.

• Therefore, the supply voltage (5 V) appears at the output.

• Conversely, when a high voltage (5 V) is applied at the input, the bottom transistor (N-type) is conducting (switch closed) while the top transistor behaves like an open circuit.

• Hence, the output voltage is low (0 V).

• The function of this gate can be summarized by the following table:

Input Output

High Low

Low High

• The output is the opposite of the input - this gate inverts the input.

• Notice that always one of the transistors will be an open circuit and no current flows from the supply voltage to ground.

Fig: Transistor "switch model The switch model of the MOSFET transistor is defined as follows:

MOSFET Condition MOSFET State of MOSFET

NMOS Vgs<Vtn OFF

NMOS Vgs>Vtn ON

PMOS Vsg<Vtp OFF

PMOS Vsg>Vtp ON

When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging VOUT to logic high. When Vin is high, the NMOS is "on and the PMOS is "on: draining the voltage at VOUT to logic low.

Procedure -

• Open the blank project in orcade family release 9.1.

• Include library:-ANALOG, BIPOLAR, PWRMOS, SOURCE, TRANSISTOR

• .Draw the circuit.

• Go to pspice and open new simulation profile.

• Perform transient analysis.

• Create net list and then run.

• Then we obtain final waveform.

Net list description -

M_M1 N00263 N00282 0 0 M2N6659

V_V1 N00385 0 5Vdc

M_M2 N00263 N00282 N00385 N00385 M2N6806

V_V2 N00282 0

+PULSE 0 5 0 0 0 50ns 100ns

Circuit diagram-

Output waveform -

EXPERIMENT 02

Object - Transient and simulation analysis of NAND gate.

Software used- Orcade lite-9.1.

Theory-

• The circuit below has two inputs and one output. • Whenever at least one of the inputs is low, the corresponding P-type transistor will be

conducting while the N-type transistor will be closed. • Consequently, the output voltage will be high. Conversely, if both inputs are high,

then both P-type transistors at the top will be open circuits and both N-type transistors will be conducting.

• Hence, the output voltage is low.• The function of this gate can be summarized by the following table:

V1 V2 Output

Low Low High

Low High High

High Low High

High High Low

• If logical 1's are associated with high voltages then the function of this gate is called NAND for negated AND.

• Again, there is never a conducting path from the supply voltage to ground.

FIG 1: CMOS NAND GATE

CIRCUIT DIGGRAM:

NET LIST DESCRIPTION :

M_M1 N00147 N00915 0 0 M2N6659

M_M2 N00201 N01003 N00147 N00147 M2N6660

V_V1 N00278 0 5Vdc

V_V6 N00915 0

+PULSE 0 5 0 0 0 50ns 100ns

M_M4 N00201 N01003 N00278 N00278 M2N6849

V_V4 N01003 0

+PULSE 0 5 0 0 0 50ns 100ns

M_M5 N00201 N00915 N00278 N00278 M2N6845

OUTPUT WAVEFORM

EXPERIMENT 03

Object - Transient and simulation analysis of CMOS nor gate.

Software used- Orcade lite-9.1.

Theory-

• The circuit below has two inputs and one output.

• Whenever at least one of the inputs is high, the corresponding N-type transistor will be closed while the P-type transistor will be open.

• Consequently, the output voltage will be low.

• Conversely, if both inputs are low, then both P-type transistors at the top will be closed circuits and the N-type transistors will be open.

• Hence, the output voltage is high.

• The function of this gate can be summarized by the following table:

V1 V2 Output

Low Low High

Low High Low

High Low Low

High High Low

• If logical 1's are associated with high voltages then the function of this gate is called NOR for negated OR.

• Again, there is never a conducting path from the supply voltage to ground.

NOR Circuit and Standard Symbol

Circuit diagram:

Net list description -

M_M1 N00138 N00382 0 M2N6659

M_M2 N00138 N00310 0 0 M2N6659

V_V3 N00310 0

+PULSE 0 5 0 0 0 50ns 100ns

M_M3 N00107 N00310 N00569 N00569 M2N6806

V_V1 N00569 0 5Vdc

M_M4 N00138 N00382 N00107 N00107 M2N6806

V_V2 N00382 0

+PULSE 0 5 0 0 0 50ns 100ns

Output waveform -

EXPERIMENT 04

Object- Transient analysis and simulation of NMOS inverter.

Software used - orcade Lite-9.1.

Theory:nverter

Single transistor, pulls signal low

Inverter Operation

• Plus signal input turns transistor on

• Ground is connected to output

• Thus a 1 (+) in gives 0 (Ground) out

• A 0 input opens transistor and output is pulled high by resistor

• Resistor dissipates heat

• Asymmetric rise/fall times.

INPUT OUTPUT

A NOTA

0 1

1 0

NOT GATE

Circuit diagram -

Net list Description-

M_M1 N00063 N00343 0 0 M2N6659

R_R1 N00063 N00131 100

V_V2 N00343 0

+PULSE 0 5 0 0 0 50ns 100ns

V_V1 N00131 0 5Vdc

Output waveform

EXPERIMENT 05

Object - Transient analysis and simulation of bjt inverter.

Software used - orcade lite- 9.1.

Theory -

The voltage transfer characteristic of a BJT inverter (Fig. 1) is consisting of three regions, the cutoff

When vi is low, the active where the characteristic has a slope and the saturation region where the

Collector current is the maximum and the output voltage is low equal to VCEsat.

1. Cut-off region. 2. Forward Active region. 3. Saturation region.

BJT Inverter can be best expressed by its voltage transfer characteristic (VTC) or DC transfer characteristic. That relates the output voltage to the input one. If: 1) Vi = Vol, Vo = Voh = Vcc: (VTC) or DC Transfer Characteristic The transistor is OFF.

2) Vi = Vil: The transistor Begins to turn on.

3) Vil < Vi < Vih The transistor is in forward active region and operates as Amplifier.

4)Vi = Voh The transistor will be deep is saturation, Vo = Vce(sat).

Circuit diagram -

Netlist description -

Q_Q1 N00087 N00493 0 Q40235

R_R1 N00087 N00200 1k

V_V2 N00493 0

+PULSE 0 5 0 0 0 50ns 100ns

V_V1 N00200 0 5Vdc

Output waveform-

EXPRIMENT 06

OBJECT: Design of 4:1 multiplexer using “with” statement.

PROGRAM:

* design 4:1 mux using with statement.*library ieee;use ieee.std_logic_1164.all;entity mux4_1 isport (i0, i1, i2, i3: in std_logic;       s: in std_logic_vector(1 downto 0);        y: out std_logic);end mux4_1;architecture mux_with of mux4_1 issignal s: std_logic_vector(1 downto 0);begins <= s1 & s0;with s selecty <= i0 when s = "00";       i1 when s = "01";       i2 when s = "10";       i3 when s = "11";       'x' when others;end mux_with;

EXPERIMENT 07

OBJECT: design of 4:1 multiplexer using “when” statement

PROGRAM:

* design 4:1 mux using when statement.*library ieee;use ieee.std_logic_1164.all;entity mux4_1 isport (i0, i1, i2, i3: in std_logic; s: in std_logic_vector(1 downto 0); y: out std_logic);end mux4_1;architecture when_mux of mux4_1 isbeginy <= i0 when (s1 & s0) = "00" else; i1 when (s1 & s0) = "01" else; i2 when (s1 & s0) = "10" else; i3 when (s1 & s0) = "11" else; 'x'; end when_mux

EXPERIMENT 08

OBJECT: Design 4:1 mux using “case” statement

PROGRAM:

* design 4:1 mux using case statement.*library ieee;use ieee.std_logic_1164.all;entity mux4_1 isport (i0, i1, i2, i3: in std_logic; s: in std_logic_vector(1 downto 0); y: out std_logic);end mux4_1;architecture case_mux of mux4_1 isbeginprocess(s0, s1, i0, i1, i2, i3)variable sel: std_logic_vector(1 downto 0);beginsel:= s1 & s0;case sel iswhen "00" => y <= i0;when "01" => y <= i1;when "10" => y <= i2;when "11" => y <= i3;when others => y <= 'x';end case;end process;end case_mux;

EXPERIMENT 09

OBJECT: Design D flip-flop with “reset using VHDL”.

PROGRAM:

* design D flip-flop with reset using VHDL.*library ieee;use ieee.std_logic_1164.all;entity dff isport(d, clk, reset, set: in std_logic;      q: out std_logic);end dff;architecture dff_res of dff isbeginprocess(clk)beginif clk'event and clk='1' thenif reset='1' thenq <= '0';elsif set='1' thenq <= '1';elseq <= 'd';end if;end if;end process;end dff_res;

EXPERIMENT 10

OBJECT: Design full adder using half adder for structural modelling.

PROGRAM:

*design full adder using half adder for structural modelling.*library ieee;use ieee.std_logic_1164.all;entity fa isport(a, b, cin: in std_logic;     s, cout: out std_logic);end fa;architecture fa_struct of fa iscomponent haport(a, b: in std_logic;     s, c: out std_logic);end component;component orport(a, b: in std_logic;      y: out std_logic);end component;signal i1, i2, i3: std_logic;beginha1: ha port map(a, b, i2, i1);ha2: ha port map(i2, cin, s, i3);or1: or port map(i1, i3, cout);end fa_struct;

EXPERIMENT 11

OBJECT: Design of 4-bit ripple carry adder using full adder as a component for structural modelling.

PROGRAM:

*design of  4-bit ripple carry adder using full adder as a component forstructural modelling.*library ieee;use ieee.std_logic_1164.all;entity rca_4-bit isport(a, b: in std_logic_vector(3 downto 0);     cin: in std_logic;      s: out std_logic_vector(3 downto 0);      cout: out std_logic);end rca_4-bit;architecture rca_4-bit_struct of rca_4-bit issignal c: std_logic_vector(2 downto 0);component fa isport(a, b, cin: in std_logic;      s, cout: out std_logic);end component;beginfa1: fa port map(a(0), b(0), cin, s(0), c(0));fa2: fa port map(a(1), b(1), c(0), s(1), c(1));fa3: fa port map(a(2), b(2), c(1), s(2), c(2));fa4: fa port map(a(3), b(3), c(2), s(3), cout);end rca_4-bit_struct;