EE315 Lecture2 DiffMultAmp v 301

THE DIFFERNTIAL AND MULTISTAGE AMPLIFIERS

Fig. 6.1: The Basic BJT Differential-Pair Configuration

Although each collector is connected to the positive supply voltage Vcc

through a resistance Rc, this connection is not essential to the operation of

the differential pair-that is, in some applications the two collectors may be

connected to other transistors rather than to resistive loads.

It is essential, though, that the collector circuits be such that Ql and Q2 never

enter saturation.

Consider first the case where the two bases are joined together and

connected to a voltage VCM, called the common-mode voltage.

Since Ql and Q2 are matched, it follows from symmetry that the current I

will divide equally between the two devices.

Thus, iE1 = iE2 = I/2, and the voltage at the emitters will be vCM - VBE, where

VBE is the base-emitter voltage (assumed to be approx. 0.7 V) corresponding

to an emitter current of I/2.

The voltage at each collector will be Vcc - ½ αIRc, and the difference in

voltage between the two collectors will be zero.

Now let us vary the value of the common-mode input signal VCM.

Obviously, as long as Ql and Q2 remain in the active region the current I will

still divide equally between Ql and Q2, and the voltages at the collectors will

not change. Thus the differential pair does not respond to (that is, it rejects)

common-mode input signals.

As another experiment, let the voltage vB2 be set to a constant value, say,

zero, and let vB1 = +1 V.

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With a bit of reasoning it can be seen that Q l will be on and conducting all

of the current I and that Q2 will be off.

For Q1 to be on, the emitter has to be at approximately +0.3 V; which keeps

the EBJ of, Q2 reverse- biased.

vC1 = Vcc - αIRc and vC2 = Vcc.

Now change vB1 to -1 V.

Again it can be seen that Q1 will turn off, and Q2 will carry all the current I.

The common emitter will be at -0.7 V, which means that the EBJ of Ql will

be reverse-biased by 0.3 V.

vC1 = Vcc and vC2 = Vcc. - αIRc

Thus the differential pair responds to difference-mode or differential

signals.

In fact, with relatively small difference voltages we are able to steer the

entire bias current from one side of the pair to the other.

This current-steering property of the differential pair allows it to be used in

logic circuits, as will be demonstrated later.

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To use the differential pair as a linear amplifier we apply a very small

differential signal (a few millivolts), which will result in one of the

transistors conducting a current of I/2+I; the current in the other transistor

will be I/2-I, with I being proportional to the difference input voltage.

The output voltage taken between the two collectors will be 2α IRc, which

is proportional to the differential input signal vi.

LARGE-SIGNAL OPERATION OF THE BJT DIFFERENTIAL PAIR

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If the voltage of the common emitter be vE then,

The collector currents can be obtained simply by multiplying the emitter

currents in Eqs. (6.7) and (6.8) by α, which is normally very close to unity.

The fundamental operation of the differential amplifier is illustrated by Eqs.

(6.7) and (6.8). First, note that the amplifier responds only to the difference

voltage vB1 - vB2. That is, if vB1 = vB2 = vCM, the current I divides equally

between the two transistors. This is the essence of differential- amp.

operation, which also gives rise to its name.

Another important observation is that a relatively small difference voltage

vB1 - vB2 will cause the current I to flow almost entirely in one of the two

transistors.

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Figure above shows a plot of the two collector currents (assuming α 1) as

a function of the difference signal. This is a normalized plot that can be used

universally.

Note that a difference voltage of about 4VT (= 100 mV) is sufficient to

switch the current almost entirely to one side of the pair.

The fact that such a small signal can switch the current from one side of the

differential pair to the other means that the differential pair can be used as a

fast current switch.

Another reason for the high speed of operation of the device as a switch is

that none of the transistors saturates.

A saturated transistor stores charge in its base that must be removed before

the device can turn off - generally a slow process.

The absence of saturation in the differential pair makes the logic family

based on it the fastest form of logic circuits available.

For application of the differential pair as a small-signal amplifier, the

difference input signal is limited to less than about VT/2 in order that we

operate on a linear segment of the characteristics around the midpoint x.

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SMALL SIGNAL OPERATION OF BJT DIFFERENTIAL AMPLIFIER

Since vB1 - vB2 = vd,

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It may be seen that when vd = 0, the bias current I divides equally between

the two transistors of the pair.

Thus each transistor is biased at an emitter current of I/2.

When a small-signal current is applied differentially, collector current of Q1

increases by an increment ic and that of Q2 decreases by an equal amount.

This ensures that the sum of the total currents in Q1 and Q2 remains constant

as constrained by the current-source bias.

The incremental or signal current component ic is given by

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An Alternative Viewpoint

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This method of analysis is particularly useful when resistances are included

in the emitters as shown below:

For this circuit:

INPUT DIFFERENTIAL RESISTANCE

The input differential resistance is the resistance seen between the two bases; that is, it

is the resistance seen by the differential input signal vd.

For the differential amplifier it can be seen that the base current of Q1 shows an

increment ib and the base current of Q2 shows an equal decrement,

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This result is just a restatement of the familiar resistance-reflection rule;

namely, the resistance seen between the two bases is equal to the total

resistance in the emitter circuit multiplied by β+1. We can employ this rule

to find the input differential resistance for the circuit as:

DIFFERENTIAL VOLTAGE GAIN

We have established that for small difference input voltages (vd 2VT; that is, vd

smaller than about 20 mV) the collector currents are given by:

The output voltage signal of a differential amplifier can be taken either

differentially (that is, between the two collectors) or single-ended (that-is,

between one collector and ground).

If the output is taken differentially, then the differential gain (as opposed to

the common-mode gain) of the differential amplifier will be:

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On the other hand, if we take the output single-endedly (say, between the

collector of Ql and ground), then the differential gain will be given by:

For the differential amplifier with resistances in the emitter leads (Fig. 6.6)

the differential gain when the output is taken differentially is given by:

Equivalence of the Differential amplifier to a Common-Emitter Amplifier

The above analysis and results are quite similar to those obtained in the case

of a common-emitter amplifier stage.

That the differential amplifier is in fact equivalent to a common- emitter

amplifier is illustrated in Fig. 6.7 below.

Fig. 6.7

Fig. (a) shows a diff. amplifier fed by a differential signal vd applied in a

complementary (push- pull or balanced) manner. 13

That is, while the base of Ql is raised by vd/2, that of Q2 is lowered by vd/2.

We have also included the output resistance R of the bias current source.

From symmetry, it follows that the signal voltage at the common emitter

will be zero. Thus the circuit is equivalent to the two common-emitter

amplifiers shown in Fig. (b). where each of the two transistors is biased at

an emitter current of I/2.

Note that the finite output resistance R of the current source will have no

effect on the operation.

The equivalent circuit in Fig. (b) is valid for differential operation only.

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In many applications the differential amplifier is not fed in a complementary

fashion; rather, the input signal may be applied to one of the input terminals

while the other terminal is grounded, as shown Fig. below.

In this case the signal voltage at the emitters will not be zero, and thus the

resistance R will have an effect on the operation.

Nevertheless, if R is large (R >> re), as is usually the case, then vd will still

divide equally (approximately) between the two junctions, as shown above.

Thus the operation of the differential amplifier in this case will be almost

identical to that in the case of symmetric feed, and the common-emitter

equivalence can still be employed.

Since in Fig. 6.7, vc2 = -vc1, the two common-emitter transistors in Fig.

6.7(b) yield similar results about the performance of the differential

amplifier.

Thus only one is needed to analyze the differential small-signal operation of

the differential amplifier, and is known as the differential half-circuit.

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If we take the common-emitter transistor fed with +vd/2 as the differential

half circuit and replace the transistor with its low-frequency equivalent

circuit model, the circuit in Fig. 6.9 results:

In evaluating the values of the model parameters r, gm and r0, we must

recall that the half-circuit is biased at I/2.

The voltage gain of the differential amplifier (with the output taken

differentially) is equal to the voltage gain of the half-circuit – that is ,

vc1/(vd/2).

Here, we note that including r0 will modify the gain expression to:

Ad = - gm(RC r0)

The input differential resistance of the differential amplifier is twice that of

the half-circuit ─ that is 2r.

Finally we note that the differential half-circuit of the amplifier is a

common-emitter transistor with a resistance RE in the emitter lead.

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Common – Mode gain

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Input Common-Mode Resistance

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EXAMPLE 6.1

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SOLUTION

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BIASING IN BJT INTEGRATED CIRCUITS

The BJT biasing techniques discussed earlier are not suitable for the design

of IC amplifiers.

This shortcoming stems from the need for a large number of resistors (one

to three per amplifier stage) as well as large coupling and bypass capacitors.

With present IC technology it is almost impossible to fabricate large

capacitors, and it is uneconomical to manufacture large resistances.

On the other hand, IC technology provides the designer with the possibility

of using many transistors, which can be produced cheaply.

Furthermore, it is easy to make transistors with matched characteristics that

track with changes in environmental conditions.

The limitations of, and opportunities available in, IC tech. dictate a biasing

philosophy, quite different from that employed in discrete BJT amplifiers.

Biasing in IC design is based on the use of constant-current sources.

We have already seen that the differential pair utilizes constant-current-

source bias.

On an IC chip with a number of amplifier stages, a constant dc current is

generated at one location and is then reproduced at various other locations

for biasing the various amplifier stages.

The advantage is that the bias currents of the various stages track each other

in case of changes in power-supply voltage or in temperature.

We shall now study a variety of current-source and current-steering circuits.

Although these circuits can be used in discrete-unit design, they are

primarily intended for application in IC design.

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The bipolar current-source and current-steering circuits are quite similar to

those implemented with MOS transistors.

THE DIODE CONNECTED TRANSISTOR

Shorting the base and collector of a BJT together results in a two-terminal

device having an i-v characteristic identical to the iE-vBE characteristic of the

BJT.

Figure 6.14 shows two diode-connected transistors, one npn and the other

pnp.

Observe that since the BJT is still operating in the active mode (vCB = 0

results in active-mode operation) the current i divides between base and

collector according to the value of the BJT β, as indicated in Fig. 6.14.

Thus, internally the BJT still operates as a transistor in the active mode.

This is the reason the i-v characteristic of the resulting diode is identical to

the iE-vBE relationship of the BJT.

It can be shown (Exercise 6.5) that the incremental resistance of the diode-

connected transistor is approximately equal to re.

In the following we shall make extensive use of the diode-connected BJT.

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THE CURRENT MIRROR

The current mirror, shown below in its simplest form is the most basic

building block in the design of IC current sources and current-steering

circuits.

The current mirror consists of two matched transistors with their bases

and emitters connected together, and which thus have the same vBE.

In addition, Q1 is connected as a diode by shorting its collector to its base.

The current mirror is shown fed with a constant-current source IREF, and the

output current is taken from the collector of Q2.

The circuit fed by the collector of Q2 should ensure active-mode operation

for Q2 (by keeping its VC higher than VB) at all times.

Assume that the BJTs have high β, and thus their base currents are

negligibly small.

The input current IREF flows through the diode-connected transistor Q1 and

thus establishes a voltage across Q1 that corresponds to the value of IREF.

This voltage in turn appears between the base and emitter of Q2. Since Q2 is

identical to Q1, the emitter current of Q2 will be equal to IREF. 26

It follows that as long as Q2 is maintained in the active region, its collector

current IO will be approximately equal to IREF.

Note that the mirror operation is independent of the value of the voltage -

VEE as long as Q2 remains active.

Next, we consider the effect of finite transistor β on the operation of the

current mirror.

The analysis proceeds as follows: Since Q1 and Q2 are matched and since

they have equal vBE, their emitter currents will be equal. This is the key

point. The rest of the analysis is straightforward.

It follows that:

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which approaches unity for β >> 1.

Note, however, that the deviation of current gain from unity can be

relatively high:

β = 100 results in a 2% error.

Another factor that makes IO unequal to IREF is the linear dependence of the

collector current of Q2, which is IO, on the collector voltage of Q2.

In fact, even if we ignore the effect of finite β and assume that Q1 and Q2

are perfectly matched, the current IO will be equal to IREF only when the

voltage at the collector of Q2 is equal to the base voltage.

As the collector voltage is increased, IO increases. Since Q2 is operated at a

constant vBE (as determined by IREF) the dependence of IO on Vo is

determined by ro of Q2.

In other words, the output resistance of this current mirror is equal to ro of

Q2.

Taking the effect of finite β and the Early effect:

Note that the term representing the Early effect has been written so that it

reduces to zero when vCB of Q2 is zero (as is vCB of Q1), in which case IO

differs from IREF only by the factor due to finite β.

A SIMPLE CURRENT SOURCE

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This circuit utilizes a pair of matched transistors in a current-mirror

configuration, with the input reference current to the mirror, IREF,

determined by a resistor R connected to the positive power supply Vcc.

VBE is the base-emitter voltage corresponding to an emitter current IREF.

Neglecting the effect of finite β and the dependence of IO on VO, the output

current IO will be equal to IREF.

The circuit will operate as a constant-current source as long as Q2 remains

in the active region ─ that is, for VO VBE.

The output resistance of this current source is ro of Q2.

Taking the finite β and the Early effect into account, the output current can

be obtained by combining Eqs. (6.64) and (6.65) and substituting VEE = 0.

CURRENT-STEERING CIRCUITS

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As mentioned earlier, in an IC a dc reference current is generated in one

location and is then reproduced at other locations for the purpose of biasing

the various amplifier stages in the IC.

As an example consider the circuit shown in Fig. 6.18.

The circuit utilizes two power supplies, VCC and - VEE.

The dc ref. current IREF is generated in the branch that consists of the diode-

connected transistor Q1, resistor R and diode –connected transistor Q2:

Now, for simplicity, assume that all transistors have high β and thus the

base currents are negligibly small.

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Diode-connected transistor Q1 forms a current mirror with Q3. Thus Q3 will

supply a constant current I1 equal to IREF.

Transistor Q3 can supply this current to any load as long as the voltage that

develops at the collector does not exceed that at the base (VCC - VEB3).

To generate a dc current twice the value of IREF, two transistors Q5 and Q6

are connected in parallel, and the combination forms a mirror with Q1.

Thus I3 = 2 IREF.

Note that the parallel combination of Q5 and Q6 is equivalent to a transistor

whose EBJ area is double that of Q1, which is precisely what would be done

if this circuit were to be fabricated in IC form.

Current mirrors are indeed used to provide multiples of the reference

current by simply designing the transistors to have an area ratio equal to the

desired multiple. This is somewhat different than in the case of a MOS

mirror where the current transfer ratio is determined by the ratio of the W/L

ratios of the two transistors and not by the device areas.

Transistor Q4 forms a mirror with Q2, and thus Q4 provides a constant

current I2 equal to IREF.

Note an important difference between Q3 and Q4: Although both supply

equal currents, Q3 sources its current to parts of the circuit whose voltage

should not exceed VCC - VEB3. On the other hand, Q4 sinks its current from

parts of the circuit whose voltage should not decrease below -VEE + VBE4.

Finally, to generate a current three times the reference, three transistors Q7,

Q8, and Q9 are paralleled and the combination placed in a mirror

configuration with Q2.

Again, in an IC implementation, Q7, Q8, and Q9 would be replaced with a

transistor having a junction area three times that of Q2.

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The above description ignored the effects of the finite transistor β. We have

analyzed this effect in the case of a mirror having a single output.

The effect of finite β becomes more severe as the number of outputs of the

mirror is increased. This is not surprising since the addition of more

transistors means that their base currents have to be supplied by the

reference current source.

IMPROVED CURERNT-SOURCE CIRCUITS

Two performance parameters of the BJT current source need improvement.

The first is the dependence of IO on β, which is a result of the error in the

mirror current-gain introduced by the finite BJT β.

The second is the output resistance of the current source, which was found

to be equal to the BJT ro and thus limited to the order of 100 kΩ.

The need to increase the current-source output resistance can be seen if we

recall that the common-mode gain of the differential amplifier is directly

determined by the output resistance of its biasing current source.

Also, it has been seen that the BJT current sources are usually used in place

of the load resistances RC of the differential amplifier.

Thus, to obtain high voltage gain, a large output resistance is required.

We shall now discuss several circuit techniques that result in reduced

dependence on β and/or increased output resistance.

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The first circuit, shown in Fig. 6.19, includes a transistor Q3 whose emitter

supplies the base currents of Q1 and Q2.

The sum of the base currents is then divided by (β + 1) of Q3, resulting in a

much smaller current that has to be supplied by IREF.

Detailed analysis, is based upon the assumption that Q1 and Q2 are matched

and thus have equal emitter currents, IE.

A node equation at the node labeled x gives:

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Our final current-source circuit, known as the Widlar current source, is

shown in Fig. 6.21.

It differs from the basic current mirror circuit in an important way: A

resistor RE is included in the emitter lead of Q2.

THE BJT DEFFERENTIAL AMPLIFIER WITH ACTIVE LOAD

Active devices (transistors) occupy much less silicon area than medium and

large-sized resistors. For this reason, many practical BJT integrated-circuit

(IC) amplifiers use BJT loads in place of the resistive loads, RC.

In such circuits the BJT load transistor is usually connected as a constant-

current source and thus presents the amplifier transistor with a very-high-

resistance load (the output resistance of the current source).

Thus amplifiers that utilize active loads can achieve higher voltage gains

than those with passive (resistive) loads.

We now study a circuit configuration that has become very popular in the

design of BJT ICs.

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The active-load differential amplifier circuit is shown in Fig. 6.25 below.

Transistors Q1 and Q2 form a differential pair biased with constant current I.

The load circuit consists of transistors Q3 and Q4 connected in a current-

mirror configuration.

The Output is taken single-endedly from the collector of Q2.

Consider first the case when no input signal is applied (that is, the two input

terminals are grounded).

The current I splits equally between Q1 and Q2. Thus Q1 draws a current of

approximately I/2 from the diode-connected transistor Q3.

Assuming β >> 1, the mirror supplies an equal current I/2 through the

collector of Q4.

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Since this current is equal to that through the collector of Q2, no output

current flows through the output terminal.

It should be noted, that in practical circuits the dc quiescent voltage at the

output terminal is determined by the subsequent amplifier stage.

Next, consider the situation when a differential signal vd is applied at the

input.

Current signals gm(vd/2) will result in the collectors of Q1 and Q2 with the

polarities indicated in Fig. 6.25.

The current mirror reproduces the current signal gm(vd/2) through the

collector of Q4.

Thus, at the output node we have two current signals that add together to

produce a total current signal of (gmvd).

Now if the resistance presented by the subsequent amplifier stage is very

large, the voltage signal at the output terminal will be determined by the

total signal current (gmvd) and the total resistance between the output

terminal and ground, Ro; that is,

vo = gmvd Ro

The output resistance Ro is the parallel equivalent of the output resistance of

Q2 and the output resistance of Q4.

Since Q2 is in effect operating in the common-emitter configuration, its

output resistance will be equal to ro2.

Also, from our study of the basic current mirror circuit in the previous

section we know that its output resistance is equal to ro of Q4 ─ that is, ro4.

Thus,

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which is a constant for a given transistor.

Typically, VA = 100 V; leading to gmro = 4000 and a stage voltage gain of

about 2000.

In some cases the input resistance of the subsequent amplifier stage may be

of the same order as Ro and thus must be taken into account in determining

voltage gain.

In such situations it is convenient to represent the amplifier of Fig. 6.25 by

the transconductance amplifier model shown in Fig. 6.26.

Here Ri is the differential input resistance, for our case Ri = 2r . The

amplifier transconductance Gm is the short-circuit transconductance, and for

our case

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Gm = gm = I /2V T

Finally Ro is the resistance given by Eq. 6.81.

In order to obtain yet higher voltage gains, current-mirror circuits with

higher output resistances, such as the Wilson mirror, can be utilized.

Also, the basic differential amplifier configuration can be modified to

increase the output resistance of Q2.

One such modification involves the use of a circuit arrangement known as

the cascode configuration.

It is important to observe the role that the current Mirror circuit in Fig. 6.25

plays:

It inverts the current signal gm(vd/2) supplied by the collector of Q1. and

provides an equal Current at the collector of Q4 with such a polarity that it

adds to the current signal in the collector of Q2.

Without the current mirror (that is, using only a simple current-source) the

voltage gain would be half the value found above.

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MULTISTAGE AMPLIFIERS

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A multistage amplifier is shown in the figure.

The circuit consists of four stages. The input stage is

differential-in, differential out and consists of transistors Q1,

and Q2, which are biased by current source Q3.

The second stage is also a differential-input amplifier, but its

output is taken single-endedly at the collector of Q5.

This stage is formed by Q4 and Q5, which are biased by the

current source Q6.

Note that the conversion from differential to single-ended as

performed by the second stage results in a loss of gain by a factor

of 2.

A more elaborate method for accomplishing this conversion,

using a current mirror as active load is also used.

In addition to providing some voltage gain, the third stage,

consisting of th epnp transistor Q7.

It provides the essential function of shifting the dc level of the

signal.

Thus while thi signal at the collector of Q5 is not allowed to

swing below the voltage at the base of Q5 (+10V), the signal at

the collector of Q7 can swing negatively (and positively, of

course).

From our study of Op-Amp, we know that the output terminal of

the op amp should be capable of both positive and negative

voltage swings.

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Therefore every op-amp circuit includes a level-shifting

arrangement.

Although the use of the complementary pnp transistor provides a

simple solution to .the level-shifting problem, other forms of

level shifter exist.

The output stage of .the op amp consists of emitter follower Q8.

As we know from our study of Op Amps, .the output operates

ideally around zero volts.

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