ee260 2018 spring materials week 10 slides b - s3-us-west ... · Magnitude Comparators : 30 A ... Chapter 6-8: Combinational Datapath 6 Equality Comparators n1-bit ......

EE260: Digital Design, Spring 2018 3/16/18

Chapter 6-8: Combinational Datapath 1

EE 260: Introduction toDigital Design

Combinational Datapath

Yao ZhengDepartment of Electrical Engineering

University of Hawaiʻi at Mānoa

Overviewn Combinational Logic Blocksn Multiplexern Encoders/Decodersn Priority Encodersn Three-State Buffersn Parity Functionsn Comparatorsn Adders/Subtractorsn Multipliers/Dividersn Shiftersn Memory/Cache

Canonical and Standard Formsn We need to consider formal techniques for

the simplification of Boolean functions.n Minterms and Maxtermsn Sum-of-Minterms and Product-of-Maxtermsn Product and Sum termsn Sum-of-Products (SOP) and Product-of-Sums

(POS)

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Karnaugh Mapsn Karnaugh maps (K-maps) are graphical

representations of boolean functions.n One map cell corresponds to a row in the

truth table.n Also, one map cell corresponds to a

minterm or a maxterm in the booleanexpression

n Multiple-cell areas of the map correspond to standard terms.

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Two-Variable Map

m3m21

m1m00

10x1x2

0 1

2 3

n NOTE: ordering of variables is IMPORTANT for f(x1,x2), x1 is the row, x2 is the column.

n Cell 0 represents x1’x2’; Cell 1 represents x1’x2; etc. If a minterm is present in the function, then a 1 is placed in the corresponding cell.

m3m11

m2m00

10x2x1

0 2

1 3OR

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Two-Variable Map (cont.)n Any two adjacent cells in the map differ by

ONLY one variable, which appears complemented in one cell and uncomplemented in the other.

n Example:m0 (=x1’x2’) is adjacent to m1 (=x1’x2) and m2 (=x1x2’) but NOT m3 (=x1x2)

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Simplificationn Enter minterms of the Boolean function

into the map, then group termsn Example: f(a,b,c) = a’c + abc + bc’n Result: f(a,b,c) = a’c + b

1 1 11 1

abc

1 1 11 1

0

10

1

7

Eliminating static hazardsn Key idea: Glitches happen when a changing

input spans separate K-map encirclementsn Example: 1101 to 0101 change can cause a static-1

glitch

0 0 1 1

1 1 1 1

1 1 0 0

0 0 0 0

ABCD

B

D

00 01 11 1000

01

11

10C

A

Combinational Logic Blocksn With K‐map, you can build any combinational functions

you want, but not everything should be build from K‐mapn Minimum SOP/POS is not always globally “optimum”n Some functions have special structures to be taken advantage

of n Some functions are so frequently used they have become

conventionsn Major examples

n Multiplexern Encoders/decodersn Arithmetic: adders, subtractors, multipliers, dividers, etc.n Logic: shiftersn Memory: ROM, RAM

Multiplexern “Selects” binary information from one of many

input lines and directs it to a single output line.n Also know as the “selector” circuit,n Selection is controlled by a particular set of

inputs lines whose # depends on the # of the data input lines.

n For a 2n-to-1 multiplexer, there are 2n data input lines and n selection lines whose bit combination determines which input is selected.

2-to-1-Line Multiplexern Since 2 = 21, n = 1n The single selection variable S has two values:

n S = 0 selects input I0n S = 1 selects input I1

n The equation:Y = S’ I0 + SI1

n The circuit:

S

I0

I1

DecoderEnablingCircuits

Y

Implementing Boolean functions with Multiplexers

n Any Boolean function of n variables can be implemented using a 2n-1-to-1 multiplexer. A MUX is basically a decoder with outputs ORed together, hence this isn’t surprising.

n The SELECT signals generate the minterms of the function.

n The data inputs identify which minterms are to be combined with an OR.



Example•F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7)•There are n=3 inputs, thus we need a 22-to-1 MUX•The first n-1 (=2) inputs serve as the selection lines

Decodersn A combinational circuit that converts

binary information from n coded inputs to a maximum 2n coded outputs à n-to- 2n decoder

n n-to-m decoder, m ≤ 2n

n Examples: BCD-to-7-segment decoder, where n=4 and m=10

1-2 Decoder

n Any combinational circuit can be constructed using decoders and OR gates! Why?

n Here is an example:Implement a full adder circuit with a decoder and two OR gates.

n Recall full adder equations, and let X, Y, and Z be the inputs:n S(X,Y,Z) = X+Y+Z = Sm(1,2,4,7) n C (X,Y,Z) = Sm(3, 5, 6, 7).

n Since there are 3 inputs and a total of 8 minterms, we need a 3-to-8 decoder.

Implementing Boolean functions using decoders

Implementing a Binary Adder Using a Decoder

S(X,Y,Z) = SUM m(1,2,4,7)

C(X,Y,Z) = SUM m(3,5,6,7)

Encodersn An encoder is a digital circuit that

performs the inverse operation of a decoder. An encoder has 2n input lines and n output lines.

n The output lines generate the binary equivalent to the input line whose value is 1.



Encoder Examplen Example: 8-to-3 binary encoder (octal-to-binary)

A0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7A2 = D4 + D5 + D6 + D7

Encoder Design Issuesn There are two ambiguities associated with the

design of a simple encoder:1. Only one input can be active at any given time. If

two inputs are active simultaneously, the output produces an undefined combination (for example, if D3 and D6 are 1 simultaneously, the output of the encoder will be 111.

2. An output with all 0's can be generated when all the inputs are 0's,or when D0 is equal to 1.

Priority Encodersn Solves the ambiguities mentioned above.n Multiple asserted inputs are allowed; one

has priority over all others.n Separate indication of no asserted inputs.

Example: 4-to-2 Priority EncoderTruth Table

Example: 4-to-2 Priority EncoderK-Maps

Buffersn The number of circuit inputs that can be driven

by a single output is limitedn If a circuit output must drive many inputs, we

use buffers to increase the driving capabilityn Buffers does not perform any logic function, i.e.

its logic equation is F=C. n It only increases the driving capability



Three-state buffers

n Output = LOW, HIGH, or Hi-Z.

lCan tie multiple outputs together, if at most one at a time is driven.

Logic values for buses signals

S2X 0 1 Z

S1

X X X X X0 X 0 X 01 X X 1 1Z X 0 1 Z

Table 1: Logic values for bus signals and the resulting value when they are connected together

Circuit with tri-state buffers

Exclusive-OR (XOR) Functionn XOR (also Å) : the “not-equal” functionn XOR(X,Y) = X Å Y = X’Y + XY’n Identities:

n X Å 0 = Xn X Å 1 = X’n X Å X = 0n X Å X’ = 1

n Properties:n X Å Y = Y Å X n (X Å Y) Å W = X Å ( Y Å W)

Parity Functionsn Odd Parity Circuit : The output is 1 if odd number of inputs are 1n Even Parity Circuit : The output is 1 if even number of inputs are 1n Example : 4-bit Parity Circuit

Daisy-Chain Structure Tree structure

Input : 1101 Odd Parity output : 1Even Parity output : 0

28

I0

I1

I2

I3ODD

EVEN I0

I1

I2

I3

ODD

EVEN

Parity-Checking Application: memory

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Comparators

n Compares Two binary words and indicate if they are equal

Magnitude Comparators :

30

AComparator A=B?

B

AComparator

A=B

BA>B A<B



Equality Comparators

n 1-bit comparator

31

l4-bit comparator

EQ_L

Iterative Comparator

32

Half Addern Performs 1-bit addition. n Inputs: A0, B0

n Outputs: S0, C1

n Index indicates significance, 0 is for LSB and 1 is for the next higher significant bit.

n Boolean equations:n S0 = A0B0’+A0’B0 = A0 Å B0

n C1 = A0B0

A0 B0 S0 C1

0 0 0 00 1 1 01 0 1 01 1 1 1

Truth Table

Full Addern Full adder (for higher-order bit addition)n Combinational circuit that performs the

additions of 3 bits (two bits and a carry-in bit)

1 bitfull adder

Ai Bi

Ci+1

Si

Ci

Full Adder (cont.)

Ai Bi Ci Si Ci+1

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

n The K-maps forn Ci+1:

n Si:

11100100

BiCiAi

01011010

BiCiAi

n-bit Combinational Addersn Perform parallel multi-bit additionn Ripple Carry Adder

n Simple designn Time consuming. Why? (you’ll see in a bit!)

n Carry Lookahead Addern More complex than ripple-carry addern Reduces circuit delay



n-bit Ripple Carry Adder

n Constructed using n 1-bit full adder blocks in parallel.

n Cascade the full adders so that the carry out from one becomes the carry in to the next higher bit position.

Carry Lookahead Addern From a FA, separate between carry generation (a new carry

signal is generated, i.e. Cout=1) and carry propagation (an existing Cin is propagated to Cout)

n Generate: Gi = AiBi: if 1, Ci+1=1n Propagate: Pi = Ai Å Bi: if true, Ci+1 = Ci

Partial Full Adder (PFA)Full Adder (FA)

Bi

Bi Ai

Ci Ci

Ci+1

Si

Si Gi Pi

Ai

4-bit Binary Adder/Subtractor

–XOR gates act as programmable inverters

Multiplication

n Flashback to 3rd graden Multipliern Multiplicandn Partial productsn Final sum

n Base 10: 8 x 9 = 72n PP: 8 + 0 + 0 + 64 = 72

n How wide is the result?n log(n x m) = log(n) + log(m)n 32b x 32b = 64b result

1 0 0 0

x 1 0 0 1

1 0 0 0

0 0 0 0

0 0 0 0

1 0 0 0

1 0 0 1 0 0 0

Array Multipliern Adding all partial

products simultaneously using an array of basic cells

1 0 0 0

x 1 0 0 1

1 0 0 0

0 0 0 0

0 0 0 0

1 0 0 0

1 0 0 1 0 0 0

Full Adder

Sin Cin Ai Bj

Cout Sout

Ai ,Bj

Multiplier

Control testWrite

32 bits

64 bits

Shift rightProduct

Multiplicand

32-bit ALU

1 0 0 0x 1 0 0 11 0 0 0

0 0 0 00 0 0 0

1 0 0 01 0 0 1 0 0 0



Booth’s Encodingn Search for a run of ‘1’ bits in the multiplier

n E.g. ‘0110’ has a run of 2 ‘1’ bits in the middlen Multiplying by ‘0110’ (6 in decimal) is equivalent to

multiplying by 8 and subtracting twice, since 6 x m = (8 – 2) x m = 8m – 2m

n Hence, iterate right to left and:n Subtract multiplicand from product at first ‘1’n Add multiplicand to product after last ‘1’n Don’t do either for ‘1’ bits in the middle

Integer Division

n Again, back to 3rd grade (74 ÷ 8 = 9 rem 2)1 0 0 1 Quotient

Divisor 1 0 0 0 1 0 0 1 0 1 0 Dividend

- 1 0 0 0

1 0

1 0 1

1 0 1 0

- 1 0 0 0

1 0 Remainder

Divider

Write

32 bits

64 bits

Shift leftShift right

Remainder

32-bit ALU

Divisor

Control test

Logical Operationsn Bitwise AND, OR, XOR, NOR

n Implement w/ 32 gates in paralleln Shifts and rotates

n rol => rotate left (MSB->LSB)n ror => rotate right (LSB->MSB)n sll -> shift left logical (0->LSB)n srl -> shift right logical (0->LSB)n sra -> shift right arithmetic (old MSB->new MSB)

Memory: ROMn Input: an n-bit addressn Output: data of width w stored at location

ROM[addr] (2^n such locations)n Since it is read-only, the ROM’s contents

have to be initialized by an offline process

Memory: RAMn If you just read the memory, memory is

combinationaln The same address always returns the same answern It is equivalent to an n-input combinational function,

each address is a minterim



Memory Hierarchy

• Capacity: Register << SRAM << DRAM• Latency: Register << SRAM << DRAM• Bandwidth: on-chip >> off-chip• On a data access:

– if data is in fast memory -> low-latency access to SRAM– if data is not in fast memory -> long-latency access to DRAM

• Memory hierarchies only work if the small, fast memoryactually stores data that is reused by the processor

Small FastMemory(RF, SRAM)

ProcessorBig SlowMemory(DRAM)

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Combinational Datapathn All digital systems comprise

n Input and outputn Combinational stuff that computes a function

(has no memory)n Sequential stuff that remembers (upcoming)

ee260 2018 spring materials week 10 slides b - s3-us-west ... · Magnitude Comparators : 30 A ... Chapter 6-8: Combinational Datapath 6 Equality Comparators n1-bit ......

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