EE241 - Spring 2000bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s00/... · EE241 6 UC Berkeley EE241 B. Nikolic Slack Borrowing l L1 phase time is from the falling edge of C2 to

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UC Berkeley EE241 B. Nikoli c

EE241 - Spring 2000Advanced Digital Integrated Circuits

Lecture 22

Latch-Based Timing

UC Berkeley EE241 B. Nikoli c

Single-Latch Timing

Latch

Logic

φ LMQMD

QMclkSUsktsklT

T

PWTTTTP +

−+++

≥−

− ,max

QmClkHsktsklLm TPWTTTT −−+++≥

Bounds on logic delay:

Either balance logic delaysor make PW short

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UC Berkeley EE241 B. Nikoli c

Latch-Based Design

L1Latch Logic

Logic

L2Latch

φ

L1 latch is transparentwhen φ = 0

L2 latch is transparent when φ = 1

UC Berkeley EE241 B. Nikoli c

Latch-Based Timing

L1Latch Logic

Logic

L2Latch

φ

φ = 1

φ = 0

L1 latch

L2 latch

Skew

Can tolerate skew!

Longpath

Shortpath

Static logic

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UC Berkeley EE241 B. Nikoli c

Latches with Dynamic Logic

φ = 0

φ = 1

L2 latchL1 latch

Shortpath

Clock evaluates logicand opens subsequent latch:

Static signals driving dynamiclogic must be eithernon-inverting orstable before evaluation

N-dominoprecharges

P-dominoevaluates

N-dominoevaluates

P-dominoprecharges

UC Berkeley EE241 B. Nikoli c

Latches with Dynamic Logic

φ = 1

φ = 0

L2 latchL1 latch

Clock opens latch and evaluates subsequent logic:

Static signals driving dynamiclogic must be eithernon-inverting orstable before latch opens

N-dominoprecharges

P-dominoevaluates

N-dominoevaluates

P-dominoprecharges

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UC Berkeley EE241 B. Nikoli c

Dynamic Logic with Latches

Edges become hardTime available to logic is P – 2TD-Q From [Harris]

UC Berkeley EE241 B. Nikoli c

Two-Phase Clocking with Latches

ClkPW1

ClkPW2

TOV

TOV is the overlap time between the phases – can be positive or negative

Duty cycles can be larger or smaller than 50%

Very common example is two-phase non-overlapping clocking

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UC Berkeley EE241 B. Nikoli c

Soft-Edge Properties of Latches

l Slack borrowing – logical partition uses left over time (slack) from the previous partition

l Time stealing – logical partition utilizes a portion of time allotted to the next partition

Bernstein et al, Chapter 8

UC Berkeley EE241 B. Nikoli c

50% Duty Cycle

L1Latch Logic Logic

L2Latch

L1Latch Logic

L2Latch

C2

C1

C1 and C2 are two ideal phases

Cycle boundary latches(CBL)

Mid-cycle latches(MCL)

S1 S1S2

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UC Berkeley EE241 B. Nikoli c

Slack Borrowing

l L1 phase time is from the falling edge of C2 to the falling edge of C1

l L2 phase time is from the falling edge of C1 to the falling edge of C2

l L1phase delay is the sum of S1 logic delay and L1 delay

l L2 phase delay is the sum of S2 logic delay and L2 delay

l Phase delays can be greater or less than phase times

UC Berkeley EE241 B. Nikoli c

Slack Borrowing

C1 = 1

C2 = 1L1 latch

L2 latch

S1delay

S2delay

L1 phase delay

L2 phase delay

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UC Berkeley EE241 B. Nikoli c

Slack Borrowing

From[Bernstein et al]

UC Berkeley EE241 B. Nikoli c

Slack Borrowing

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Slack Borrowing Example

From[Bernstein et al]

UC Berkeley EE241 B. Nikoli c

Slack Borrowing Example (2)

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UC Berkeley EE241 B. Nikoli c

Time Stealing

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Time Stealing Example

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UC Berkeley EE241 B. Nikoli c

Time Stealing Example (2)

UC Berkeley EE241 B. Nikoli c

Skew-Tolerant Domino

l General Reference:Harris, Horowitz, “Skew-tolerant domino circuits”

ISSCC’97, JSSC 11/97

Also slides from D. Harris’s Web site:http://www3.hmc.edu/~harris/index.html

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UC Berkeley EE241 B. Nikoli c

Domino Logic with Latches

Time available to logic is P – 2TD-Q

UC Berkeley EE241 B. Nikoli c

Clock Skew

Time penalty: TL = P – (2TD-Q + 2Tsk)

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UC Berkeley EE241 B. Nikoli c

Non-Balanced Phase Delays

Time penalty: TL = P – (2TD-Q + 2Tsk) - Timbal

UC Berkeley EE241 B. Nikoli c

Skew-Tolerant Domino

Overlap clocks:• x evaluates before y precharges • implicit latch between φ1 and φ2• no need for latch between domino phases

From [Harris]

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Multiple Phases

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Precharge Phase

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UC Berkeley EE241 B. Nikoli c

Evaluation Phase

UC Berkeley EE241 B. Nikoli c

Skew Tolerance

From [Harris]

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Time Borrowing