1 EE241 Spring 2010 EE241 - Spring 2010 Advanced Digital Integrated Circuits TuTh 3:30-5pm 293 Cory Practical Information Instructor: Borivoje Nikolić 550B C H ll 3 9297 b @ 550B Cory Hall , 3-9297, bora@eecs Office hours: M 10:30am-12pm Reader: TBA tba@eecs Admin: Rosita Alvarez-Croft 2 253 Cory Hall, 3-4976, rosita@eecs Class Web page http://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s10
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EE241 - Spring 2010bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s10/Lectures/Lecture1-Intro-annotated.pdf“Leakage in Nanometer CMOS Technologi es,” by Narendra and Chandrakasan,
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EE241 Spring 2010EE241 - Spring 2010Advanced Digital Integrated Circuits
TuTh 3:30-5pm293 Cory
Practical InformationInstructor:
Borivoje Nikolić550B C H ll 3 9297 b @550B Cory Hall , 3-9297, bora@eecs
Office hours: M 10:30am-12pm
Reader: TBAtba@eecs
Admin: Rosita Alvarez-Croft
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253 Cory Hall, 3-4976, rosita@eecs
Class Web pagehttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s10
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Class Topics
This course aims to convey a knowledge of advanced concepts of circuit design for digital VLSI components in state-of-the-art MOS technologies in state of the art MOS technologies.
Emphasis is on the circuit design, and optimization for both high performance high speed and low power for use in applications such as microprocessors, signal and multimedia processors, communications, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of
li d b i ff t i bilit di t ib ti d
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scaling, deep sub-micron effects, variability, power distribution and consumption, and timing.
EECS141 vs. EECS241
EECS 141:Basic transistor and circuit modelsBasic circuit design stylesBasic circuit design stylesFirst experiences with design – creating a solution given a set of specifications
EECS 241:Transistor models of varying accuracyDesign under constraints: power-constrained, flexible, robust,…
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g pLearning more advanced techniques Study the challenges facing design in the coming yearsCreating new solutions to challenging design problems
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EECS141 vs. EECS241
EECS1410.25m and 90nm CMOS
Unified transistor model
EECS241Mostly 45nm CMOS
Different modelsUnified transistor model
Basic circuit design techniques
Well defined design project
Cadence/Hspice
Focus on principles
Different models
Advanced circuit techniques
Open design/research project
Any tool that does the job
Focus on principles
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Special Focus in Spring 2010
Current technology issues
Process variationsProcess variations
Robust design
SRAM
Power and performance optimization
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Timing
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Class TopicsFundamentals - Technology and modeling – Scaling and its limits (2 weeks)
Introduction to variability: SRAM example (3 weeks)Sources of variability, modeling y, g
1 term-long design project (40%)Phase 1: Proposal (week of ISSCC)
Phase 2: Study (report by week 8)
Phase 3: Design (presentation and report by final week)
Report and presentations, May 4
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Final exam (30%) (Thursday, April 29, in-class)
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Class Material
Text: J. Rabaey, “Low Power Design Essentials,” Springer 2009.Available at www.springerlink.com
Baseline: “Digital Integrated Circuits - A Design Perspective”, 2ndBaseline: Digital Integrated Circuits A Design Perspective , 2ed. by J. M. Rabaey, A. Chandrakasan, B. NikolićOther reference books:
“Design of High-Performance Microprocessor Circuits,” edited by A. Chandrakasan, W. Bowhill, F. Fox“Low-Power Electronics Design,” C. Piguet, Ed.“CMOS VLSI Design,” 3rd ed, N.Weste, D. Harris“Hi h S d CMOS D i St l b K B t i t l
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“High-Speed CMOS Design Styles, by K. Bernstein, et al.“Leakage in Nanometer CMOS Technologies,” by Narendra and Chandrakasan, Ed.“Digital Systems Engineering” by W. Dally
Class Material
List of background material available on web-site
Selected papers will be made available on web-siteLinked from IEEE Xplore and other resources
Need to be on campus to access, or use library proxy, library VPN (check http://library.berkeley.edu)
Class-notes on web-siteNo printed handouts in class!
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Sources
IEEE Journal of Solid-State Circuits (JSSC)
IEEE International Solid-State Circuits Conference (ISSCC)
Symposium on VLSI Circuits (VLSI)
Other conferences and journals
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Project Topics
Focus this semester: ResiliencyCan span from architecture to technologyImmunity to variations and soft errors in logic and SRAMVariability compensationDelay monitoringAdaptive designs
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Power-performance tradeoffsTemperature, supply, noise measurementsOr a topic of interest to you
0.18 /0.13/0.09 m CMOS device models on the class web site
Other tools, schematic or layout editors are optional
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Cadence, Synopsys, available on instructional servers
More information on the web site.
EE241 Spring 2010EE241 - Spring 2010Advanced Digital Integrated Circuits
Lecture 1: IntroductionTrends and Challenges in Trends and Challenges in
Digital Integrated Circuit Design
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Suggested ReadingInternational Technology Roadmap (http://public.itrs.net) Rabaey, LPDE, Ch 1 (Introduction)Baseline: Rabaey et al, DIC Chapter 3.Chandrakasan, Bowhill, Fox, Chapter 1 – Impact of physical technology on architecture (J.H. Edmondson),Chandrakasan, Bowhill, Fox, Chapter 2 – CMOS scaling and issues in sub-0.25m systems (Y. Taur)Selected papers from the web:
G.E. Moore, No exponential is forever: but "Forever" can be delayed! Proc. ISSCC’03, Feb 2003.
T C Chen Where CMOS is going: trendy hype vs real technology Proc ISSCC’06 Feb
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T.-C. Chen, Where CMOS is going: trendy hype vs. real technology. Proc. ISSCC 06, Feb 2006.
S. Chou, Innovation and Integration in the Nanoelectronics Era, Proc. ISSCC’05, Feb. 2005.
S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol.19, no.4, p.23-29, July-Aug. 1999.
The contributions to this lecture by a number of people (J. Rabaey, S. Borkar, etc) are greatly appreciated.
Semiconductor Industry Revenues
16M. Chang, “Foundry Future: Challenges in the 21st Century,” ISSCC’2007
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Moore’s Law
In 1965, Gordon Moore noted that the number of t i t hi d bl d 12 thtransistors on a chip doubled every 12 months. He made a prediction that semiconductor technology will double its effectiveness every 12 months
“The complexity for minimum component costs has increased at a rate of roughly a
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factor of two per year. Certainly over the short term, this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000.”Gordon Moore, Cramming more Components onto Integrated Circuits, (1965).
Moore’s Law - 1965
““Reduced cost is one of the big Reduced cost is one of the big attractions of integrated attractions of integrated electronics, and the cost electronics, and the cost advantage continues to increaseadvantage continues to increase
TransistorsTransistorsPer DiePer Die
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advantage continues to increase advantage continues to increase as the technology evolves as the technology evolves toward the production of larger toward the production of larger and larger circuit functions on a and larger circuit functions on a single semiconductor substrate.”single semiconductor substrate.”Electronics, Volume 38, Electronics, Volume 38, Number 8, April 19, 1965Number 8, April 19, 1965