EE201L_ClassNotes_Ch10_Counters_transparencies.fm 4/24/06 EE201L Class Notes - Chapter #10 Counters Page 1 / 8 C Copyright 2006 Gandhi Puvvada Chapter 10 Counters (a short discussion) 1 Decimal count sequence: Ex: 788, 789, 790, . . . Ex: 798, 799, 800, . . . Generalization: 2 Binary count sequence: In a multi-bit up counter, a bit (such as Q2) will flip (in- crement) when all its right neighbors (Q1 and Q0) are ________________ (all 1’s / all 0’s). In a multi-bit down counter, a bit (such as Q2) will flip (decrement) when all its right neighbors (Q1 and Q0) are ________________ (all 1’s / all 0’s). 3 Basic element in building a counter: A toggle flip-flop A JK FF with its J and K tied to ________________ (0,0 / 1,1) acts as a toggle FF. If the J and K are tied to ________________ (0,0 / 1,1), the FF remains stay put. 4 Ripple counter Which of the following is an up-counter and which is a down-counter? What are the rest? Do you call the counter a positive-edge triggered counter or a negative-edge triggered counter or a mixed-edge triggered counter? Whey are these called ripple counters? 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 Q2 Q1 Q0 Q2 Q1 Q0 J Q CLK Q K J Q CLK Q K
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In a multi-bit up counter, a bit (such as Q2) will flip (in-crement) when all its right neighbors (Q1 and Q0) are________________ (all 1’s / all 0’s).
In a multi-bit down counter, a bit (such as Q2) will flip(decrement) when all its right neighbors (Q1 and Q0)are ________________ (all 1’s / all 0’s).
3 Basic element in building a counter: A toggle flip-flop
A JK FF with its J and K tied to ________________ (0,0 / 1,1) acts as a toggle FF.
If the J and K are tied to ________________ (0,0 / 1,1), the FF remains stay put.
4 Ripple counter
Which of the following is an up-counter and which is a down-counter? Whatare the rest?Do you call the counter a positive-edge triggered counter or a negative-edge triggered counter or a mixed-edge triggered counter? Whey are these called ripple counters?
Which of the following D-FF hook-ups act as a toggle FF? How do you describe the others?
Which of the following D-latch hook-ups act as a toggle latches!? How do you describe the others?
6 Ripple counter using D-FFs
In lab #4, you built a ripple counter, using negative-edge triggered JK Flip-Flops.Build a 4-bit ripple UP counter using the four D-FF hookups given below. This counter shall count-upwhenever the sysclk produces a positive edge. Label the four outputs RQ3RQ2RQ1RQ0 (RQ0 is the LSB. "R" stands for "ripple).
To change the above design so as to make the counter to count on the negative edges of the sysclk,would you change just one of the four FFs to a negative-edge triggered FF or all the four? If one, which one?
Which of the following D-FF hook-ups act as a toggle FF? How do you describe the others?
Which of the following D-latch hook-ups act as a toggle latches!? How do you describe the others?
6 Ripple counter using D-FFs
In lab #4, you built a ripple counter, using negative-edge triggered JK Flip-Flops.Build a 4-bit ripple UP counter using the four D-FF hookups given below. This counter shall count-upwhenever the sysclk produces a positive edge. Label the four outputs RQ3RQ2RQ1RQ0 (RQ0 is the LSB. "R" stands for "ripple).
To change the above design so as to make the counter to count on the negative edges of the sysclk,would you change just one of the four FFs to a negative-edge triggered FF or all the four? If one, which one?
You may have seen in one of the episodes of "I love Lucy". Lucy tries to dance by lookingat other dancers rather than by following the beat of the drum.
If the FF propagation delay is 1 ns, then, in the case of a 32-bit ripple counter
In the case of a synchronous counter design, each FF shall be prepared individually to toggle if appro-priate on the tick of the next clock.
8 A synchronous counter with CLR, LOAD, and EN controls
To build the three bit incrementer, do you need 3 full-adders or 3 half-adders? __________________
You may have seen in one of the episodes of "I love Lucy". Lucy tries to dance by lookingat other dancers rather than by following the beat of the drum.
If the FF propagation delay is 1 ns, then, in the case of a 32-bit ripple counter
In the case of a synchronous counter design, each FF shall be prepared individually to toggle if appro-priate on the tick of the next clock.
8 A synchronous counter with CLR, LOAD, and EN controls
To build the three bit incrementer, do you need 3 full-adders or 3 half-adders? __________________
10 Transitional values at the output of counters during transition
all 1’s (1111_1111_1111_1111) rolling over to all 0’s (0000_0000_0000_0000),
is it possible that any 16-bit number may appear at the output of the counter for a very short time during the transition? ___________ (Yes / No).Does your answer assume that the counter is a ripple counter or a synchronous counter or any of the two types? ________________________ Is there any harm due to these transitional values? ____________________________________________________________________
D Q
A0A1A2
B0B1B2
S0S1S2
Adder
001
Most Significant
RegisterQ0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
CLK
D QQ3* Q3
B3
A3
S3
D QCLK
D QCLK
D QCLK
D QCLK
sysclk
sysclk
sysclk
sysclk
D QCLKsysclk
Instead of looking at half-adders building an incre-menter, you can explain the design slightly differently.
The XOR gate in front of the D-FF acts like an inverterif the control input is a 1. Else (if the control input is azero), it (the XOR gate) acts like a non-inverter. So basically, the control input (CTRL) is telling the D-FF (through the XOR gate) whether it should be tog-gling on the next clock.
CTRLi Qi
Label the outputs
Q
Q
Q
Q
CTRLi = Qi-1 . Qi-2 . . . . . Q0
Can you replace this with a 3-input and gate to improve performance?
10 Transitional values at the output of counters during transition
all 1’s (1111_1111_1111_1111) rolling over to all 0’s (0000_0000_0000_0000),
is it possible that any 16-bit number may appear at the output of the counter for a very short time during the transition? ___________ (Yes / No).Does your answer assume that the counter is a ripple counter or a synchronous counter or any of the two types? ________________________ Is there any harm due to these transitional values? ____________________________________________________________________
D Q
A0A1A2
B0B1B2
S0S1S2
Adder
001
Most Significant
RegisterQ0
Q1
Q2
D Q
D Q
Q0*
Q1*
Q2*
CLK
D QQ3* Q3
B3
A3
S3
D QCLK
D QCLK
D QCLK
D QCLK
sysclk
sysclk
sysclk
sysclk
D QCLKsysclk
Instead of looking at half-adders building an incre-menter, you can explain the design slightly differently.
The XOR gate in front of the D-FF acts like an inverterif the control input is a 1. Else (if the control input is azero), it (the XOR gate) acts like a non-inverter. So basically, the control input (CTRL) is telling the D-FF (through the XOR gate) whether it should be tog-gling on the next clock.
CTRLi Qi
Label the outputs
Q
Q
Q
Q
CTRLi = Qi-1 . Qi-2 . . . . . Q0
Can you replace this with a 3-input and gate to improve performance?
Consider the following two designs. Are they both right designs? Is one of them better if you want to build a "fast" counter?
12 Truncated Counters
Complete the following two incomplete designs of a truncated counter with 5 states 0, 1, 2, 3, 4, (from4 back to 0). Which is better if we want to build a "fast" counter.
Consider the following two designs. Are they both right designs? Is one of them better if you want to build a "fast" counter?
12 Truncated Counters
Complete the following two incomplete designs of a truncated counter with 5 states 0, 1, 2, 3, 4, (from4 back to 0). Which is better if we want to build a "fast" counter.
15 Fix Mr. Bruin, I mean, Mr. Bruin’s design of a stop watch. This stop watch goes from 0:00 to 1:59 (1 Min. 59 Sec.) and rolls back to 0:00. It has a CLEAR and START/STOP controls.
15 Fix Mr. Bruin, I mean, Mr. Bruin’s design of a stop watch. This stop watch goes from 0:00 to 1:59 (1 Min. 59 Sec.) and rolls back to 0:00. It has a CLEAR and START/STOP controls.