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Digital TimingDigital Timing All sequential circuits must have a well-defined ordering of the switching events to ensure the correct operation.
The very popular synchronous approach, in which all memory elements in the system are simultaneously updated using a globally distributed periodic synchronization signal, is an effective way to enforce correct ordering
But global synchronous clock might suffer from clock skew (spatial variation) and clock jitter (temporal variation)
Asynchronous design avoids the problem of clock uncertainty by eliminating the need for a globally distributed clock at expense of hardware and speed (not necessarily)
This means that clock skew has the potential to improve the performance of the circuit (minimum required clock period reduces!). However, increasing clock skew makes the circuit more susceptible to race conditions.
Clock Distribution TechniquesClock Distribution Techniques Clock skew and jitter affects the system performance, so it is important to design a clock network to minimize both.
When designing clock network, power consumption is a big issue. In today’s digital processors, a majority of the power is dissipated in the clock network.
To reduce power consumption, part of the clock network should conditionally shut down
Clock network design is a complicated task with many degrees of freedom, such as material used for wires, basic topology and hierarchy, sizing of wires and buffers, rise time and fall time, load capacitance etc.
Clock Distribution TechniquesClock Distribution Techniques
CLK
Clock is distributed in a tree-like fashion
Balance pathApproach:H-tree
The absolute delay from a central clock source to the clock elements is irrelevant, only the relative phase or delay between any two clock elements is important.
More realistic H-treeMore realistic H-tree The H-tree configuration is particularly useful for regular array networks in which all elements are identical and the clock can be distributed as a binary tree.
A more general approach, referred to as matched RC trees, represents a floorplan that distributes the clock signal so that the interconnections carrying the clock signals to the functional sub-blocks have equal time constants. (that is the general approach does not rely on a regular physical structure)