EE 60542 - Analog Integrated Circuits Design Project ... · 1. Overview 1. Overview In this project, an operational ampli er is designed and simulated using AIMSPICE, based on the

EE 60542 - Analog Integrated

Circuits

Design Project:

Achieving Low Power Dissipation

by

Louisa C. Schneider

University of Notre Dame

Contents

Contents

1. Overview 1

2. Summary Goals vs. Simulation 3

2.1. Design Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1.1. Read-out parameters . . . . . . . . . . . . . . . . . . . . . . . 4

2.1.2. Target calculation . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1.3. Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2. Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.1. Open Loop Gain - Magnitude . . . . . . . . . . . . . . . . . . 6

2.2.2. Open Loop Gain - Phase . . . . . . . . . . . . . . . . . . . . . 6

2.2.3. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.4. Maximum Input/Output Swing . . . . . . . . . . . . . . . . . 9

3. Aimspice 10

3.1. SPICE Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2. Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4. Executive Summary 11

A. Netlist 12

B. Operating Point 17

C. Transfer Function Analysis 20

I

1. Overview

1. Overview

In this project, an operational amplifier is designed and simulated using AIMSPICE,

based on the configurations from the class textbook1 given in chapter 6. In particular,

the following design parameters are of interest:

• Supply Voltage

• Power Dissipation

• Open Loop Gain

• Open Loop Bandwidth

• Load

• Input Resistance

• Output Resistance

• Maximum Output Swing

• Minimum Output Swing

• Phase Margin

1Analog Integrated Circuit Design, T. Carusone, D. Johns, K. Martin, 2e, 2012

1

1. Overview

The technology models for the 16nm-node MOSFET are used in the AIMSPICE

simulation, giving a minimum gate length of 16nm. The widths of the different

transistors as well as the supply voltage are individually choosen to meet the design

specifications.

The circuit in figure 3.1 is simulated for this project2.

Figure 1.1.: Simulated Circuit

2Figure 6.3, page 243, Analog Integrated Circuit Design, T. Carusone, D. Johns, K. Martin, 2e,2012

2

2. Summary Goals vs. Simulation

2. Summary Goals vs. Simulation

2.1. Design Parameter

Parameter Target Simulated Units

Supply Voltage 2.1 2.1 VPower Dissipation 1.2 0.561 mWOpen Loop Gain 2.4 2.39 V/VOpen Loop Bandwidth 100 3.3 ·109 HzRC-Load 10; 8 10; 8 MΩ; pFInput Resistance 2.5 5.64 ·105 MΩOutput Resistance 500 618 ΩMaximum Output Swing 2 0.6 VMinimum Output Swing 0.1 0.175 VPhase Margin 45 113 deg

Table 2.1.: Design Goals vs. Simulation Results

3

2. Summary Goals vs. Simulation

2.1.1. Read-out parameters

(a) n-mos (b) p-mos

Figure 2.1.: IV curves for n- and p-mos

Parameter nmos pmos Units

gm 3.125 1.75 mSr0 1 1 kΩVeff 0.1 0.1 V

Table 2.2.: Read-out parameters

2.1.2. Target calculation

1. The supply voltage is chosen as 2.1V, to ensure a supply of at least 0.7V for

every transistor in the circuit.

2. The bias current is chosen to 27µA.

3. The power dissipation is simply given by

P = V · I (2.1)

= 2.1V · 26 · 20µA (2.2)

= 1.1mW (2.3)

4

2. Summary Goals vs. Simulation

4. Open Loop Gain:

Av =(gm · r0

2

)2

(2.4)

= 2.4V/V (2.5)

5. Open Loop Bandwidth: choosen to be 100Hz

6. RC-Load: with C = 8pF and R = 10MΩ

7. Input Resistance ∼ 2.5MΩ (is given by typical Op-Amp Datasheet values)

8. Output Resistance:

Rout =r02

(2.6)

= 500Ω (2.7)

9. Max. Output Swing

Vout,max = VDD − Veff (2.8)

= 2V (2.9)

10. Min. Output Swing

Vout,min = Veff (2.10)

= 0.1V (2.11)

11. Phase Margin: Choosen to 45

2.1.3. Simulation

The values in table 2.1 are read out of the operating point analysis once the simulation

is done.

5

2. Summary Goals vs. Simulation

2.2. Simulation Results

2.2.1. Open Loop Gain - Magnitude

2.2.2. Open Loop Gain - Phase

6

2. Summary Goals vs. Simulation

2.2.2.1. Unity Gain Frequency

ωt = 7.5 Ghz

2.2.2.2. The 3dB-Frequency

ω3dB = 3.3 Ghz

2.2.2.3. Phase Margin

At ωt = 7.5Ghz, the phase margin is given by

PM = 180 − 67 (2.12)

= 113 (2.13)

2.2.2.4. Bandwidth

The bandwidth is given by the 3dB-frequency:

Bandwidth = 3.3 Ghz

The listed parameters are read out of the magnitude and phase plots on page 6.

Each plot shows an open-loop condition (meaning no load attached) and the effect

of an RC load attached to the output of the amplifier. Clearely it can be seen that

adding a load does not change the magnitude of the gain nor the stability, since the

Phase Margin of the open loop amplifier is already less then 180. As shown in the

simulation results, the load has only an effect on the bandwidth of the amplifier.

7

2. Summary Goals vs. Simulation

2.2.3. Power Dissipation

Parameter Value Unit

Current 6.29 ·10−4 ABias Voltage 2.1 VPower 1.32·10−3 W

Table 2.3.: Operating Point Analysis (Simulation values)

The power dissipation is calculated by the supply voltage multiplied by the sum of

all currents (for exact values see the operating point analysis in the appendix on

page 17):

P = V · I (2.14)

= 2.67 · 10−4A · 2.1V (2.15)

= 0.561 · 10−3W (2.16)

The dissipated power is now 0.56mW, which is half of the target value. This amplifier

was optimized for a lower power consumption, and 0.56mW was the lowest value that

could be achieved in this design.

Since the supply voltage is kept constant, the dissipated power is directly proportional

to the current. The current, in turn, is manly depending on the different WL

-ratios

of the different transistors used in the amplifier.

Changing the width and the bias current, a lower power dissipation that expected

was achieved.

8

2. Summary Goals vs. Simulation

2.2.4. Maximum Input/Output Swing

The output swing is simulated by applying a sinusoidal singal to the input of the

differentail amplifier. As can be seen in figure 2.2, the signal clips at the top and

bottom of the curve. This defines the maximum/minimum output swing.

Figure 2.2.: Output Swing of the Operational Amplifier

2.2.4.1. Maximum Swing

vout,max = 0.6V

2.2.4.2. Minimum Swing

vout,min = 0.175V

9

3. Aimspice

3. Aimspice

3.1. SPICE Netlist

The Netlist used for all simulations is given at the end of the report.

3.2. Circuit

Figure 3.1.: Simulated Circuit with labeled nodes (RC load is not shown here)

DC voltages:

• VDD=2.1V

• V +in = V −

in = 0.9V

The currents, which are measured during the simulation, are labeled in red in figure

3.1.

10

4. Executive Summary

4. Executive Summary

Summarizing, in table 2.1 (on page 3) the simulation results are shown compared

to the hand-calculated target values. Almost all targets are archieved, except of the

bandwidth which turned out to be an unrealistic choice.

Most important, the power dissipation is reduced by a factor of 2 while still keeping

a high bandwidth of the designed amplifier.

Compared to an ideal op-amp, the input current is non-zero, but very low, in the

order of 12 pA. The input impedance is given by the simulation to 618Ω, the output

impedance is very high (around 5·105MΩ). These results are very realistic, since a

zero-input restistance and a infinite output resistance (in an ideal case) cannot be

fabricated.

Due to a low gain, the circuit is very stable, and no frequency compensation methods

(eg. adding RC and/or CC) are necessary. As can be seen in the simulation results

for the output voltage magnitude and phase plots (given on page 6), adding a load

does not change the stability of the circuit. The phase margin is simulated to 113,

which is already lower than 180, so the circuit is considered as stable in any case.

However, adding a load does change the frequency response of the amplifier: it will

get reduced. This feature is useful for designing (low-pass) filters, by choosing ap-

propriate parameters one can tune it to a specific frequency range.

The operating point analysis, the transfer function analysis and the complete netlist

are given in the appendix.

11

Appendix A. Netlist

Appendix A.

Netlist

12

* IC Design Project - Netlist * Current source Ibias 8 0 1.7u * Voltage Source Vdd 9 0 2.1 * Input Voltage Vin- 1 0 DC 0.9 AC 1m 180 Vin+ 2 0 DC 0.9 AC 1m 0 *Vin+ 2 0 sin(0.01 0.25 1k 0 0) *Vin- 0 1 sin(0.01 0.25 1k 0 0) * Nodes MOSFET's: D G S B * Biasing: Q8 m8 8 8 9 9 pmos1 L=0.016u W=0.04u * Tail current: Q5 m5 3 8 9 9 pmos1 L=0.016u W=0.04u * Input pair: Q1, Q2 m1 4 1 3 9 pmos1 L=0.016u W=0.02u m2 5 2 3 9 pmos1 L=0.016u W=0.02u * Active load for diff pair: Q3, Q4 m3 4 4 20 0 nmos1 L=0.016u W=0.02u m4 5 4 30 0 nmos1 L=0.016u W=0.02u * Output stage: Q6, Q7 m6 7 8 9 9 pmos1 L=0.016u W=0.04u m7 7 5 40 0 nmos1 L=0.016u W=0.9u *Load c1 7 0 8p r1 7 0 10Meg Vs3 20 0 DC 0 Vs4 30 0 DC 0 Vs7 40 0 DC 0 * PTM High Performance 16nm Metal Gate / High-K / Strained-Si * nominal Vdd = 0.7V .model nmos1 nmos level = 32 +version = 4.6.1 binunit = 1 paramchk= 1 mobmod = 0

+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 +permod = 1 acnqsmod= 0 trnqsmod= 0 +tnom = 27 toxe = 9.5e-010 toxp = 7e-010 toxm = 9.5e-010 +dtox = 2.5e-010 epsrox = 3.9 wint = 5e-009 lint = 1.45e-009 +ll = 0 wl = 0 lln = 1 wln = 1 +lw = 0 ww = 0 lwn = 1 wwn = 1 +lwl = 0 wwl = 0 xpart = 0 toxref = 9.5e-010 +xl = -6.5e-9 +vth0 = 0.47965 k1 = 0.4 k2 = 0 k3 = 0 +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 5e-009 +ngate = 1e+023 ndep = 7e+018 nsd = 2e+020 phin = 0 +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 +voff = -0.13 nfactor = 2.3 eta0 = 0.0032 etab = 0 +vfb = -0.55 u0 = 0.03 ua = 6e-010 ub = 1.2e-018 +uc = 0 vsat = 290000 a0 = 1 ags = 0 +a1 = 0 a2 = 1 b0 = 0 b1 = 0 +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 +fprout = 0.2 pdits = 0.01 pditsd = 0.23 pditsl = 2300000 +rsh = 5 rdsw = 140 rsw = 75 rdw = 75 +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 +eigbinv = 1.1 nigbinv = 3 aigc = 0.0213 bigc = 0.0025889 +cigc = 0.002 aigsd = 0.0213 bigsd = 0.0025889 cigsd = 0.002 +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 +xrcrg1 = 12 xrcrg2 = 5 +cgso = 5e-011 cgdo = 5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010 +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 +moin = 15 noff = 0.9 voffcv = 0.02 +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 +at = 33000 +fnoimod = 1 tnoimod = 0 +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1

+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 +xtis = 3 xtid = 3 +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 +dwj = 0 xgw = 0 xgl = 0 +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 .model pmos1 pmos level = 32 +version = 4.6.1 binunit = 1 paramchk= 1 mobmod = 0 +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 +permod = 1 acnqsmod= 0 trnqsmod= 0 +tnom = 27 toxe = 1e-009 toxp = 7e-010 toxm = 1e-009 +dtox = 3e-010 epsrox = 3.9 wint = 5e-009 lint = 1.45e-009 +ll = 0 wl = 0 lln = 1 wln = 1 +lw = 0 ww = 0 lwn = 1 wwn = 1 +lwl = 0 wwl = 0 xpart = 0 toxref = 1e-009 +xl = -6.5e-9 +vth0 = -0.43121 k1 = 0.4 k2 = -0.01 k3 = 0 +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 5e-009 +ngate = 1e+023 ndep = 5.5e+018 nsd = 2e+020 phin = 0 +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 +voff = -0.126 nfactor = 2.1 eta0 = 0.0032 etab = 0 +vfb = 0.55 u0 = 0.006 ua = 2e-009 ub = 5e-019 +uc = 0 vsat = 250000 a0 = 1 ags = 1e-020 +a1 = 0 a2 = 1 b0 = 0 b1 = 0 +keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 +pvag = 1e-020 delta = 0.01 pscbe1 = 1.2e+009 pscbe2 = 8.0472e-007 +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 +rsh = 5 rdsw = 140 rsw = 70 rdw = 70

+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 +eigbinv = 1.1 nigbinv = 3 aigc = 0.0213 bigc = 0.0025889 +cigc = 0.002 aigsd = 0.0213 bigsd = 0.0025889 cigsd = 0.002 +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 +xrcrg1 = 12 xrcrg2 = 5 +cgso = 5e-011 cgdo = 5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010 +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 +moin = 15 noff = 0.9 voffcv = 0.02 +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 +at = 33000 +fnoimod = 1 tnoimod = 0 +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 +xtis = 3 xtid = 3 +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 +dwj = 0 xgw = 0 xgl = 0 +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1

Appendix B. Operating Point

Appendix B.

Operating Point

17

Operating Point Analysis

* Common source ID VDS - 16 nm PTM look-ahead model

Variables in circuit Values

v(8) 1.74878 V

v(9) 2.1 V

v(1) 0.9 V

v(2) 0.9 V

v(3) 1.32388 V

v(4) 0.437255 V

v(5) 0.437254 V

v(20) 0 V

v(30) 0 V

v(7) 0.417914 V

v(40) 0 V

v(m7.gate) 0.437254 V

v(m7.dbody) 6.88065E-012 V

v(m7.body) 7.49259E-012 V

v(m7.sbody) 3.74629E-012 V

v(m4.gate) 0.437255 V

v(m4.dbody) 3.7533E-012 V

v(m4.body) 9.47793E-013 V

v(m4.sbody) 4.73897E-013 V

v(m3.gate) 0.437255 V

v(m3.dbody) 3.75331E-012 V

v(m3.body) 9.47797E-013 V

v(m3.sbody) 4.73898E-013 V

v(m6.gate) 1.74878 V

v(m6.dbody) 2.1 V

v(m6.body) 2.1 V

v(m6.sbody) 2.1 V

v(m2.gate) 0.9 V

v(m2.dbody) 2.1 V

v(m2.body) 2.1 V

v(m2.sbody) 2.1 V

v(m1.gate) 0.9 V

v(m1.dbody) 2.1 V

v(m1.body) 2.1 V

v(m1.sbody) 2.1 V

v(m5.gate) 1.74878 V

v(m5.dbody) 2.1 V

v(m5.body) 2.1 V

v(m5.sbody) 2.1 V

v(m8.gate) 1.74878 V

v(m8.dbody) 2.1 V

v(m8.body) 2.1 V

v(m8.sbody) 2.1 V

i(vs7) 0.000255644 A

i(vs4) 4.92131E-006 A

i(vs3) 4.92133E-006 A

i(vin+) 1.62537E-013 A

i(vin-) 1.62981E-013 A

i(vdd) -0.000267187 A

Appendix C. Transfer Function Analysis

Appendix C.

Transfer Function Analysis

20

Transfer Function Analysis

* Common source ID VDS - 16 nm PTM look-ahead model

transfer function 1.2707

vin+.input impedance 5.64E+11

output impedance at v(7) 618.042