Eds

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous)

(ISO/IEC - 27001 - 2005 Certified)

SUMMER – 13 EXAMINATION Subject Code: 12262 Model Answer Page No: 1 / 38 ___________________________________________________________________________________

Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate may vary but the examiner may try to assess the understanding level of the candidate. 3) The language errors such as grammatical, spelling errors should not be given more Importance (Not applicable for subject English and Communication Skills). 4) While assessing figures, examiner may give credit for principal components indicated in the figure. The figures drawn by candidate and model answer may vary. The examiner may give credit for any equivalent figure drawn. 5) Credits may be given step wise for numerical problems. In some cases, the assumed constant values may vary and there may be some difference in the candidate’s answers and model answer. 6) In case of some questions credit may be given by judgement on part of examiner of relevant answer based on candidate’s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept.




Q.1]a) i) (02-marks for diagram, 02-marks for explanation)

Draw pin diagram of RS232 DB9 connector and describe all pins.

TXD

This is the pin through which serial data is transmitted by data terminal equipment.

RXD

Serial data is received by Data terminal equipment through RXD line




DTR (data terminal ready)

When Data terminal Equipment (DTE) is turned on, it sends out signal DTR to indicate that it is

ready for communication.

DSR (data set ready)

When Data Communication Equipment (modem, DCE) is turned on and has gone through the

self-test, it assert DSR to indicate that it is ready to communicate.

RTS (request to send)

When the DTE device has byte to transmit, it assert RTS to signal the modem that it has a byte of

data to transmit

CTS (clear to send)

When the modem is ready to store the data it is to receive, it sends out signal CTS to DTE to

indicate that it can receive the data now

DCD (data carrier detect)

The modem asserts signal DCD to inform the DTE that a valid carrier has been detected and that

contact between it and the other modem is established

RI (ring indicator)

An output from the modem and an input to a PC indicates that the telephone is ringing. It goes on

and off in synchronous with the ringing sound

Pin number 5 is signal ground.

Q.1]a) ii) State four applications of embedded systems

Any four application – 1 mark each

Applications can be

Mobile phone

Digital camera

Robots

Point of sales terminals

Automatic Chocolate Vending Machine

Stepper motor controllers for a robotics system

Washing or cooking system

Multitasking Toys




Microcontroller- based single or multi-display digital panel meter for voltage, current,

resistance and frequency

Keyboard controller

Serial port cards

CD drive or Hard Disk drive controller

Peripheral controllers,, a CRT display controller, a keyboard controller, a DRAM controller,

a DMA controller, a printer controller,

a laser printer-controller, a LAN controller, a disk drive controller

Fax or photocopy or printer or scanner machine

Remote (controller) of TV

Telephone with memory, display and other sophisticated features

_Motor controls Systems - for examples, an accurate control of speed and position of d.c.

motor, robot, and CNC machine;, the automotive applications like such as a close loop

engine control, a dynamic ride control, and an anti-lock braking system monitor

Electronic data acquisition and supervisory control system

Spectrum analyzer

Biomedical systems - for example, an ECG LCD display-cum-recorder, a blood- cell

recorder cum analyzer, and a patient monitor system service.

Banking systems - for examples, Bank

ATM and Credit card transactions

Signal Tracking Systems - for examples, an automatic signal tracker and a target tracker

Communication systems, for examples, such as for a mobile-communication a SIM card, a

numeric pager, a cellular phone, a cable TV terminal, and a FAX transceiver with or without

a graphic accelerator

Image Filtering, Image Processing, Pattern Recognizer, Speech Processing and Video

Processing

Q.1] a) iii) Describe in detail the interrupt handling mechanism in real time operating system

(RTOS)

What is interrupt handler - 1 Mark

Three ways of handling interrupt by RTOS – 1 mark each

An interrupt is a hardware mechanism used to inform the CPU that an asynchronous event has

occurred. The interrupt and event handling mechanism of an RTOS provides the following

functions:

• Defining interrupt handler

• Creation and deletion of ISR

• Referencing the state of an ISR




• Enabling and disabling of an interrupt

• Changing and referencing of an interrupt mask

RTOS uses one of three strategies on interrupt source calls

(i) A hardware source calls the ISR directly , and ISR just merely informs the RTOS on enter

and sends exit information before return.

(ii)RTOS Kernel intercepting the call and calling the corresponding ISR and tasks. RTOS

kernel schedules only the tasks (processes) and ISR executes only during a temporary suspension

of the task by the RTOS

(iii)RTOS Kernel intercepting the call and calling the ISR, which initiates and queues the ISR

call into a priority FIFO. The RTOS kernel schedules the ISTs and tasks (processes) as per

priorities.

Q.1] a)iv ) Explain in detail context switching between two tasks in an operating system.

Explanation – 2 marks

Each task has a context, which has a record that reflects the CPU state just before OS blocks one

task and initiates another task into running state. Context is continuously updated during the

running of a task.

When a multitasking kernel decides to run a different task, it saves the current task's context

(CPU registers) in the current task’s context storage area – its stack. After this operation is

performed , the new task’s context is restored from its storage area and then resumes execution

of the new task’s code. This process is called a context switch or a task switch. Context

switching adds overhead to the application. The more registers a CPU has, the higher the

overhead. The time required to perform a context switch is determined by how many registers

have to be saved and restored by the CPU.

Diagram – 2 marks Diagram can be drawn in various ways, but logically it should cover all the

concepts as below




Status

SP

Priority

Status

SP

Priority

Status

SP

Priority

SP

Context

MEMORY

CPU

Task Control Block

Task Control Block

StackStack

Stack

TASK # 1 TASK # 2 TASK # n

Task Control Block

CPU Registers

MULTIPLE TASKS

Q.1] b) i) Draw and describe memory organization of 8051 microcontroller

Program memory – 2 marks

Internal data memory – 3 marks

External data memory – 1 mark

The 8051 has separate address spaces for program storage and data storage called as program

memory and data memory




Program memory: diagram – 1 Mark, explanation – 1 mark

The executable program code is stored in this code memory. 8051 has 4kB internal ROM. External

code memory can also be connected to 8051, but the memory size is limited to 64KBytes (in a

standard 8051). The code memory is read-only in normal operation and is programmed under special

conditions e.g. it is a PROM or a Flash RAM type of memory.

The program memory can be either on-chip or external depending on the value of the EA input pin.

If EA is low, then the program memory is external.

If EA is high, then addresses from 0000 to 0FFF will refer to on-chip memory

and addresses 1000 upto FFFF refer to external memory.

Internal data memory: Diagram - 1 mark, explanation – 2 marks

The 8051’s on-chip memory consists of 256 memory bytes organized as follows:




First 128 bytes:

00h to 1Fh : Register Banks: The 8051 uses 8 general-purpose registers R0 through R7 (R0, R1,

R2, R3, R4, R5, R6, and R7).

20h to 2Fh : Bit Addressable RAM : The 8051 supports a special feature which allows access to

bit variables. This is where individual memory bits in Internal RAM can be set or cleared. In all

there are 128 bits numbered 00h to 7Fh. Being bit variables any one variable can have a value 0

or 1. A bit variable can be set with a command such as SETB and cleared with a command such

as CLR.

30 to 7Fh : General Purpose RAM : These 80 bytes of Internal RAM memory are available for

general-purpose data storage. The general purpose RAM can be accessed using direct or indirect

addressing modes.

Next 128 bytes: 80h to FFh Special Function Registers

The first 128 bytes of internal memory is organised as shown in figure below, and is referred to

as Internal RAM, or IRAM




External Data Memory - 1 Mark

Access to external memory is slower than access to internal data memory. There may be up to

64K Bytes of external data memory having address from 0000H to FFFFh.




Q.1] b) ii ) Describe the operation of Mode 0 and Mode 1 of timer in 8051 microcontroller

Mode 0: diagram - 1 marks, explanation - 2 marks

This is 13 bit timer mode. This mode is selected when M0 and M1 bits of TMOD register are 0

and 0.

The timer starts the operation when TR1 bit of TCON register is set to 1. If GATE bit of TMOD

register is high, the timer will start operation only when corresponding INT bit is high.

The upper 8 bits of the count are in TH and the lower 5 bits are in the lower 5 bits of TL. The

upper 3 bits of TL are not used.

The counter register will be incremented by one for each clock pulse. There are two clocking

sources: If C/T = 0, continuous timer operation is selected and the timer is clocked from by the

system clock divided by 12. If C/T = 1, the timer is clocked from an external source (pin T0 or

T1 on port 3).

The TFx flag will be set when the counter switches from all 1’s to all 0’s.

Mode 1: diagram 1 mark, explanation 2 marks




This is 16 bit timer mode. This mode is selected when M0 and M1 bits of TMOD register are 0

and 1.

The timer starts the operation when TR1 bit of TCON register is set to 1. If GATE bit of TMOD

register is high, the timer will start operation only when corresponding INT bit is high.

The upper 8 bits of the count are in TH and the lower 8 bits are in TL. The counter register will

be incremented by one for each clock pulse. There are two clocking sources: If C/T = 0,

continuous timer operation is selected and the timer is clocked from by the system clock divided

by 12. If C/T = 1, the timer is clocked from an external source (pin T0 or T1 on port 3).




Q.2] Identify the addressing mode used in following instruction

Four instructions – 1 mark each

i. MOV A, #55H – Immediate addressing mode

ii. ADD B – Register addressing mode

iii. MOV @Ri, 35H – direct addressing mode

iv. MOVC A, @A+DPTR – indexed addressing mode

Q.2] b) State the 8051 interrupts with priorities, vector location and cause

(Listing – 1 mark, Vector location - 1 mark, Priorities – 1 mark, Cause – 1 mark)

Interrupt Vector

location

priorities cause

External hardware

interrupt 0 (INTO)

0003H 1 IE0

Timer 0 internet (TFO

Overflow)

00OBH 2 TF0

External hardware

Interrupt 1 (INT1)

0013H 3 IE1

Timer 1 interrupt (TF1

Overflow)

001BH 4 TF1

Serial communication

interrupt (Rl and Tl)

(Reception/Transmission

of Serial Character)

0023H 5 TI or RI

Q.2] c) With suitable figure describe data transfer in I2c bus.(Diagram: 2 marks, Explanation – 2

marks)




1. Master sends start condition (S) and controls the clock signal

2. Master sends a unique 7-bit slave device address

3. Master sends read/write bit (R/W) – 0 - slave receive, 1 - slave transmit

4. Receiver sends acknowledge bit (ACK)

5. Transmitter (slave or master) transmits 1 byte of data

6. Receiver issues an ACK bit for the byte received

7. Repeat 5 and 6 if more bytes need to be transmitted

8. a) For write transaction (master transmitting), master issues stop condition (P) after last byte of

data.

b) For read transaction (master receiving), master does not acknowledge final byte, just issues

stop condition (P) to tell the slave the transmission is done.

Q.2] d) Enlist the hardware and software components in the embedded system of digital

camera (Digital camera Hardware components: 2 marks) Digital Camera Software

components – 2 marks

_Microcontroller or ASIP (Application Specific Instruction Set Processor)

_ Multiple processors (CCDSP, DSP, Pixel Processor and others)

_ RAM for storing temporary variables and stack

_ ROM for application codes and RTOS codes for scheduling the tasks

_Timer, Flash memory for storing user preferences, contact data, user address, user date of

birth, user identification code, ADC, DAC and Interrupt controller

_ The DAC gets the input from pixel processor, which gets the inputs from JPEG file for the

saved images and also gets input directly from the CCDSP through pixel processor or the

frame in present view

_ USB controller

_Direct Memory Access controller

_ LCD controller

_ Battery and external charging circuit

Digital Camera Software components – 2 marks

_ CCD signal processing for off-set correction

_ JPEG coding

_ JPEG decoding

_ Pixel processing before display




_ Memory and file systems

_ Light, flash and display device drivers

_ LCD, USB and Bluetooth Port device- drivers for port operations for display, printer and

computer communication control

Q.2] e) With suitable diagram describe the DMA process (Diagram – 2 marks, Explanation – 2 marks)

Explanation:

A DMA facilitates multibyte data set or a burst of data or a block of data is to

be transferred between the external device and system or two systems. _ A device facilitates

DMA transfer with a processing element (single purpose processor) and that device is called

DMAC (DMA Controller). Data transfer occurs efficiently between system memory and

external devices with least intervention of CPU. The system address and data bus become

unavailable to the processor and available to I/O device that interconnects using DMAC. The




DMAC has to be initialized or programmed by the processor at first. The steps in the process

of DMA are

1. The I/O device send a DMA request signal to DMAC

2. The DMAC sends a hold request to the CPU (using interrupt or hold signal)

3. CPU acknowledges that if the system memory buses are free to use and allows DMAC to

take control of buses

4. The DMAC sends Acknowledge to the I/O device and facilitates direct data transfer.

There are three modes of data transfer : 1. Single transfer at a time and then release of

the hold on the system bus. 2. Burst transfer at a time and then release of the hold on the

system bus. A burst may be of a few kB. 3. Bulk transfer and then release of the hold on

the system bus after the transfer is completed

Q.2] f) Enlist the various forms of system memory. (Various forms of system memory: (1/2 marks

each)

1. Internal RAM of 256 or 512 bytes in a microcontroller for registers, temporary data and

stack.

2. Internal ROM/PROM/EEPROM/FLASH for about 4kB to 64 kB of program

3. External RAM for temporary data and stack or internal caches in case of some

microprocessors

4. Internal flash for storing the result of processing in non volatile memory

5. Memory stick for storing images, video, songs or speeches and large storage in digital

camera and mobile systems

6. External ROM or PROM for embedding software

7. RAM memory buffers at ports

8. Caches in pipelined and superscalar microprocessors







Q.3] a) (02-marks for diagram, 02-marks for instructions)

Draw and describe the format of PSW of microcontroller 8051. Write the instructions to select

bank 1 and bank 3 of microcontroller 8051.

Program status Word (PSW):

D7 D6 D5 D4 D3 D2 D1 D0

Parity flag (p):

P=0 indicates even parity i.e. no. of 1’s in accumulator.

P=1 indicates odd parity i.e. odd no. of 1’s in accumulator.

Overflow flag (OV):

The flag is set when, there is a carry from bit 6 to bit 7 and no carry generated out of bit 7 Or when

there is no carry generated from bit 6 to bit 7, but a carry is generated out of bit 7.

Otherwise this flag is zero.

RS1 And RS0 (Register Bank select bits)

These bits are used to select one of the four register banks of internal RAM.

RS1 RS0 Register Bank

0 0 0

0 1 1

1 0 2

1 1 3

F0 : user flag ‘0’

This flag is available to user and can be used in programming the microcontroller.

AC F0 RS1 RS0 OV - P CY




Auxiliary carry flag (AC):

AC=1 if there is a carry from bit 3 to bit 4.

AC=0 if there is no carry from bit 3 to bit 4.

Carry flag (CY):

CY=1, if there is a carry generated from bit 7.

CY= 0, if there is no carry generated from bit 7.

Q.3] b) (04-marks for correct program)

Write assembly language program to exchange contents of the RAM locations from 30H in

microcontroller 8051.

START: MOV R0, #30H ; source pointer = 30H

MOV R1, #50H ; destination pointer can be any value 40H onwards

MOV R2, #0AH OR MOV R2, #10 ; load the register for counting ten

; three instructions above are for initialization carry 1 mark

LOOP: MOV A, @R0 ; take the source byte in A

XCH A, @R1 ; exchange the source byte in A with destination byte

MOV @R0, A ;move the destination byte in A to destination location

; three instructions above are for exchanging the data byte carry 2 marks

INC R0

INC R1

DJNZ R2, LOOP

; three instructions above are for looping carry 1 mark

HERE: SJMP HERE




Q3. C)

Write an assembly language program to toggle all the bits of port P1 every 200ms. Assume crystal

frequency of 12MHz.







Q.3] d) (02-marks for definition, 02-marks for features)

Define the term device driver. State its features.

A device driver is a function used by a high level language programmer and does the interaction

with the device hardware and communicates data to the device, sends control commands to the

device and runs the codes for reading the device data.

Features:

1. The driver provides a software layer interface between the application and the actual device.

2. The driver facilitates the use of a device by executing and ISR.

3. The device driver controls a device without requiring understanding of the device

configuration, control, status, data and other registers, while using the generic functions.

4. The driver translates the program generic functions for using the device and sends the

necessary commands to the device configuration and control registers.

Q3. E) Need of RTOS [2 marks]

• Real-time system is a special-purpose operating system.

• A real time system is used when rigid time requirements have been placed on the operation of a

processor or flow of data.

• Real time systems has well defined, fixed time constraints.

• Processing must be done within the defined constraints or the system will fail.

• A real time system functions correctly only if it returns the correct result within its time constraints.

• Embedded system is used in some critical application such as

1. Scientific experiments.

2. Medical imaging systems

3. Industrial control systems

4. Certain display systems

5. Automobile-engine

6. Fuel injection systems

7. Home appliance controllers

8. Weapon systems




• In all above application process must be carried out in real time. Therefore RTOS (Real time

operating system) is required in embedded system.

Specifications [any two – 1 mark each]

Reliability : it is a system which does not fail. The reliability of an Embedded system depends upon

the hardware and the software systems working together.

Predictability: RTOS is said to be predictable if it is able to complete the task within the specified

time limit.

Scalability: As RTOS can be used in various applications, they must be able to scale up or down to

suit the application.

Note: any other relevant point should be considered.

Q.4]a) i) State the function of the following pins of 8051 microcontroller. (1mark for each pin –

total 4 marks)

RST: the reset input pin resets the microcontroller 8051, only when it goes high for two or more

machine cycles.

ALE: the address latch enable output pulse indicates the valid address bits are available on their

respective pins. This ALE signal is valid only for external memory access. Normally, the ALE

pulses are emitted at the rate of one-sixth of the oscillator frequency.

EA: external access enable pin, if tied low, indicates that the 8051 can access external program

memory.for execution of programs in internal memory, the EA must be tied high.

PSEN : program store enable is an active low output signal that acts as the strobe to read the external

program memory. This goes low during external program memory access.

Q4. a) ii) (02-marks for Hard real time system, 02-marks for Soft real system)

Hard Real Time System

Hard real time systems should strictly follow the deadline of each task. When an event occurs, it

should be services within the predictable time always. Thus hard RTOS is one which has predictable

performance with no deadline miss. The pre-emptition period in the worst case should be less than

few microseconds.

Example: automobile engine control system antilock brake




Soft Real Time Systems:

A soft real time system is the one in which deadline are mostly met. Soft real time means that only

the precedence and the sequence for the task operations are defined, interrupt latencies and context

switching latencies are small but there can be a small deviation between the expected and actual

latencies. And a few deadline misses are acceptable. The pre-emptition period in worst case may be

about a few milliseconds.

Example: mobile phone, digital camera

Q4. a) iii) [2marks explanation, 2 marks diagram]

Describe the processor and memory organization in Harvard Architecture.

In Harvard architecture the address spaces for the data and for program are distinct. Hence handling

streams of data that are required to be accessed in cases of single instruction, multiple data type

instructions and DSP An instruction becomes easier. Separate data buses ensure simultaneous

accesses for instructions and data. Program segments and memory blocks for data and stacks have

separate set of addresses in Harvard architecture. Control signals and read-write instructions are also

separate for accessing the program memory and data memory.




Q.4]a) iv) (02-marks each)

Describe in brief, starvation an deadlock in an operating system.

Starvation :

Starvation is multitasking related problem. Starvation occurs as a result of non-availability of the

necessary resources. The scheduling algorithm, which is a part of the kernel, is supposed to allocate

the resources to all the processes.

Suppose a high priority process A is running before the low priority process B. So process B is not

being executed. But there is another high priority process X which is depending on results obtained

in process B. but as B is experiencing starvation and process X will not be completed in time.

Deadlock :

Deadlock is specific condition when two or more processes are waiting for each other to release a

resource. Or more than two processes are waiting for resources in circular chain.

There are four conditions for the deadlock

Mutual Exclusion

Hold and Wait

No Pre-emption

Circular wait

Deadlock can be prevented and avoided. The process should inform and request for all the resources

they need before starting up. This will help to avoid the deadlock, but it is difficult to get the prior

information of all required resources. Also it is possible to detect the deadlock. If the deadlock is

detected, a process is restarted. The resources needed for each process are known to the resource

scheduler or OS. Thus accordingly the processes are restarted in order to avoid the deadlock to take

place.

Q.4] b)i) Elaborate the features of PCI bus which makes it suitable for distributed embedded

devices.

(3 Marks for Diagram & 3 Marks for Theory Explanation)

Imp Note: Any other relevant diagram should also be given correct)




1. PCI is microprocessor independent Bus i.e. It can be used with any Microprocessor

2. PCI is fast and is an excellent match for current generation microprocessor.

3. PCI peripheral Cards supports automatic plug and play devices.

4. Standard bandwidth of PCI bus at clock Rate of 33 MHz and 32 bit capacity is equal to 133 MBps

5. It has auto configuration capabilities for peripherals i.e. IRQ and DMA channels for the data

transfer are assigned automatically.

6. Two versions of 5V & 3.3V are available as shown below.

7. The world’s best Microprocessor makers support PCI bus.




Q.4] b) ii) (02-marks for diagram (optional), 06-marks for steps)

Describe the stepwise procedure to convert C language program into a ROM image.

Steps for converting program in C to ROM image

1) A compiler generates the object code. It assembles the code according to the processor

instruction set. The C compiler for embedded system must use a code-optimiser which

optimizes the code.

2) The linker links the object code with other needed codes. The code for device and driver

management is also linked at this stage.

3) The loader (part of the operating system) finds the physical memory address available at at

given instant. The loader reallocates the code into memory after reading the .exe file. As the

program is loaded into RAM, it is ready to run.

4) The locator program realocates the linked files and creates a file for permanent location of

the codes in a standard format.

5) Lastly the ROM image is taken by the device programmer and burnt into the PROM or

EPROM.




Q.5] a) (04-marks for architecture, 04-marks for function of ALU and Boolean Processor)

Draw the internal architecture of 8051 microcontroller and state function of ALU and Boolean

Processor

ALU: Arithmetic and Logical Unit (ALU) of 8051 performs arithmetic operations like addition,

subtraction, multiplication and division.

It also performs logical operations like AND, OR, XOR, rotate, clear and complement.

It manipulates 8-bit and 16 bit data.

It manipulates 8-bit and 16 bit registers.

ALU calculates the address of jump location in relative branch execution and also compares

two bytes through subtraction.

Boolean Processor:

ALU consists of Boolean Processor.

Boolean Processor performs bit set, test, clear, complement, move and all logical operations.

It also performs internal data transfer operations.

It makes condition branching decisions.

Boolean Processor can also be used for control applications.







Q.5] b) (02-marks for mode 3, 02-marks for calculation of count value, 04-marks for program)

Describe why mode 3 of 8051 microcontroller is called split timer mode. Write an assembly

language program to generate a square wave of 4KHz. Assume clock frequency of 12 MHz. show

calculations of count to be loaded in timer.

1. Mode 3 as a Split Timer mode

2. Calculation of count value

3. Program for Square wave

In mode 3, timer 0 is split up into two independent 8-bit timers.

In this mode, TLO & THO can be used as two separate 8-bit counters. TLO uses Timer 0

control bits like INTo, C/To, GATEo, TRo & TFo.

And THO uses timer 1 control bits like TR1 & TF1.

TLO operates in timer as well as counter modes but THO operates in timer modes only.

Timer1 holds only count value.

Since in mode 3 timer0 is split into two independent 8-bit timers TLO and THO, so it is

called split timer mode.

Calculation of count value

Step-2

For 4KHZ square wave,

Tsquare = ¼ KHz = 0.25ms

= 250 µs

Step-3

1/z of it for high and low time period,

Ton = Toff = 125 µs

Step-4

Clock count = 125/1 µs = 125 cycles.

Step-1

For clock frequency of 12 MHz, 12/12MHz = 1 x 10 6

Tcrystal = 1 / 1x10 6 = 1 µs.




Step-5

Count to be loaded in timer using

Timer1 in mode 1.

65536 – 125 = 65411

=FF83 H

OR

Count to be loaded in timer using timer1 in mode 2

256-125 = 131

= 83H

Program in Mode 1

MOV TMOD, #10H

BACK : MOV TL1, #83H

MOV TH1, #OFFH

Setb TR1

AGAIN: JNB TF1, AGAIN

CLR TR1

CPL P2, 3

CLR TF1

SJMP BACK

Program in Mode 2

MOV TMOD, # 20H

MOV TH1, #83H

Setb TR1

BACK: JNB TF1, BACK

CPL P10




CLR TF1

SJMP BACK

Q.5] c) (03-marks for Os services, 01-mark for task definition, 03-marks for states of task)

Describe the various OS services in an RTOS software. Define task wih respect to RTOS and give

five states in which a task resides.

Following are the different OS services in RTOS.

1. Facilitating easy sharing of resources as per schedule and allocations. Resources mean processors,

memory, IOs, devices, virtual devices, system timer, keyboard, displays, printers and other such

resources, which processes (tasks or threads) request from the Os. No processing task or thread uses

any resource until it has been allocated by the OS at a given instance.

2. Facilitating easy implementation of the application program with the given system hardware. An

application programmer for a system can use the Os functions that are provided in given Os without

having to write the codes for the services (functions) that follow.

3. Optimally scheduling the processes on one or more CPU if available and providing an appropriate

context-switching mechanism.

4. Maximizing the system performance to let the different processes (tasks or threads) share the

resources most efficiently with protection and without any security breach.

5. Providing management functions for the processes, memory, devices and IOs.

6. Providing management and organization functions for the devices, files, virtual devices and IOs.

7. Providing easy interfacing and management functions for the network protocols and networking.

8. Providing portability of applications on different hardware configurations.

9. Providing inter operability of applications on different networks.

10. Providing a common set of interfaces that integrates various devices and applications through

standard and open systems.




Task: Task is the term used for the process in RTOS. For the embedded systems. A task is similar to

a process or thread in an OS.

A task consists of a sequentially executable program (codes) under a state control by an OS.

Task states: A task has state, which includes its status at a given instance, in the system. A task can

be considered to be in one of the five states as shown below.

1. Running (created) state: the task has been created and memory allocated to its structure. However,

it is not ready and not schedulable by the kernel.

2. Ready (active) state: The created task is ready and is schedulable by the kernel but not running at

present as another higher priority task is scheduled to run and has the system resources at this

instance.

3. Running State: Executing the servicing codes and getting the system resources at this instance. It

will run till it needs some IPC (input) or starts wait for an event or till it pre-empts by another higher

priority task than this task.

4. Block (waiting) state: Execution of the servicing codes suspends after saving the needed

parameters into its context. It needs some IPC (input) or waiting for an event or higher priority task

to block. For example, a task is pending while it waits for an input from the keyboard or file. The

scheduler then puts it in the blocked state.

signal or

message

Idle Ready Running

Blocked

Wait for signal or

message

Attached with kernel

Detached with

kernel

Created signal or message




5. Deleted (finished) state: the created task has memory de-allocated to its structure. It frees the

memory. Task has to be recreated.

A created and activated task will be in one of the three states, ready, running and blocked.

Q.6]a) (02-marks for features, 02-marks for arbitration) Elaborate features of CAN bus (any

three). Explain the Arbitration field in a CAN frame.

Features:

1. The CAN bus network has a serial line, which is bi0directional. Line is at logic 1 in its idle state,

also called the recessive state.

2. Each node has a buffer gate between an input pin and a CAN serial line. A node gets the input at

any instance from the line after sensing that instant when the line is pulled down to 0. The latter is

called dominant state.

3. Each node has a current driver circuit between output pin and serial line. The node sends a bit to

line by pulling the line 0 by its driver for a bit period.

4. A node sends the data bits as a data frame. Data frames always start with 1 and always ends with

seven zeros. Between two data frames, there are minimum three fields.

5. The CAN bus line usually interconnects to a CAN controller between the line and host node. A

host node is one that has controller for use as bus master.

Arbitration field in CAN bus:

This is the first field of 12 bits, which contains the packets 11-bit destination address and

RTR bit. (Packet means a set of bits sent on the bus)

RTR stands for (Remote Transmission Request). The receiving addressed device is at

destination address specified in 11-bit subfield and RTR is defined on the basis of whether

the data byte being sent is a data for the device or a request to the device.

11-bit address identifies the device to which data is being sent or the request being made.

When RTR bit is at 1, it means this packet is for the device at destination address.




If this bit is 0 (dominant state) it means this packet is a request for the data from the device.

Q.6] b) (02-marks for any for processors, 02-marks for features) State the various processors used

in embedded system. Which features of processor are considered while carrying out selection in

embedded system?

Following are the various processors used in embedded system based on requirement.

1. Microprocessors: used when large embedded software is to be located in external memory. RISC

processors are used for intense computing.

2. Microcontroller: used when small part of the embedded software is to be located in internal

memory and on chip parts, timers and interrupts are required.

3. Digital signal Processor (DSP): used when fast signal processing is required.

4. Embedded Processor: used when fast processing and automatic operations are required.

5. Application Specific system processors (ASSPs): used as an additional processing unit for running

application specific tasks.

6. General Purpose Processors (GPP): used when a single processor is not enough to handle tasks

that are performed concurrently. The operations of all the processors are synchronized.

For a system designer, following are the important considerations for selecting a processor.

1. Instruction set.

2. Maximum bits in an operands in a single arithmetic or logical operation.

3. Clock frequency and processing speed in Million Instructions Per Second (MIPS).

4. Processing ability and capability to handle complex algorithms.

Q.6] c) (04-marks for Explanation) Which information must be collected by the programmer

before writing the device driver program.

The embedded software programmer must design codes for:




1. Device initialization

2. Device activation

3. Device driving using interrupt service routine.

4. Resetting or device deactivation.

The following points must be considered before writing device drivers:

The device has three registers, data registers, control registers and status registers.

The device address may have more than one registers.

The devices initializes by setting the control register bits.

The device closes by resetting the control bits.

All the actions of the device are controlled by the control register bits.

The control bit controls which address corresponds to which data register at that instant.

The status flag register bit reflect the status of the device at that instant. The status flag

change after performing actions as per the device driver.

Setting of a status flag or a hardware call by a signal initiates a call for executing an ISR.

When writing a device code the addresses of each register has to be known.

What is the purpose of each bit in the control register.

What is the purpose of each status bit in the status flag register.

Which control bits and status flags are at the same address. Which status bit when set calls

the ISR.

Whether both control bits and the flag bits may be in the same register.

Whether the status flag auto resets after execution of the ISR.

Whether the control bits need to be changed before returning to the main program.

List of actions required by the driver at the data buffers, control registers, and status registers.

Q.6] d) (02-marks for IPC, 02-marks for IPC functions) What do you mean by IPC? State various

IPC functions.

IPC stands for Interprocess Communication.




IPCs in a multiprocessor system are used to generate information about certain sets of

computations finishing on one processor and to let the other processors waiting for finishing

those computations take note of the information.

IPC means that a process (scheduler, task or ISR) generates some information by signal or

value or generates an output so that it allows another process to take note or use it through

the kernel functions for the IPCs.

IPC in a multitasking system are used to set or reset a signal or token or flag or generate

message from the certain sets of computations finishing on one task and to let the other tasks

take note of the signal or get the message.

OS’s provide the software programmer the following IPC functions:

1. Signals

2. 2. Semaphore as token or mutex or counting semaphores for the inter task communication

between tasks sharing a common buffer or operations.

3. Queues and mail boxes.

4. Pipes and sockets

5. Remote procedure calls (RPCs) for distributed processes.

Q.6] e) (02-marks for synchronization, 02-marks for semaphores) State the methods of task

synchronization and describe any one in detail.

Following are the methods of task synchronization:

1. Use of a semaphore as an Event Signaling or Notifying variable.

2. Use of a semaphore as Resource key and for critical section.

3. Mutex

4. Monitors

5. Use of multiple semaphores for synchronizing the tasks.

6. P & V semaphores.




Semaphores:

In multitask system, the resource may be shared by two or more tasks as shown in the figure below

There should be proper discipline to share display for task 1 and task 2. Otherwise the display will

display matter of both tasks simultaneously. This is called resource synchronization. Figure below

gives example of task synchronization.

In this case, read operation should take place after write operation. This is called Task

Synchronization.

Semaphore is a kernel object used for resource and task synchronization.

The task takes semaphore to access shared resource.

Display

Task2 display

humidity

Task1 display

temperature

A

D

C

D

A

C

Task to write

data

Memory

Task to read

data




The task releases semaphores after accessing resource.

The allocation of semaphore is done on the basis of priority or first come first served.

If a number of tasks have to access the same resource, then the tasks are kept in queue and

each task can acquire the semaphore one by one.

There are two types of semaphores.

1. Counting semaphore.

2. Binary Semaphore.

Counting semaphore will have integer value graeter than on. Whenever a task acquires the

semaphore the value is decremented by one. When a task releases the semaphore the value is

incremented by 1.

Binary semaphore takes the value of either 0 or 1

0 shared resource is not available.

1 shared resource is available.

------------------------------***************************---------------------------------

Eds

Engineering

maharashtra

data terminal

assembly language

system clock

general purpose

rtos kernel

rtos kernel

higher priority