EDGE HARDWARE FAMILY ig t a l Main DAC out Dual … · The VITA57 standard FPGA Mezzanine Card (FMC) [8] is used for the daughtercards. Many of the selected compo-nents, such as the

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ABSTRACT A leading-edge hardware family, evolution of that successfully deployed in CERN’s Low-Energy Ion Ring (LEIR), is under development at CERN to address the LLRF needs of synchrotrons in the Meyrin site. It will be deployed in 2014 in the CERN’s PS Booster and in the medi-cal machine MedAustron. It will be then retro-fit to LEIR to standardise its LLRF implementation. It will also be used for the LLRF as well as longitudinal diagnostics implementation for the new Extra Low ENergy Antiproton (ELENA) Ring (see poster #46), a new synchrotron that will be commissioned in 2016 to further decelerate the antiprotons transferred from the CERN’s Antiproton Decelerator (AD).

The requirements for the LLRF as well as for the diagnostics systems are very demanding owing to the revolution frequency swing, dynamic range and low noise required by the cavity voltage control and digital signal processing to be performed.

CONCLUSIONS AND OUTLOOK A leading-edge hardware family is under development at CERN to ad-

dress the LLRF needs of synchrotrons in the Meyrin site. After being de-ployed in machines at CERN and abroad, it will be used for the LLRF and for the longitudinal diagnostics implementation in the ELENA ring. This hardware family provides very high processing power by making

advanced use of FPGA and DSP resources. Furthermore, it is compact, flexible and modular. Its planned wide-spread use will allow for an easier maintenance and a better spares management.

A LEADING-EDGE HARDWARE FAMILY FOR LOW-LEVEL RF AND DIAGNOSTICS APPLICATIONS IN CERN’S SYNCHROTRONS

M. E. Angoletta, A. Blas, M. Jaussi, P. Leinonen, T. Levens, J. Molendijk, J. Sanchez-Quesada, J. Simonin, CERN, Geneva, Switzerland.

-18dB

-3dB BW = 40Mhz

RF_Input 1

50W

+10dBm Full Scale+21dBm Surge Protected

-3dB BW = 40MhzADC A

LNA, G = +18dB

-18dB

-3dB BW = 40Mhz

RF_Input 2

50W

+10dBm Full Scale+21dBm Surge Protected

-3dB BW = 40MhzADC B

LNA, G = +18dB

Gain DC Offset

-18dB

-3dB BW = 40Mhz

RF_Input 3

50W

+10dBm Full Scale+21dBm Surge Protected

-3dB BW = 40MhzADC A

LNA, G = +18dB

Gain DC Offset

-18dB

-3dB BW = 40Mhz

RF_Input 4

50W

+10dBm Full Scale+21dBm Surge Protected

-3dB BW = 40MhzADC B

LNA, G = +18dB

Gain DC Offset

Converter block 1

Converter block 2

ADC CLK 0

ADC CLK 1

Power supply:

3.3V

AUX 3.3V

12V

1.8V Linear

1.8V Switched

5V Switched

-5V Switched

FRONT PANEL

LAMPS

IPMI SYSTEM

MONITOR

Gain DC Offset

I2C Bus

FM

C C

on

ne

cto

r

DAC

DAC

DAC

DAC

ADC MODULE

The ADC FMC daughtercard uses an AD9286 ADC and includes four inde-pendent digitisation channels with up to 125 MS/s and 16 bits. Its analogue front-end, based on the LT6409 IC, provides signal conditioning with DC cou-pling, low noise, low distortion and a con-trollable gain switching of 18 dB, corre-sponding to 3 LSBs. Measured wideband SFDR > 70 dB SNR > 74 dB ENOB = 12.5 bits (typical) Analogue BW = 300 MHz (max.)

Parallel / Serial

Reconstruction Filter

FM

C C

on

ne

cto

r

DDS Core

AD9858Clock distributor

and dividers.

AD9512

PLL

AD9511

Power supply:

3.3V, AUX 3.3V: From FMC

1.3V Linear regulator

10MHz Reference input

Limiter

998.0 – 1001.0 MHz

VCO

20dB

BALUN

BALUN

Squarer: ADCMP553

Limiter

TAG pulse

generator

logic

Loop Filter

50W

0dBm nominal level

Parallel / Serial

Reconstruction Filter

DDS Core

AD9858Clock distributor

and dividers.

AD9512

Limiter

TAG pulse

generator

logic

SPI Control bus

SPI Control bus

SPI Control bus

P

N

P

N

Channel 1

Tag + RFCLK

Frontpanel

Connector

eSATA

P

N

P

N

Channel 2

Tag + RFCLK

Frontpanel

Connector

eSATA

CH1 TAG Trigger

CH1 DTAG Trigger

CH1 Tag Clock

CH1 Tag to Carrier

CH1 RF Clock to Carrier

CH2 TAG Trigger

CH2 DTAG Trigger

CH2 Tag Clock

CH2 Fast Clock

CH2 RF Clock

CH2 TAG

CH1 TAG

CH1 RF Clock

CH2 Fast Clock

CH1 Fast Clock

100W

100W

100W

100W

Low noise

power

supply

FRONT

PANEL

LAMPS

IPMI SYSTEM

MONITOR

I2C Bus

1GHz Master

Clock

1GHz Master

Clock

88 Full-Duplex Gigabit channelsParallel Data

0 = GTP Dual Tile Y index. Ex: GTP_DUAL_X0Y0

P1

P2

P0

VME 64x

VXS

FMC0

6

SRAM 14Mx18

eS

AT

A

Front

RF1 Clock& Tag

A(31-24)D(31-16)

FPGAXC5VLX110T-1FF1136

1

A

Main

FPGAXC5VSX95T-1FF1136

1

A

FMC

4

FMC2

4

DSPADSP-21369KBPZ-3A

Triggers I+O(15-0)

A(23-1)D(15-0)etc.

160

160 852

90

90

14

e-W

ISH

BO

NE

Tile 6, 7

Tile 4, 5

Tile(0:3)

Tile(4:7)Tile(0:3)

0

12

01 2

SRAM 11Mx4x18

SRAM 01Mx4x18

SRAM 04Mx18

200

CY7C1474V33-167BGC

CY7C1472V33-167BGC

RF+Tag

JT

AG

JT

AG

PWR

Clocks

JTAG

F0 OKF2 OKSTAT

EDA-0XXXX

RTM I2C

2

RF Clock & TAG

DAC MODULE

The DAC FMC daughtercard is based on the AD9747 DAC and allows four independent digital-to-analogue conversion channels with 16 bits resolution in the conversion and programmable gain switching of 18 dB. The output is DC coupled, with a 40 MHz ana-logue bandwidth and a full scale, peak output voltage of 3.6 V. The sampling rate of the DAC mezzanine can go up to 250 MS/s and the front-end, like the ADC board, includes low distortion and low noise electronics.

Measured wideband SFDR: > 60 dB

Gain switching settling time: < 30 nS

DDS MODULE

The DDS FMC daughtercard uses the AD9858 IC as the DDS core; it is a high quality, compact clock generator, featuring two independ-ent channels synchronised to the same reference and allowing up to 232 mHz frequency step resolution.

Typical jitter figure: ~800 fS (max. 2 pS for certain DDS output frequencies).

Output divider combinations: 1:1 to 1:32

Frequency resolution: 32 bits

Generates the TAG signal to synchro-nize all DDC & SDDS channels.

VXS CARRIER BOARD The VXS-DSP-FMC Carrier board is a 6U unit board carrying:

A SHARC Digital Signal Processor (DSP) ADSP-21368

A Virtex 5 Field Programmable Gate Arrays (FPGAs) XC5VLX110T (Main FPGA)

A Virtex 5 FPGA XC5VSX95T with DSP capabilities (FMC FPGA)

Two dedicated full-duplex VXS chan-nels from each Carrier board routing to Switch B distribute RF clock + TAG.

Six full-duplex VXS channels, bonded to form three 32 bit data paths, to transfer 10b8b-encoded data between Carrier boards at a raw link rate of 2 Gbit/s or 100 MS/s (32 bit).

The Carrier board can host up to two FMC daughtercards with a high-pin count format. It in-cludes memory banks for observation purposes: two 4Mx18 bit banks clocked at 100 MS/s and two, 1Mx4x18 bit banks clocked at the RF clock frequency.

VXS SWITCH MODULE The VXS Switch board allows using the VXS bus to interconnect

boards via full-duplex Giga-bit serial links. Each VXS crate is fitted with two Switch boards each positioned at a starpoint, called “A” & “B” allow-ing to fully route a total of eight full-duplex up-to 3.125 Gbit/s from any payload slot to another. The Switch boards also implement a multi-cast capability used to distribute RF Clock + Tag across the VXS fabric.

RTM MODULE The RTM is the VXS-DSP-FMC Carrier companion board. Installed in

the rear side of the VXS crate and interfaced to the Carrier via the J2/P2 connector, it carries all major secondary power supplies needed by the Carrier. The RTM front panel provides sixteen general purpose digi-tal inputs and eight general-purpose digital outputs using stacked LEMO 00 connectors.

Module top side with dimension [cm]

Typical HD2 and HD3 for a FS input

OVERVIEW

The new hardware family [1] developed by CERN’s RF Group, is an evolution of that successfully operational in CERN’s LEIR since 2006 [2]. It will be deployed in the PSB [3] and MedAustron [4] in 2014, retrofit to LEIR in 2015 and deployed in ELENA [5] in 2016. Other synchrotrons will soon follow [6].

The family provides a very high processing power, is compact, flexible and modular.

The hardware family is based upon the VME Switched Serial (VXS) [7] enhancement of the VME64x standard, which supports switched serial fabrics over a new, high-speed P0 connector.

The VITA57 standard FPGA Mezzanine Card (FMC) [8] is used for the daughtercards.

Many of the selected compo-nents, such as the mother-board’s Virtex 5 FPGAs and the daughtercards’ 16-bit ADCs and DACs, are amongst the most advanced units on the market.

Module top side with dimension [cm]

Typical HD2 and HD3 for a FS output

VXS Carrier with two daughtercards installed

VXS Carrier block diagram

DAC FMC block diagram

Typical low frequency spectral noise density

ADC FMC Block diagram

DDS FMC block diagram

Typical phase noise plot for a 125MHz output.

Module top side with dimension [cm]

TAG + Clock signals—encoding scheme.

-90dBc

-150dBc

Dual DAC chip

FMC

connector

(HPC)

Legend

HPC = High Pin Count (400-pins)

FMC = FPGA Mezzanine Card (Vita 57 standard)

Switch

Fc = 40MHz

16

Digital

data CH1

IIC-bus

Secondary IIC-bus

EEPROM Voltage/temp Monitor Serial number

Front panel

LED control

Power good

indication

4x

SMC

G = 1G = 7

RF out

50ohm

4CH ADC

CH1-4

SPI-link

DAC control via SPI-link

CLK max. 250MSPS

Power

distribution

IIC-to-1-wire master

1-wire

SW control

Main DAC1

AUX DAC1

Main DAC2

AUX DAC2

16

Digital data CH2

Main DAC out

AUX DAC out

Dual DAC chip16

Digital

data CH3

DAC control via SPI-link

CLK max. 250MSPS

Main DAC1

AUX DAC1

Main DAC2

AUX DAC2

16

Digital

data CH4

Main DAC out

AUX DAC out

Main DAC out

AUX DAC out

Main DAC out

AUX DAC out

18dB

attOffset

compensation

The new hardware in a test system installed in CERN’s PSB during the 2012—2013 run

REFERENCES [1] M. E. Angoletta et al., “A Leading-Edge Hardware Family for Diagnostics

Applications and Low-Level RF in CERN’s ELENA Ring”, IBIC’13, Ox-

ford, September 2013, TUPF28.

[2] M.E. Angoletta et al., “CERN’s LEIR Digital LLRF: System Overview and

Operational Experience”, IPAC’10, Kyoto, May 2010, TUPEA057, p. 1464.

[3] M. E. Angoletta et al., “CERN’s PS Booster LLRF Renovation: Plans and

Initial Beam Tests”, IPAC’10, Kyoto, May 2010, TUPEA056, p. 1461.

[4] http://www.medaustron.at/en/

[5] T. Eriksson (editor) et al., “ELENA, an Updated Cost and Feasibility

Study”, CERN-BE-2010-029.

[6] T. Eriksson et al., “Upgrades and Consolidation of the CERN AD for Oper-

ation During the Next Decades”, IPAC2013, Shanghai, China, May 2013,

WEPEA063, p. 2654.

[7] http://www.vita.com/fmc.html

[8] http://www.vita.com/vxs.html

[9] Intel Hewlett-Packard NEC Dell, “-IPMI- Intelligent Platform Manage-

ment Interface Specification Second Generation”, June 2009.

VXS interconnect structure with two Switch boards

Several communication channels are implemented in the Main FPGA: a) VME64x (A32/D32); b) DSP (A16/D32); c) Carrier-to-Carrier (VXS full-duplex dual 32 bit link with a transfer rate of 100 MS/s); d) communication & data exchange with the FMC FPGA (full-duplex 32 bit Gigabit links); e) I

2C link to control the RTM configuration and LEDs; f) I

2C link to control the board front-panel LEDs; g) I

2C to

control the VXS Switch module; h) I2C links to exchange IPMI [9] information with the FMC FPGA. The communication architecture is

configured such that no arbitration is required on any of the link nor bus interfaces for simplicity and overall system reliability.