Ch 10 MOS Digital – Pt. 1 ECES 352 Winter 2007 Ch 10 MOSFETs and MOS Digital Circuits * Examine MOSFET use in inverters * Inverter = two transistors in series Input to gate of driver (at least) Second transistor acts as load Output off connection between transistors * NMOS Inverters Enhancement driver, resistor load Enhancement driver and load Enhancement driver, depletion load * CMOS Inverter N channel driver, P channel load * Analyze to find inverter performance: * Voltage transfer characteristic * Noise margins * Power dissipation * Switching speed Driver Load V i V o
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ECES 352 Winter 2007 Ch 10 MOS Digital – Pt. 1 1 Ch 10 MOSFETs and MOS Digital Circuits *Examine MOSFET use in inverters *Inverter = two transistors in.
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Ch 10 MOS Digital – Pt. 1
1ECES 352 Winter 2007
Ch 10 MOSFETs and MOS Digital Circuits* Examine MOSFET use in inverters
* Inverter = two transistors in series Input to gate of driver (at least) Second transistor acts as load Output off connection between
* Analyze to find inverter performance: * Voltage transfer characteristic * Noise margins * Power dissipation * Switching speed
Driver
Load
Vi
Vo
Ch 10 MOS Digital – Pt. 1
2ECES 352 Winter 2007
MOSFETs and MOS Digital Circuits
* Inverters combined in series and parallel to form digital circuits such as AND’s, NAND’s, OR’s, NOR’s, flip-flops, etc.
* Understanding inverter operation is basic to understanding and describing digital circuit operation
* Also important in modifying their design to enhance their performance, e.g. speed, power dissipation, susceptibility to noise, and fan-out capability
Ch 10 MOS Digital – Pt. 1
3ECES 352 Winter 2007
N-Channel Enhancement MOSFET
* Positive voltage on gate attracts electrons to surface to form “induced channel of electrons”.
* Channel forms path for electron flow between source and drain.
* Without channel, have back-to-back diodes in series between source and drain so negligibly small current
Ch 10 MOS Digital – Pt. 1
4ECES 352 Winter 2007
N-Channel Enhancement MOSFET* Basics of device operation
VTh = threshold voltage
No channel of electrons for vGS < VTh
No current for vGS < VTh
VTh > 0 for enhancement mode n-channel MOSFET
VTh
Saturation mode operation (large VDS)
iDS
vGS
Increasing vGS
iDS
vDS
Increasing vGS
Channel formation for vGS > VTh
Ch 10 MOS Digital – Pt. 1
5ECES 352 Winter 2007
N-Channel Enhancement MOSFET
iDS
vDS
Constant vGS
curve
vDS sat = v GS – VTh
Ch 10 MOS Digital – Pt. 1
6ECES 352 Winter 2007
N-Channel Enhancement MOSFET* Cutoff region (vGS < VTh)
* Triode region (vDS < vDSsat)
* Triode-saturation boundary at vDS = vDSsat = vGS - VTh OR
where vGS - vDS = VTh
* Saturation region (vDS > vDSsat)
flow)current the(along
channel theoflength L
flow)current ular to(perpendic
channel theofwidth
strength field electric
elocityelectron v
E
v
secin channel in themobility electron
2
1
n
2
W
/Vcm
tC
L
WCK
n
ox
oxox
oxn
]2[ 2DSDSThGSD vvVvKi
2ThGSD VvKi
where
0DiiDS
vDS
vDS sat = v GS – VTh
Ch 10 MOS Digital – Pt. 1
7ECES 352 Winter 2007
* Basics of device operation VTh < 0 for depletion mode n-
channel MOSFET VTh = threshold voltage Channel exists even when no bias
is applied to the gate, i.e for vGS = 0.
Drain current can flow for vGS = 0 and for any vGS > VTh.
* Only difference from enhancement mode device is that the gate voltage may be negative. But vGS must still be larger than the threshold voltage for the device to be on!
NMOS Inverter (E-MOSFET + Resistor Load)* Analyze to find inverter
performance: voltage transfer characteristic, noise margins, power dissipation and switching speed
* Transistor characteristics (driver)
KR
VV
D
DD
2
5
vi
+
_
vo
+
_
2
272
27
614
ox
6
2
/3.0
)1
5)(/1077.1sec)(/700(
2
12
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/1077.1
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VmA
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L
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cmFx
cmxcmFxxC
tC
cmxnmt
Vcm
mmW
VV
oxn
ox
oxox
ox
n
Th
Ch 10 MOS Digital – Pt. 1
11ECES 352 Winter 2007
* Device operation in inverter Load line comes from connections of transistor in the circuit
For a given vGS, e.g. 3V (=VTh+2V), transistor’s operating point is where load line crosses vGS = 3V transistor characteristic.
Transistor must operate on load line as gate voltage changes. At points A, the transistor is in cutoff mode (small vGS). Between points A and C (larger vGS), transistor is in saturation mode. Between points C and D (even larger vGS), transistor is in triode
mode.
NMOS Inverter - Load Line
VDD
KR
VV
D
DD
2
5
2/3.0
0.1
VmAK
VVTh
A.C
D
DS
D
DDD
DSDDDDo
R
v
R
Vi
orviRVv
DVDD/RD
=5V/2K=2.5 mA
Load line
+
_
vo = v DS
iDS
vDS
Increasing vGS
Ch 10 MOS Digital – Pt. 1
12ECES 352 Winter 2007
* Voltage transfer characteristic Vo versus Vi
* Region I (A to B) 0 < Vi < VTh
iD = 0 since transistor is off, i.e. in cutoff.
NMOS Inverter (E-MOSFET + Resistor Load)
vi
+
_
vo
+
_
vi
vo
00
A B
KR
VV
D
DD
2
5
2/3.0
0.1
VmAK
VVTh
5V
VTh=1V
A to B
.5V
I
iDS
vDS
Ch 10 MOS Digital – Pt. 1
13ECES 352 Winter 2007
* Region II (B to C) Vi > VTh and iD > 0 since transistor is on.
iD is increasing as Vi = vGS increases
Transistor is operating in saturation mode since vDS > vDSsat
NMOS Inverter (E-MOSFET + Resistor Load)
vi
+
_
vo
+
_
vi
vo
00
A B
KR
VV
D
DD
2
5
2/3.0
0.1
VmAK
VVTh
5V
VTh =1V
A to B
.5V
C
V
VvV
VvV
mAKViRVv
iVvV
mAVvKi
i
iRDDDo
RiThGSD
2
22
22
2
16.05
13.025
13.0
C
I II
vDSsat
iDS
vDS
Ch 10 MOS Digital – Pt. 1
14ECES 352 Winter 2007
* Where is point C and what are the corresponding values of Vi and Vo?
* At C, transistor is operating at the edge of the saturation mode where
NMOS Inverter (E-MOSFET + Resistor Load)
vi
+
_
vo
+
_
vi
vo
00
A B
KR
VV
D
DD
2
5
2/3.0
0.1
VmAK
VVTh
5V
VTh
A to B
.5V
C
VVVV(at C)v(at C)vThen
V(at C)vsoandVorV
KVmA
VKVmA
KR
VKR-(at C) v
v
RVvKVVv
RVvKViRVv
VvVvvvv
Thi
i
D
DDDi
i
DThiDDThi
DThiDDRDDDo
ThiThGSDSsatDSo
2.10.12.2
2.2)possiblenot(8.32.22.1
6.31
2)/3.0(2
)5(2)/3.0(411
2
411
get wefor Solving
get we
equation Line Load with combining So
0
2
2
C
2.2V
1.2V
I II
iDS
vDS
Ch 10 MOS Digital – Pt. 1
15ECES 352 Winter 2007
* Region III (C to D) Vi > VTh and iD > 0 since transistor is still on.
Transistor is operating in triode mode so
NMOS Inverter (E-MOSFET + Resistor Load)
vi
+
_
vo
+
_
vi
vo
0
0.95V
A B
KR
VV
D
DD
2
5
2/3.0
0.1
VmAK
VVTh
5V
VTh
A to B
.5V
C
C
I II III
D
K
RKV
RVvK
K
RVvK
v
R
V
RVvKvKv
R
vVii
andvvVvKvvVvKi
D
DD
DThi
DThi
o
D
DD
DThioo
D
oDDRD
ooThiDSDSThGSD
2
412
2
12
01
2
get wegrearrangin and combining so
]2[]2[
2/12
2
22
DAt D, vi = 5V and vo= 0.95V or 8.7V (not possible).
1.2V
2.2V
iDS
vDS
Ch 10 MOS Digital – Pt. 1
16ECES 352 Winter 2007
Noise Margins for NMOS Inverter (E-MOSFET + Resistor Load)
* Noise margin for low state Measures degree of
inverter sensitivity to noise for the low state, i.e. how large an input noise signal causes problems at output.
Assumes identical inverter providing input signal
Noise Margin = NML = VIL - VOL where
VOL = output voltage when input set to VOH
VIL = maximum input voltage recognized as a low input
For this inverter design, NML is very low (0.05V) !
Can change by changing R or VTh or transistor’s K.
vi
vo
VOL=0.95V
VOH = 5V
VIL=VTh
= 1.0V
5V
Vi =VOL
= 0.95V
NML= VIL - VOL
= 1.0 V- 0.95 V = 0.05 V
Normal low input signal size without noise.
Input signal size with noise that causes problems..
high lowhigh
Ch 10 MOS Digital – Pt. 1
17ECES 352 Winter 2007
Noise Margins for NMOS Inverter (E-MOSFET + Resistor Load)
* Noise margin for high state Measures degree of inverter
sensitivity to noise for the high state, i.e. how large a negative input noise signal causes problems at the output.
Assumes identical inverter providing input signal
Noise Margin = NMH
= VOH - VIH where VOH = output high voltage
when input set to VOL
VIH = minimum input voltage recognized as a high input
Can change by changing R or VTh or transistor’s K.
How do we find VIH?
vi
voVOH = 5V
VIH
5V
NMH = VOH - VIH
Vi=VOH
VOL= 0.95V
Slope = -1
Normal high input signal size without noise.
Input signal size with noise that causes problems.
low highlow
Ch 10 MOS Digital – Pt. 1
18ECES 352 Winter 2007
* Noise margin for high state Noise Margin = NMH = VOH - VIH
where VOH = output high voltage when
input set to VOL
VIH = minimum input voltage recognized as a high input
Can find VIH by using expression derived for region II
This VIH is less than 2.2V where FET enters region III, so our guess that device at VIH is in region II is okay.
Noise Margins for NMOS Inverter (E-MOSFET + Resistor Load)
vi
voVOH = 5V
VIH
5V
NMH = VOH - VIH
= 5 V- 1.83 V = 3.17 V
Vi=VOH
VOL=0.95V
Slope = -1
VVmAK
V
KRVVv
soVvKRdv
dv
VvKRViRVv
DThIHi
ThiDi
ThiDDDRDDDo
83.1)/3.0)(2(2
11
2
1
120
2
C
2.2V
II III
low highlow
Ch 10 MOS Digital – Pt. 1
19ECES 352 Winter 2007
Noise Margins for NMOS Inverter (E-MOSFET + Resistor Load)
* Alternate analysis for Noise margin for high state
Noise Margin = NMH = VOH - VIH
Can find VIH by using expression derived for region III
The noise margin for the high state NMH now becomes smaller.
NMH = VOH – VIH = 5 V- 4.5 V = 0.5 V This is smaller than the previously
determined value, but is still a factor of ten larger than that for the low state NML = 0.05 V.
vi
voVOH = 5V
VIH
5V
NMH = VOH - VIH
= 5 V- 4.5 V = 0.5 V
VOH
VOL= 0.95V C
2.2V
II III
IHi
i
io
D
DD
DThioo
VVvso
v
vforgetweVvpickwe
R
V
RVvKvKv
5.4
02
5
2
1)1)(3.0(2)1(3.0
,1If
01
2
2
2
VO= 1.0 V
low highlow
Ch 10 MOS Digital – Pt. 1
20ECES 352 Winter 2007
* Input low, output high. Transistor is off, iD = 0. Power dissipation PH = 0
* Input high (5 V), output low (0.95 V).
* Average Static Power Dissipation P
Power Dissipation for NMOS Inverter (E-MOSFET + Resistor Load)
vi
+
_
vo
+
_
vi
vo
0
0.95V
A B
KR
VV
D
DD
2
5
2/3.0
0.1
VmAK
VVTh
5V
VTh
A to B
.5V
CC
I II III
D
D
1.2V
2.2V
mWmAVP
mAK
VVi
VDvv
L
D
DSo
10)0.2(5
0.22
95.05
95.0)(
mWmW
PPP LH 52
10
2
1
iDS
vDS
Ch 10 MOS Digital – Pt. 1
21ECES 352 Winter 2007
Propagation Delays and Switching Times for NMOS Inverters
* Previously considered static characteristics of inverters, e.g. Voltage transfer characteristic.
* Switching performance is also of interest.
* Finite switching times are due to the capacitance load on the output and RC charging and discharging times.
* Capacitance load comes from: 1) gate capacitance of subsequent inverters to which the output is connected and 2) capacitance of interconnect wires to inputs of other gates.
* Propagation delays tPHL = output high to low tPLH = output low to high tP = (1/2)(tPHL+ tPLH) )
defines the speed of the inverter.
vi
+
_
vo
+
_
t
vo
vi
t
Ch 10 MOS Digital – Pt. 1
22ECES 352 Winter 2007
Propagation Delays and Switching Times for NMOS Inverters
* Output goes from Low to High Drive transistor turns off Load resistor provides current to
charge up C.
tPLH = time to charge to the midpoint ½(VOH+VOL) = 1/2(5V + 0.95V) = 3.0V
C
iD= 0
iR
iC
Driver
Load
KRD 2
Resistor
24
1
11
1
101.3
1 L ,5
0.1
V
AxK
mmW
VVTh
CRtOLDDDDo
t
D
tv
V oDD
o
D
oDDR
oC
D
o
OL
eVVVtv
dtCRvV
dv
R
vVi
dt
dvCi
/
0
)(
1
vi=VOL
t
+
_
vo
+
_
vo
VDD
VOL=0.95V
sec140.35
95.05ln)10(2
0.3ln
,10
0.3)( /
nVV
VVpFK
VV
VVCRt
pFCFor
VeVVVtv
DD
OLDDDPLH
CRtOLDDDDPLHo
DPLH
tPLH
3V
Ch 10 MOS Digital – Pt. 1
23ECES 352 Winter 2007
Propagation Delays and Switching Times for NMOS Inverters
* Output goes from High to Low Drive transistor turns on But load resistor continues to
provide some current so
tPHL = time to discharge from VOH = VDD to
(VOH+VOL) = 1/2(5V + 0.95V) = 3.0V
C
iD
iR
iC
Driver
Load
KRD 2
Resistor
24
1
11
1
101.3
1 L ,5
0.1
V
AxK
mmW
VVTh
CRtOHDDDDDDDDo
t
D
tv
V DDoDD
o
ThOHThiD
DD
oDDDR
oC
D
o
OH
eVRiVRiVtv
dtCRRivV
dv
VVKVvKi
iR
vVii
dt
dvCi
/
0
22
)(
1
!constant a
t
+
_
vo
+
_
vo
VDD
VOL=0.95V
sec5.40.3)2(55
5)2(55ln)10(2
0.3ln
,10
0.3)( /
nVKmAV
VKmAVpFK
VRiV
VRiVCRt
pFCFor
VeVRiVRiVtv
DdDD
OHDdDDDPHL
CRtOHDDDDDDDDPHLo
DPHL
tPHL
3V
vi =VOH
mAVVV
Ax
VVKVvKi ThOHThiD
5)15(101.3 22
4
22
vi = VOH
Ch 10 MOS Digital – Pt. 1
24ECES 352 Winter 2007
Propagation Delays Time for NMOS Inverters
* Output goes from Low to High Drive transistor turns off Load resistor provides current to
charge up C.
* Output goes from High to Low Drive transistor turns on to discharge
the capacitor but Load resistor continues to provide
current.
* Average Propagation Time tPD
sec5.40.3
ln nVRiV
VRiVCRt
DdDD
OHDdDDDPHL
C
iD= 0
iR
iC
Driver
Load
KRD 2
Resistor
24
1
11
1
101.3
1 L ,5
0.1
V
AxK
mmW
VVTh
vi=VOL
t
+
_
vo
+
_
voVDD
VOL=0.95V
sec140.3
ln nVV
VVCRt
DD
OLDDDPLH
tPLH
3V
sec10sec14sec5.42
1
2
1nnnttt PLHPHLPD
vo
VDD
VOL=0.95V
tPHL
3V
t
Ch 10 MOS Digital – Pt. 1
25ECES 352 Winter 2007
Propagation Delay for NMOS Inverter
* Output goes from High (VOH = 5V) to Low (VOL = 0.95V)
Driver transistor Q
(starts from P R S T) At outset, Q is off (P), and
vDS1 = vo = VOH = 5V, vi < VTh
Driver turns on (P to R) when vGS is switched to VOH = 5 V.
Driver initially is in saturation mode, then eventually moves into triode as capacitor discharges and vo (= vDS) decreases
Q moves along constant vGS characteristic (R S T).
Ends at (T) in triode region, where vDS = vo = VOL = 0.95V.
Load resistor continuously providing current opposing discharge of capacitor.
* Output goes from Low to High Drive transistor is off
(vi = 0.95 V < VTh = 1.0 V Transistor moves from T P as the
output voltage vo rises to 5 V.
C
iD
iR
iC
Load
Driver
Driver
P
SR
T
vo =VOH = 5 V
vi = vGS = VOH =5 V
vo=VOL
=0.95V
iDS
vDS
Ch 10 MOS Digital – Pt. 1
26ECES 352 Winter 2007
* Resistor’s Undesirable Effects
Wasted power for transistor on (output low)
Resistor provides limited charging current
Maximum iR = 2 mA, but iR decreases
as vo rises.
iR slows down discharge of C when
output goes low.
Power-Delay Product for NMOS Inverter (E-MOSFET + Resistor Load)
* Average Propagation Time tPD
* Average Power Dissipation P
* Power-Delay Product DP
C
sec10sec14sec5.42
1
2
1nnnttt PLHPHLPD
mWmW
PPP LH 52
)100(
2
1
pJnmWtPDP PD 50sec)10(5
mWPmAK
VV
R
VVi L
D
OLDDR 10 and 0.2
2
95.05
* Problems with this inverter: * Unequal noise margins! NML = 0.05 V, NMH = 3.17 V * Unequal transition times! τPHL = 4.5 nsec, τPLH = 14 nsec * Significant power dissipation!Can we improve on this inverter ?