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Cl k jitt• Clock jitter– Temporal variations in consecutive edges of the clock signal; modulation + random noiseg ;
– Cycle‐to‐cycle (short‐term) tJS– Long term tJL
• Variation of the pulse width – Important for level sensitive clocking
GMU, ECE 680 Physical VLSI Design 6
Clock Skew and JitterClock Skew and Jitter
ClkClktSK
Clk tJS
• Both skew and jitter affect the effective cycle time
• Only skew affects the race margin
Tclk + δ – 2tjitter > tc ‐ q + tlogic + tsu
δ 2t t t t
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GMU, ECE 680 Physical VLSI Design 7
δ + 2tjitter + thold < tc – q, cd + tlogic, cd
Clock SkewClock Skew
# of registersg
Earliest occurrenceof Clk edge
Latest occurrenceof Clk edgeg
Nominal – /2g
Nominal + /2
Clk delayInsertion delayMax Clk skew
GMU, ECE 680 Physical VLSI Design 8
Positive and Negative SkewPositive and Negative Skew
R1 R2 R3R1In Combinational
LogicD Q
tCLK1CLK tCLK2
R2D Q Combinational
Logic
tCLK3
R3• • •D Q
(a) Positive skew
delay delay
R1In Combinational
LogicD QR2D Q Combinational
Logic
R3• • •D Q
(b) Negative skew
tCLK1
delay
tCLK2 tCLK3
delay CLK
( ) g
GMU, ECE 680 Physical VLSI Design 9
Positive SkewPositive Skew
CLK1TCLK
TCLK
1 3CLK1
CLK2
CLK2
th
2 4
Launching edge arrives before the receiving edge
GMU, ECE 680 Physical VLSI Design 10
Negative SkewNegative Skew
TCLK
TCLK +
1 3CLK1 1 3
CLK2
2 4
Receiving edge arrives before the launching edge
GMU, ECE 680 Physical VLSI Design 11
Timing ConstraintsTiming Constraints
R1 R2R1D Q Combinational
LogicIn
t
R2D Q
tCLK tCLK1 tCLK2
tc qtc q, cd
tlogictlogic, cdq
tsu, tholdg
Minimum cycle time:T T ‐ = tc‐q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )
GMU, ECE 680 Physical VLSI Design 12
Timing ConstraintsTiming ConstraintsR1
CombinationalInR2
D Q CombinationalLogic
CLK tCLK1
D Q
tCLK2
tc qtc q, cdtsu, thold
tlogictlogic, cd
su, hold
Hold time constraint:t(c‐q, cd) + t(logic, cd) > thold +
Worst case is when receiving edge arrives lateRace between data and clock
GMU, ECE 680 Physical VLSI Design 13
Impact of JitterImpact of Jitter
TC LK
CLK-tji tter
t j itter
tji tter
ICombinationalREGS
CLK
In Logic
tc-q , tc-q, cdt log ict l i dq q, log ic, cdtsu, thold
tjitter
GMU, ECE 680 Physical VLSI Design 14
Longest Logic Path in Edge‐Triggered Systems
ClkTSU
TJI +
T
TClk-Q TLM
Latest point of launching
Earliest arrivalf lof launching of next cycle
GMU, ECE 680 Physical VLSI Design 15
Clock Constraints in Edge‐Triggered Systems
If launching edge is late and receiving edge is early the data will not be too late if:If launching edge is late and receiving edge is early, the data will not be too late if:
T + T + T < T T T Tc-q + TLM + TSU < T – TJI,1 – TJI,2 -
Minimum cycle time is determined by the maximum delays through the logic
2Tc-q + TLM + TSU + + 2 TJI < T
Skew can be either positive or negativeSkew can be either positive or negativeGMU, ECE 680 Physical VLSI Design 16
Shortest PathShortest Path
E li t i t
Clk
Earliest point of launching
TClk-Q TLm
ClkClkTH
Data must not arrivebefore this timeNominal
clock edge Example 10.1
GMU, ECE 680 Physical VLSI Design 17
Clock Constraints in Edge‐Triggered Systems
If launching edge is early and receiving edge is late:
4-Phase Handshake Protocol4 Phase Handshake ProtocolImplementation using Muller‐C elements
Senderlogic
Receiverlogic
Data
Data ready Data accepted
ReqS
Ack
C C
Handshake logic
GMU, ECE 680 Physical VLSI Design 56
Self‐Resetting LogicSelf Resetting Logic
PrechargedLogic Block
PrechargedLogic Block
PrechargedLogic Block
completiondetection
(L1)
completiondetection
(L2)
completiondetection
(L3)
(L1) (L2) (L3)
VDDVDD
Post‐charge
A B C
intout
logic
GMU, ECE 680 Physical VLSI Design 57
Clock‐Delayed DominoClock Delayed DominoGND
CLK1 CLK2 (to next stage)
V
Pulldown
Q1 (also D2)
D1
VDD
PulldownNetwork
D1
GMU, ECE 680 Physical VLSI Design 58
Asynchronous‐Synchronous Interfacey y
fin
Asynchronoussystem
Synchronous system
fCLK
Synchronization
GMU, ECE 680 Physical VLSI Design 59
Synchronizers and ArbitersSynchronizers and Arbiters
• Arbiter: Circuit to decide which of 2 events occurred first
• Synchronizer: Arbiter with clock as one of the inputs
• Problem: Circuit HAS to make a decision in limited time which decision is not importanttime ‐ which decision is not important
• Caveat: It is impossible to ensure correct operation• But we can decrease the error probability at theBut, we can decrease the error probability at the expense of delay
GMU, ECE 680 Physical VLSI Design 60
A Simple SynchronizerA Simple Synchronizer
CLK
int I1D Q
I2
D Q
I2CLK
• Data sampled on rising edge of the clock
• Latch will eventually resolve the signal value• Latch will eventually resolve the signal value,but ... this might take infinite time!