ECE606: Solid State Devices Lecture 24 MOSFET non-idealitiesee606/downloads/ECE606_f12_Lecture24.pdfsubstrate work function, trapped charges, interface states. 3) Although nonindeal

Klimeck – ECE606 Fall 2012 – notes adopted from Alam

ECE606: Solid State DevicesLecture 24

MOSFET non-idealities

Gerhard [email protected]


Outline

2

1) Flat band voltage - What is it and how to measure it?

2) Threshold voltage shift due to trapped charges

3) Physics of interface traps

4) Conclusion

Ref: Sec. 16.4 of SDF Chapter 18, SDF


Outline

3




4) Conclusion


,

( )IT sM M Fth th ideal

O OMS

O

QQ QV V

C C C

φγφ= + − − −

( )( ) ~= −D D DD G thI V V V Vα

1< α < 2


(1) Idealized MOS Capacitor

4

Substrate (p)yχs

Φm

χi

EC

EVEF

p semiconductormetal insulator

Vacuum level

,( )= −i ox G th idealQ C V V

Recall that

,

2=

= −s F

Bth ideal s

ox

QV

C ψ φ

ψ

In the idealized MOS capacitor, the Fermi Levels in metal and semiconductor align perfectly so that at zero applied bias, the energy bands are flat


Potential, Field, Charges

5

χs

Φm

χiV

E

Vbi=0 ρ

x

x

x

No built in potential, fields or charges at zero applied bias in the idealized MOS structure


Real MOS Capacitor with ΦΦΦΦM < ΦΦΦΦS

6

ΦM = qφm χS

ΦS

qψ S > 0

EC

EV

EF

EVAC

EC

EV

EF

Note the difference

Do we need to apply less or more VG to invert the channel ?

In reality, the metal and semiconductor Fermi Levels are never aligned perfectly � when you

bring them together there is charge transfer from the bulk of the semiconductor to the

surface so that we have alignment


Physical Interpretation of Flatband Voltage

7

ψS = 0 flat band

EC

EV

EF

0FB ms biV Vφ= = − <

VG = VFB < 0

EC

EV

EF

VG = 0

Vbi = −φms > 0+ −

The Flatband Voltage is the voltage applied to the gate that gives zero-band bending in the MOS structure. Applying this voltage nullifies the effect of the built-in potential. This voltage needs to be

incorporated into the idealized MOS analysis while calculating threshold voltage


How to Calculate Built-in or Flat-band Voltage

8

χs

Φm

Vacuum level

EV

EF

EC

( )= + − ∆ −

=

Φ

≡bi g p

FB MS

s MqV E

qV φ

χ qVbi

( )i ox G thQ C V V= −

Therefore,

2

= − −

Bth F

oxFB

QV

CVφ

The presence of a flatband voltage lowers or raises the threshold voltage of a MOS structure. Engineering question � Is it desirable to have a metal having a work function greater or less

than the electron affinity+(Ec-Ef) in the semiconductor?


Measure of Flat-band shift from C-V Characteristics

9

C/Cox

VG

Ideal Vth

Actual Vth

The transition point between accumulation and depletion in a non-ideal MOS structure is shifted to the left when the metal work function is smaller that the electron affinity +(Ec-Ef). At zero applied bias the semiconductor is already depleted so that a very small positive bias inverts the channel. The flatband voltage is the amount of voltage required to shift the

curve such that the transition point is at zero bias.


Outline

10




4) Conclusion


,

( )= + − −− M M F IT st

o

h th ideal M

x

S

ox ox

Q QV

CCV

C

Q φγφ


(2) Idealized MOS Capacitor

11

χsΦm

χi

EC

EV

EF

p semiconductormetal insulator

Vacuum level

,( )= −i ox G th idealQ C V V

Recall that

,

2=

= −s F

Bth ideal s

ox

QV

C ψ φ

ψ

Substrate (p)y

Qox

=0


Distributed Trapped charge in the Oxide

12

EC

EV

EF

Ox

0x

= − −F Mth S

oM

x ox

Q QV

C Cψ γ

0

( )OX

M ox xQ dxρ= ∫

0

0

0

00

0

( )

( )

≡ =∫

∫

ox

ox

x

MM

x

x dxx

xxx dx

xρ

ργ

In the absence of charges in the oxide, the field is constant (dV/dx = constant). The presence of a charge distribution inside the oxide changes the field inside the oxide and effectively traps field lines comping from the gate. As a result, depending on the polarity of charges in the oxie, the threshold voltage is modified.

xm represents the centroid of the charge distribution – one can think of this as replacing the entire distribution with a

delta charge at this point


An Intuitive View

13

Ideal charge-free oxide

-E

0

Bulk charge

-E

0

-E

Interface charge

0

Reduced gate charge


Gate Voltage and Oxide Charge

14

VG

=Vox

+ψs

2

20

( )− = =ox o

o

xx o

x

d V d

dx d

x

x κρ

εE

0 0( )

0( )

( ') 'x x

oxox

oxx x

x dxd

ρκ ε

=∫ ∫E

E

E

−dV

ox

dx=E

ox(x

0) −E

ox(x ) =E

ox(x

0) −

ρox

(x ')dx '

κox

ε00

x

∫

Vox

=κ

S

κox

x0E

S(x

0) − dx

0

x0

∫ρ

ox(x ')dx '

κox

ε00

x0

∫

=κ

S

κox

x0E

S(x

0) −

x ρox

(x )dx

κox

ε00

x0

∫

-E

0

Kirchoff’s Law – balancing voltages

Known from boundary conditions in semiconductor

and continuity of E


Gate Voltage and Oxide Charge

15

0

0 00 0

(

( 2 )

1( 2 ) )) (

= = + ∆

= = + − ∫

th s F ox

x

Sos F xS

ox o

V V

x x x dxC x

x

ψ φ

κψ φκ

ρE

0

0

0

0

0

00

( )( )

x

Sox S

ox

x

o

o xx dxV x

xx

xκ ε

κκ

ρ∆ = −

∫E

0

0 00 0

( () )1= − ∫

oox

x

SS

ox x

x x x dxx

xCκ

ρκE

0

,0 0

,

( )1= −

= −

∫ o

x

th ideal

ox

Mth ideal

ox

x

M

V x dxC x

QV

C

xρ

γ


Interpretation for Bulk Charge

16

0

1,0

1,

0

1

0

( ) ( )

(

1

)

= −

= −

−∫x

th th idealo

th id

o

o

x

Meal

V V x x x dx

Q x

xC x

xV

x C

ρ δ

C/Cox

VG

Ideal VT

New VT


Interpretation for Interface Charge

17

0

*

0 0

*

( ) ( )1

ox o

x

th th

o

Fth

o

V V x dxC x

V

x x

C

x

Q

ρ δ= −

= −

−∫

C/Cox

VG

Ideal VT

New VT


Time-dependent shift of Trapped Charge

18

E

0

, 10 0

1,

0

1( ) ( ( ))

( ) ( )

= − × −

= − ×

∫x

th th ideal oxox

oxth ideal

ox

V V xQ x x x t dxC x

x t Q xV

x C

δ

Sodium related bias temperature instability (BTI) issue

C/Cox

VG

Ideal VT


Bias Temperature Instability (Experiment)

19

----------

+++++

+++++

M O S

(-) biases

0 xo

0.1xo

x

ρio

n

M O S----------

+++

++

+++++

(+) biases

x

0 xo

ρio

n

0.9xo


Outline

20




4) Conclusion


,

( )M M Fth th ideal MS

ox ox

IT s

ox

Q

C

Q QV V

C C

γφ φ−= + − −


SiO and SiH Bonds

21

Local ordering tetrahedra

No long-range order


Interface States

22Unpassivated bonds ~1014 cm-2With annealing technologyUnpassivated bonds ~1010 cm-2


‘Annealing’ of Interface States

23

HH H

Forming gas anneal

111 surface dataBUT: 110 surface has

1/3 less danglingbonds

Good MOSFET requires about 1010/cm2


C-V Stretch Out

24

HH H

Forming gas anneal

Good MOSFET requires about 1010/cm2


Nature of Donor and Acceptor Traps

25

Acceptor levelNeutral when emptyNegative when full

Donor levelPositive when empty Neutral when full

Combination when both are present

Now the surprising part:Hydrogen passivation can act as a donor and as an acceptor leveDepends on details of bond configuration


Donor like Interface States

26

0

*

0 0

( )1

( ) ( )x

th th ox ox

Go

V V x Q x x x dxx

VC

δα× −×= − ∫

C/Cox

VG

* 0( ) ( )oxth

x

G

o

Q

C

V xV

α= −

( ) 0GVα = 0 1( )GVα< < 1( ~)GVα

Assume the charges wouldNOT be voltage dependent=> solid shift BUT: charges change with voltage=> smooth shift


Acceptor like Interface States

27

C/Cox

VG

0

-1

* 0( ( ))( ) ox

th G tho

G

x

V Q xV V V

C

α+=

0

-1

( ) 0GVα = 0 1( )GVα< < 1( ~)GVα


Acceptor and Donor Traps Combined

28

C/Cox

VG

2

Donor-related stretchout

Acceptor-related stretchout


Summary

29

1) Non-ideal threshold characteristics are important

consideration of MOSFET design.

2) The non-idealities arise from differences in gate and

substrate work function, trapped charges, interface

states.

3) Although nonindeal effects often arise from transistor

degradation, there are many cases where these

effects can be used to enhance desirable

characteristics.

ECE606: Solid State Devices Lecture 24 MOSFET non-idealitiesee606/downloads/ECE606_f12_Lecture24.pdfsubstrate work function, trapped charges, interface states. 3) Although nonindeal

Documents