ECE2030 Introduction to Computer Engineering Lecture 12: Building Blocks for Combinational Logic (3) Adders/Subtractors, Parity Checkers Prof. Hsien-Hsin Sean Lee Prof. Hsien-Hsin Sean Lee School of Electrical and Computer School of Electrical and Computer Engineering Engineering Georgia Tech Georgia Tech
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ECE2030 Introduction to Computer Engineering Lecture 12: Building Blocks for Combinational Logic (3) Adders/Subtractors, Parity Checkers Prof. Hsien-Hsin.
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ECE2030 Introduction to Computer Engineering
Lecture 12: Building Blocks for Combinational Logic (3) Adders/Subtractors, Parity Checkers
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean Lee
School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering
For an For an NN-bit ripple adder-bit ripple adderCritical Path Delay Critical Path Delay ~ 2(N-1)+3 = (2N+1) Gate delays~ 2(N-1)+3 = (2N+1) Gate delays
S0
A0 B0
Cin
S1
A1 B1
S2
A2 B2
S3
A3 B3
Carry
Issue of Ripple Adder• Carry propagationCarry propagation is the main issue in
an N-bit ripple adder• A faster adder needs to address the
serial propagation of the carry bit• Let’s re-examine the equation for full
adders
Carry GenerateGenerate & PropagatePropagate
)B(ACBAC iiiii1i
)(propagate BAp
(generate) BAg
iii
iii
iii1i CpgC
0012301231232333334
00120121222223
0010111112
0001
CppppgpppgppgpgCpgC
CpppgppgpgCpgC
CppgpgCpgC
CpgC
Note that all the carry’s are Note that all the carry’s are only dependent on input A and only dependent on input A and
B and CB and C
4-bit Carry-Lookahead Adder (CLA)
Carry Lookahead LogicCarry Lookahead Logic
g1g1 p1p1
A1 B1S1S1
C1C1
g2g2 p2p2
A2 B2S2S2
C2C2
g3g3 p3p3
A3 B3S3S3
C3C3
g0g0 p0p0
A0 B0S0S0
C0C0C4C4
)(propagate BAp
(generate) BAg
iii
iii
iiii BACS
InefficientInefficient Implementation of Carry Lookahead Logic
A0 B0S0S0A1 B1S1S1
C0C0
A2 B2S2S2A3 B3S3S3
C1C1C2C2C3C3
C4C4
g0g0p0p0g1g1p1p1g2g2p2p2g3g3p3p3
0012301231232333334
00120121222223
0010111112
0001
CppppgpppgppgpgCpgC
CpppgppgpgCpgC
CppgpgCpgC
CpgC
Reuse some gate output results Reuse some gate output results Little ImprovementLittle ImprovementCarry Delay is 4*DCarry Delay is 4*DANDAND + 2*D + 2*DOROR for Carry C for Carry C44
Implementation of Carry Lookahead Logic
C4C4
A0 B0S0S0A1 B1S1S1
C0C0
A2 B2S2S2A3 B3S3S3
0012301231232333334
00120121222223
0010111112
0001
CppppgpppgppgpgCpgC
CpppgppgpgCpgC
CppgpgCpgC
CpgC
Carry Lookahead LogicCarry Lookahead Logic
Only 3 Gate Delay for each Carry COnly 3 Gate Delay for each Carry C ii