ic Verilog with VCS- 1 What’s a Hardware Description Language? Two things distinguish an HDL from, say, “C”: • Concurrency – The ability to do several things simultaneously. – i.e. different code-blocks can run concurrently • Timing – Ability to represent the passing of time and sequence events accordingly A powerful feature of the Verilog HDL is that we can use the same language for describing, testing and debugging our system
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Basic Verilog with VCS- 1
What’s a Hardware Description Language?
Two things distinguish an HDL from, say, “C”:
• Concurrency– The ability to do several things simultaneously. – i.e. different code-blocks can run concurrently
• Timing– Ability to represent the passing of time and sequence events
accordingly
A powerful feature of the Verilog HDL is that we can use the same language for describing, testing and debugging our system
Basic Verilog with VCS- 2
Simulation Environment
Simulator
INPUT OUTPUT
models.v
test vectors
libraries
Assembly/Microcode
Textual messages
Tabular output
Graphical waveform
Visual drawings
controlcommands
Feedback
Basic Verilog with VCS- 3
What is Synthesis?
Translation(& syntax-check)
Verilog code:
always @ (A or B or C)begin case (1’b1) A: result = 2’b00; B: result = 2’b01; C: result = 2’b10; default: result = 2’b00; endcaseend
GenericBoolean(GTECH)
netlist
Optimization& Target Library
Mapping
TargetTechnology
NetlistSynopsys
HDL-synthesis Toolset
Constraints
Basic Verilog with VCS- 4
Basic Modeling Structure
always @ (posedge clk)....
assign #3 out=(sel)?in0:in1;
BodyInstancesConcurrent blocks
Ports
Module gate, block, chip,board, system, ...
Pins, Interface
Levels ofabstractions
Multilevel
Basic Verilog with VCS- 5
An Examplemodule test_incrementer;reg clk, inc;wire [11:0] value;
initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end/* This section of code implements a pipeline */always @ (posedge clk) begin a = b; b = c; endendmodule
initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end/* This section of code implements a pipeline */always @ (posedge clk) begin a = b; b = c; endendmodule
"This format is spaced with a tab \t followed with this"
"\n This puts a newline before this string"
"Address = %h at time %d"
Quick Reference pg. 26 - text formatting codes
Basic Verilog with VCS- 10
IdentifiersIdentifiers are names assigned by the user to Verilog objects such as
modules, variables, tasks etc.
• Identifiers must begin with an alphabetical character (a-z A- Z _ )
• Identifiers may contain alphabetical characters, numerics,
underscores and dollar signs (a-z A- Z 0-9 _ $).
module pound_one;reg [7:0] a,a$b,b,c; // register declarationsreg clk;initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end/* This section of code implements a pipeline */always @ (posedge clk) begin a = b; b = c; endendmodule
module pound_one;reg [7:0] a,a$b,b,c; // register declarationsreg clk;initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end/* This section of code implements a pipeline */always @ (posedge clk) begin a = b; b = c; endendmodule
Identifiers in this module:
pound_one, a, a$b, b, c, clk,
Basic Verilog with VCS- 11
Escaped IdentifiersThe use of escaped identifiers allow any character
to be used in an identifier.
• Escaped identifiers start with a backslash (\)
and end with white space.
• Gate level netlists generated by EDA tools
(like DC) often have escaped identifiers
Examples:
\ab#~*this=or=that
\5-6
\bus_a[0] // typical of a Synopsys netlist
\bus_a[1]
Basic Verilog with VCS- 12
Case Sensitivity
Verilog is case sensitive (so are Synopsys synthesis tools)
• Identifiers that do not match in case are considered unique
• All Verilog key words are in lower case
Examples
module // keyword
Module // unique identifier but not keyword
MODULE // unique identifier but not keyword
Quick Reference pg. 1 - reserved keywords
module MoDule (mODULE, modulE); //horrible code, but legalinput …...endmodule
Silly example...
Basic Verilog with VCS- 13
Logic values
Verilog has 4 logic Values:
0 zero, low, false, not asserted
1 one, high, true, asserted
z or Z high impedance
x or X unknown
Basic Verilog with VCS- 14
Integers & Real Numbers• Verilog numbers may be integers or real numbers.
• Integers may be sized or unsized.
Syntax: <size>'<base><value>
where:
<size> is the number of bits<base is b or B (binary), o or O (octal), d or D (decimal), h or H (hex)
<value> is 0-9 a-f A-F x X z Z ? _
Examples: 2'b01, 6'o243, 78, 4'ha,
• Default radix is decimal
1 1'd1
• underscores ( _ ) are ignored (use them as you would commas).
836_234_408_566_343
• a "?" is interpreted as Z (high impedance)
2'b?? 2'bzz
• When <size> is less than <value> - the upper bits are truncated.
2'b101 2'b01, 4'hfcba 4'ha
Basic Verilog with VCS- 15
Integers & Real Numbers -2• When <size> is greater than <value>, and the left-most bit of <value> is 0 or 1,
then zero's are extended to <size> bits.
4'b01 4'b0001, 16'h0 16'h0000
4'b11 4'b0011, 16'h1 16'h0001
• When <size> is greater than <value>, and the left-most bit of <value> is an x
then the x value is extended to <size> bits
4'bx1 4'bxxx1, 16'hx 16'hxxxx
• When <size> is greater than <value>, and the left-most bit of <value> is a z then
the z value is extended to <size> bits
4'bz1 4'bzzz1, 16'hz 16'hzzzz
• Real numbers may be either in decimal or scientific notation.
`define tpd 5#`tpd c = f;designA.v DUT (...);. . .
test_designA.v designA.v
vcs test_designA.v designA.v
order is important because of `define
#`tpd a = 0;. . .
Basic Verilog with VCS- 19
Time scales establish the delay time base and precision in Verilog models.
`timescale time_unit base / time_precision base
time_unit base: sets the time unit for 1 time step ie. What a delay of 1 means
time_precision base: sets the precision ie how to round delays
Example: `timescale 1 ns / 100 ps time unit is 1 ns and round to the nearest .1ns
`timescale Compiler directive
• By default a time step is unit-less.
• Once you set a time scale for any one module you must have a time
scale set for all modules
Specify a `timescale for each module in your design
Basic Verilog with VCS- 20
QuizQ. Which of the following code fragments (if any) will compile. What is wrong in each case (assume any Verilog syntax we have not covered yet is correct)?
A:reg clk,
1a;integer fred;
B:a = 0; /* this is a ratherb = 0; simple comment */
C:include load_file; // reuse last-weeks code
Q. What value is put into register “a” by each of these assignments? Assume “a” is 32 bits wide and has a value of “unknown” before each assignment.
a = 32'b0;a = 64'haabbccddeeff0011; a = 16'h3x0;a = 24'b1;a = 16'bz;
Basic Verilog with VCS- 21
Verilog Modulemodule name (port_names);
module port declarations
data type declarations
procedural blocks
continuous assignments
user defined tasks & functions
primitive instances
module instances
specify blocks
endmodule
module name (port_names);
module port declarations
data type declarations
procedural blocks
continuous assignments
user defined tasks & functions
primitive instances
module instances
specify blocks
endmodule
• Modules contain
• declarations
• functionality
• timing
syntax:module module_name (signal, signal,... signal ) ;
endmodule
syntax:module module_name (signal, signal,... signal ) ;
endmodule
Basic Verilog with VCS- 22
Module Port Declarations
input a, into_here, george; // scalar portsinput [7:0] in_bus, data; //vectored portsoutput [8:31] out_bus; //vectored portinout [maxsize-1:0] a_bus; //parameterized port
input a, into_here, george; // scalar portsinput [7:0] in_bus, data; //vectored portsoutput [8:31] out_bus; //vectored portinout [maxsize-1:0] a_bus; //parameterized port
Scalar (1bit) port declarations:port_direction port_name, port_name ... ;
Vector (Multiple bit) port declarations:port_direction [port_size] port_name, port_name ... ;
port_direction : input, inout (bi-directional) or outputport_name : legal identifierport_size : is a range from [msb:lsb]
big endian or little endian may be usedliteral integers or parameters may be used
module name (port_names);
module port declarations
data type declarations
procedural blocks
continuous assignments
user defined tasks & functions
primitive instances
module instances
specify blocks
endmodule
module name (port_names);
module port declarations
data type declarations
procedural blocks
continuous assignments
user defined tasks & functions
primitive instances
module instances
specify blocks
endmodule
Basic Verilog with VCS- 23
Module Instances
syntax for instantiation with port order:module_name instance_name (signal, signal,...);
syntax for instantiation with port name:module_name instance_name (.port_name(signal), .port_name (signal),... );
syntax for instantiation with port order:module_name instance_name (signal, signal,...);
syntax for instantiation with port name:module_name instance_name (.port_name(signal), .port_name (signal),... );
• A module may be instantiated within another module.• There may be multiple instances of the same module.• Ports are either by order or by name.• Use by order unless there are lots of ports• Use by name for libraries and other peoples code (may change)• Can not mix the two syntax's in one instantiation
module example (a,b,c,d);input a,b;output c,d;. . . .endmodule
example ex_inst_1(in_1, in_2, w, z);example ex_inst_2(in_1, in_2, , z); // skip a portexample ex_inst_3 (.a(w), .d(x), .c(y), .b(z));
module example (a,b,c,d);input a,b;output c,d;. . . .endmodule
example ex_inst_1(in_1, in_2, w, z);example ex_inst_2(in_1, in_2, , z); // skip a portexample ex_inst_3 (.a(w), .d(x), .c(y), .b(z));
Synthesizes Synthesizes module name (port_names);
module port declarations
data type declarations
procedural blocks
continuous assignments
user defined tasks & functions
primitive instances
module instances
specify blocks
endmodule
module name (port_names);
module port declarations
data type declarations
procedural blocks
continuous assignments
user defined tasks & functions
primitive instances
module instances
specify blocks
endmodule
Basic Verilog with VCS- 24
Module HierarchyA hierarchical path in Verilog is in form of: module_name.instance_name.instance_name
top.a.b.c is the path for the hierarchy below.
A hierarchical path in Verilog is in form of: module_name.instance_name.instance_name
top.a.b.c is the path for the hierarchy below.
top
a
cb
Synthesizes Synthesizes
module
instance
Basic Verilog with VCS- 25
Quiz
What (if anything) is wrong with the following lines of code?
examples:wire a,b; // scalar wireswor [7:0] in_bus; // wired-OR buswand [8:31] out_bus; // wired and bus
examples:wire a,b; // scalar wireswor [7:0] in_bus; // wired-OR buswand [8:31] out_bus; // wired and bus
• Connect devices.• Are continuously driven by the device that drives them.• New values are propagated automatically when the
driver changes.
wire, tri standard basic interconnectwor, trior wired-OR outputswand, triand wired-AND outputstri0 pulls down when tri-statedtri1 pulls up when tri-statedtrireg stores last value when tri-statedsupply0, supply1 constant 0 or 1
wire, tri standard basic interconnectwor, trior wired-OR outputswand, triand wired-AND outputstri0 pulls down when tri-statedtri1 pulls up when tri-statedtrireg stores last value when tri-statedsupply0, supply1 constant 0 or 1
Synthesizes Synthesizes
Synthesizes Synthesizes
Synthesizes Synthesizes
Synthesizes Synthesizes
Synthesizes Synthesizes
Coding style tip - Use "tri" instead of "wire" as a visual indicator for more than
one driver on a net.
Basic Verilog with VCS- 28
Registers
reg unsigned variable of any sizeinteger signed 32-bit variabletime unsigned 64 bit variablereal signed floating point variable of double precision
reg unsigned variable of any sizeinteger signed 32-bit variabletime unsigned 64 bit variablereal signed floating point variable of double precision
reg a; // scalar reg variablereg [7:0] in_bus; // vectored reg variableinteger i, j; //32 bit signed variablestime t; // unsigned 64 bit variablereal b,c; // signed floating point variables
reg a; // scalar reg variablereg [7:0] in_bus; // vectored reg variableinteger i, j; //32 bit signed variablestime t; // unsigned 64 bit variablereal b,c; // signed floating point variables
• Storage device (may represent abstract or real).