ECE 598 JS Introductionjsa.ece.illinois.edu/ece598js/Lect_01.pdf · Title: Microsoft PowerPoint - Lect_01 [Compatibility Mode] Author: jose Created Date: 1/17/2012 1:29:15 PM

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 598‐JS, Spring 2012 1

ECE 598 JSIntroduction

Spring 2012

Jose E. Schutt-AineElectrical & Computer Engineering

University of [email protected]


0

0.5

1

1.5

2

2.5

Log

(Cap

acity

Gb/

s)

1980 1985 1990 1995 2000 2005 2010A

Limits of Optical

Future System Needs and FunctionsAuto Digital Wireless

Consumer Computer

MEMS

High bandwidth High-speed Digital

Analog, RF


Activities at home* Telecommuting / home* Teleshopping / home banking* Home medical and health care

Information-oriented living* Shopping / events / traffics* Pastime / learning / sightseeing* Administrative services for residents

Pursuing comfortable labor* Remote and mobile offices* Remote control, unattended factory* Collaboration environment

Voice64 kbps

Documentsand drawings

128 kbps

3D-CG1 Mbps

HD stillimages1 Mbps

Video images1 Mbps

NTSC images6 Mbps

HDTV images26 Mbps

Required media andthe amount of information

100 Mbps per home

Demand in the Information Age

Source: ITRCS


PCI

• PC InterfaceFor external cardsGraphics, Network, Sound, etc…Parallel


• Computer Expansion Card StandardReplaced older PCIBased on serial linksCapacity up to 1 Gb/sV3.0 scheduled for 2010

PCI‐Express


Universal Serial Bus (USB)

• Interfaces devices to computersNo rebootingLow powerNo need for external power supply480 Mb/s


• Expansion Card StandardReplaced older PCIBased on serial linksCapacity up to 1 Gb/sV3.0 scheduled for 2010

IDE


Serial ‐ ATA

• Storage interfaceReplaces older parallel ATA or IDEBased on serial linksCapacity up to 3 Gb/sHot swapping capability


Computer Interconnections


Motherboards and Backplanes


Cables and Transmission Lines

coaxial

twisted pairs


Cable Specifications


Measurements

VNA: S-parameter Spectrum Analyzer

Time-domain simulation Eye diagram


Chip size(mm2)

Number of transistors(million)

Interconnect width(nm)

Total interconnect length(km)

1997 2003 20122006

300 430 750520

11 76 200 1400

200 100 70 35

2.16 2.84 5.14 24

Semiconductor Technology Trends


Source: ITRS roadmap 2004

Signal Delay Trend

Signal Delay

Delay for Metal 1 and Global Wiring versus Feature Size

gates delay

interconnect delayGlobal

Wiring w/o Repeaters

GlobalWiring w

Repeaters

LocalWiring

Gate Delay


0

5

10

15

20

25

Del

ay (p

s)

30

35

40

45

650 595 540 485Generation (nm)

SPEED/PERFORMANCE ISSUE

Gate Delay

Sum of Delays, Al & SiO2

Sum of Delays, Cu & Low K

Interconnect Delay, Al & SiO2

Interconnect Delay, Cu & Low K

430 375 320 265 210 155 100

Gate wi Al & SiO2

Gate

Al 3.0 μΩ -cmCu 1.7 μΩ -cmSiO2 κ = 4.0Low κ κ = 2.0Al & Cu .8μ ThickAl & Cu Line 43μ Long

The Interconnect Bottleneck


MOS Technology Trends


• Total interconnect length (m/cm2) – active wiring only, excluding global levels will increases:

• Interconnect power dissipation is more than 50% of the total dynamic power consumption in 130nm and will become dominant in future technology nodes

• Interconnect centric design flows have been adopted to reduce the length of the critical signal path

Interconnect

Year 2003 2004 2005 2006 2007 2008 2009Total

Length 579 688 907 1002 1117 1401 1559


Source: M. Bohr and Y. El-Mansy - IEEE TED Vol. 4, March 1998

5‐Layer Interconnect Technology 0.25 μm

Vertical parallel-plate capacitance 0.05 fF/μm2

Vertical parallel-plate capacitance (min width) 0.03 fF/μmVertical fringing capacitance (each side) 0.01 fF/μmHorizontal coupling capacitance (each side) 0.03


Metal 5

Metal 4

Metal 3Metal 2

Metal 1

Substrate

Vertical parallel-plate capacitance 0.05 fF/μm2

Vertical parallel-plate capacitance (min width) 0.03 fF/μmVertical fringing capacitance (each side) 0.01 fF/μmHorizontal coupling capacitance (each side) 0.03

Integrated Circuit Wiring


Chip‐Level Interconnect Delay

Line

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Vol

ts

0 0.4 0.8 1.2 1.6 2Time (ns)

Far End Response

BoardVLSISubmicronDeep Submicron

-0.1

0.175

0.45

0.725

1

0 0.4

Vol

ts

0.8 1.2 1.6 2Time (ns)

Near End Response

BoardVLSISubmicronDeep Submicron

Pulse Characteristics: rise time: 100 ps fall time: 100 ps pulse width: 4ns

Line Characteristics length : 3 mm near end termination: 50 Ω far end termination 65 Ω

LogicthresholdLogic

threshold


Package‐Level Complexity

- Up to 16 layers- Hundreds of vias- Thousands of TLs- High density- Nonuniformity


TransmissionChannel

TransmissionChannel

TransmissionChannel

Ideal

Common

Noisy

Signal Integrity


Crosstalk Dispersion Attenuation

Reflection Distortion Loss

Delta I Noise Ground Bounce Radiation

Sense Line

Drive Line

Drive Line

Signal Integrity


IC on Package


• Simultaneous switching and inductance (Leff)

• Leff is f( current magnitude and direction)

• Interactions between noise generated by power/ground and signal paths

Mixed Signal Noise

Power bus

Interconnect

Analog Digital

coupled noise

Substrate

Power bus

Interconnect

GND

bond InductanceChip-packageinterconnect


- Power-supply-level fluctuations- Delta-I noise- Simultaneous switching noise (SSN)- Ground bounce

IdealVout

ActualVout

VOH

VOL

Time

Power‐Supply Noise


+

-

Gate A Gate C

RWire B

N

Output voltage fromGate A

+

-

V1

Differential voltageat receiverV1 - R

GROUND CONNECTIONInternalreferencegenerator

+

-

V1

+-

+

-

Gate A Gate C

RWire B

N

Equivalent noisesource in serieswith ground connection

Output voltage fromGate A

+

-

V1

Differential voltageat receiverV2 - N - R

GROUND CONNECTIONInternalreferencegenerator

+

-

V2

Power Distribution Problem

At high frequencies, Wire B is a transmission line and ground connection is no longer the reference voltage

Low Frequency

High Frequency


VP Bus

VP Bus

VP Bus

VP Bus

VP Bus

GND Bus

GND Bus

GND Bus

GND Bus

VP

GND

Local Buses

Wiring Tracks

• Distribution Network for Peripheral Bonding– Power and ground are brought onto the chip via bond pads located

along the four edges– Metal buses provide routing from the edges to the remainder of the chip

On‐Chip Power and Ground Distribution


-Mounted on PWB in pin-through-hole (PTH) configuration- Chip occupies less than 20% of total space- Lead frame with large inductance

Dual‐in‐Line (DIP) Package


Packages & Packaging Trends

Quad Flat Pack Thermal Package

MCM


Stacked Wire Bonds


Ceramic Substrate


Area Bonding with Flip Chip

Pins

PackageBody

Bumped Die

– Minimizes IR drops between gates– Minimizes interconnection inductance


* Schematic editor

* Circuit level simulator

* Layout editor

* Placement & routing

* Design rule checker

* Netlist extractor

* Layout vs Schematic

* Libraries

* Design verification

* Electromagnetic analysis

Tools for Physical Design


State‐of‐the‐Art in Extraction

CAPACITANCE

* MoM- BEM

* FEM

* Fast Multipole

INDUCTANCE

* MoM- BEM (2D)

* FEM (2D)

* PEEC (3D)

* Fast Multipole

Main Challenge: 3D inductance extraction is computationally expensive.


Circuit Simulation

* SPICE

* Asymptotic Waveform Evaluation

* Complex Frequency Hopping

* Passive Multipoint Matching Method

* Latency Insertion Method

Y(t) v(t) = I(t)Given, Y and I, find v

Board/Module Chip


Established platform

Powerful engine

Source code available for free

Extensive libraries of devices

New device installation procedure straightforward

Why SPICE ?


spice3f4

conf examples lib doc

helpdir scripts

bjt

utiltmppatches srcnotesman

man1 man3 man5 unsuppobin include lib skeleton

ckt cp dev fte hlp inp mfb mfbpc misc ni sparse mac

asrc bsim1 bsim2 cap cccs ccvs csw dio disto ind isrc mes

mos1

ltrajfet

mos2 mos3 mos6 res sw tra urc vccs vcvs vsrc

lib

Parser StampFromNetlist I=YVDevice To

Solver

Directory Structure

SPICE


Interconnect Simulation Application

• New Interconnects:– 3D Interconnect (System In Package)– package-intermediated interconnects

• Power Ground Network:It will greatly affect the performance of the chip design:– Voltage (IR) drops on VDD nets– ground bounce on VSS nets – High currents in the power grids Electromigration effect

Chip-Package-Board Co-Design

Power Ground Network Design


Chip‐Package Co‐Design

Source: Joel Mcgrath, “Chip/package co-design: The bridge between chips and systems “, Advanced Packaging Magazine June, 2001

Repeated Simulation of the Package/BoardSuper FastSimulation

Repeated Simulation of the Package/BoardSuper FastSimulation


Power Ground Network Design Flow

Repeated Simulation of the P/G networkSuper

FastSimulation


DesignSpecification

FunctionalDesign

LogicDesign

CircuitDesign

PhysicalDesign

fabrication

extraction andverification

circuitanalysis

logicsimulation

functionalsimulation

specification

behavioralrepresentation

structuralrepresentation

structuralrepresentation

physicalrepresentation

requirements

Deep Submicron Timing Closure

Unbounded design iterations resulting from unpredicted timing violations

- 0.25 microns and lower- 2 to 20 iterations- mismatch between logic and physical designs - greater timing variations- dominated by interconnects- inductive and capacitive coupling- slows time-to-market


X cells

Y cells

+- +-

+

-

+- +-

+

-

+

-=Unit cell

Example: Power Bus/Ground Plane Model

Typical workstation simulation time for a 1200-cell network is 2 h 40 min.

Too time consuming!

- Determine R,L,G,C parameters and define cell- Synthesize 2-D circuit model for ground plane- Use SPICE to simulate transient

Modeling


Large Network (>1,000 nodes)

Reduced Order Model

(< 30 poles)

SPICE Y(t) v(t) = i(t) Y(ω) V(ω) = I(ω)

Order Reduction

Y(ω) = Y(ω)~ ~

Recursive Convolution

Y(t) v(t) = i(t) ~

MOR Schemes* AWE

* Padé via Lanczos

* Complex frequency hopping

* Direct rational approximation

Model Order Reduction