CE 545 - Lecture 13 Motorola 68HC11
Jan 16, 2016
ECE 545 - Lecture 13
Motorola 68HC11
Resources
68HC11 E-series Reference Guide and if necessary
68HC11 E-series Technical Data 68HC11 Reference Manual
all available at http://www.technologicalarts.com/myfiles/links.html
Optionally:Peter Spasov, Microcontroller Technology, any edition, Prentice-Hall, Chapter 2, Software,and Chapter 7 Clocked Operation(you can borrow this book from the ECE 447 students).
Basic Computer System
CPUMemoryProgram + Data
I/O Interface
ParallelI/O Device
SerialI/O Device
Data Bus
Address Bus
Control Bus
Parallel Data
Serial Data
Microprocessor - usually memory off-chip and only basic I/O interface on chip
e.g., Intel 8008, 8080, 8086, 80286, Pentium
Single-chip microcomputer - CPU, memory, I/O interface, and simple I/O devices on one LSI chip
e.g., Intel 8048, 8051, Motorola 68HC11, 68HC16
Microcontroller: I/O oriented single-chip microcomputer
Microcontroler vs. other single-chip microcomputers:
• Extended I/O capabilities
synchronous and asynchronous communication devices,A/D and D/A converters, timers, counters, watchdogs
• Interrupt handling
increased ability to prioritize levels of interrupts and maskindividual interrupts
• Instruction setinstructions oriented toward bit manipulation, operations on single bits of memory words or I/O ports
Early microcroprocessors
performance integration
General-purposemicroprocessors
Single-chip microcomputers
- small price- low power consumption- built-in memory- built-in I/O devices
- high speed- long word size
volumesold x 1 x 10
(e.g., Pentium, Alpha, Power PC) (e.g., MC68HC11, 8051)
(8080, 6800, Z80)
68HC11 Organization
CPU RAM
ROM
EEPROM
TIMER
A/DSPI
SCI
PORT A PORT B PORT C PORT D PORT E
Organization of MC68HC11 in the Single-Chip Mode
8 8 (4)8
24
6
8 (4)8
3 3 2
CPU RAM
ROM
EEPROM
TIMERA/D
SPI
SCI
PORT A PORT D PORT E
Organization of MC68HC11 in the Expanded Bus Mode
8 (4)
24
6
8 (4)8
3 3 2
EXTERNAL RAM
EXTERNAL ROM
EXTERNAL EPROM
EXTERNAL I/O
Abbreviations
CPU - Central Processing Unit := ALU (Arithmetic Logic Unit) + Control
RAM - Random Access Memory := Read/Write Memory
ROM - Read Only Memory (non-volatile)
EPROM - Erasable Programmable ROM
EEPROM - Electrically Erasable ROM
SCI - Serial Communication Interface (asynchronous serial communication interface)
SPI - Serial Peripheral Interface (synchronous serial communication interface)
A/D - analog-to-digital converter
Internal Registers
X-index register
Y-index register
Stack Pointer
Program Counter
Condition Code Register
Register structure of MC6811
Double Accumulator DAccumulators A and B or
IX 015
IY 015
SP 015
PC 015
CCR 07
D 015
7 70 0A B
S X H I N Z V C
Condition Code Register
CCR 07
S X H I N Z V C
carry / borrowoverflowzeronegativeI-interrupt maskhalf-carry (from bit 3)X-interrupt maskstop disable
I/O Ports and other I/O Devices
Input/Output Ports
PortInput Pins
Output Pins
Bidirectional Pins
SharedFunctions
Port A
Port B
Port C
Port D
Port E
3
–
–
–
8
3
8
–
–
–
2
–
8
6
–
Timer
High Order Address
Low Order Address and Data Bus
SCI and SPI
A/D Converter
Memory mapped I/O
(e.g., Motorola)
0
MAX
I/O
Control lines: read/write
Separate I/O
(e.g., Intel)
0
MAX
I/O0
max
Control lines: read/write memory/io
Memory map of MC68HC11E1
$0000
$1000
$B600
$FFFF
$0000
$1000
$B600
$FFFF
EXT
EXT
EXT
$0000-$01FF 512 bytes RAM
$1000-$103F 64 bytes I/O registers
$B600-$B7FF 512 bytes EEPROM
Single-chip mode Expanded bus mode
I/O Device Architecture
…..
Control registersinstructions
…..
Status registersstatus of the device
Data registers
…..
I/O device
address1/name1
addressN/nameN
. . . . .
inputs (operands)
outputs (results)
Input/Output Register Types
1. Control registers - hold instructions that regulate the operation of internal I/O devices
2. Status registers - indicate the current status of internal I/O devices
3. Data registers - hold the input data sent to the I/O device and output data generated by this device
4. Data direction registers - control the direction (in or out) of the data flow to/from bidirectional data registers
Assembly Language vs.
Machine Code
Assembly language vs. machine code
Assembly language
[label] mnemonic [operands]
LDAA #$4ALDAA $5B, Y
Machine code
$86 $4A
[prebyte] opcode [operands]
$18 $A6 $5B
START CLRA
$4F
Number of instructions represented using a single-byte opcode
Number of instructions represented using a combination prebyte+opcode
76
236
Values of prebytes
18, 1A, CD
Machine code
; move.s11; function that transfer an array of 128 bytes; starting at location $C800 to the memory area; starting at location $D800
SECTION .text
transfer:LDX #$C800LDY #$D800
loop_beginLDD 0,XSTD 0,YINXINXINYINYCPX #$C880BNE loop_beginRTS
END
move.s11
move.lst
C:/introl/Examples/E Sep 24 00:41 19102 Page 1 1 ; move.s11 2 ; function that transfer an array of 128 bytes 3 ; starting at location $C800 to the memory area 4 ; starting at location $D800 5 6 SECTION .text 7 8 00000000 transfer: 9 00000000 cec800 LDX #$C800 10 00000003 18ced800 LDY #$D800 11 00000007 loop_begin 12 00000007 ec00 LDD 0,X 13 00000009 18ed00 STD 0,Y 14 0000000c 08 INX 15 0000000d 08 INX 16 0000000e 1808 INY 17 00000010 1808 INY 18 00000012 8cc880 CPX #$C880 19 00000015 26f0 BNE loop_begin 20 00000017 39 RTS 21 22 END
C:/introl/Examples/E Sep 24 00:41 19102 Page 2 Section synopsis
1 00000018 ( 24) .text C:/introl/Examples/E Sep 24 00:41 19102 Page 3 Symbol table
.text 1 00000000 | loop_begin 1 00000007 | transfer E 1 00000000C:/introl/Examples/E Sep 24 00:41 19102 Page 4 Symbol cross-reference
.text *6 loop_begin *11 19 transfer *8
Groups of Instructions
Groups of instructions (1)1. Data handling instructions a. Move instructions (e.g., load, store, exchange) b. Alter data instructions (e.g., clear, increment, decrement) c. Edit instructions (e.g., shift, rotate)
2. Arithmetic instructions (e.g., add, subtract, multiply, divide, negate)
3. Logic instructions (e.g., and, or, xor)
4. Data test instructions (e.g. compare, test, bit test)
5. Control instructions (e.g., jump, branch)
Groups of instructions (2)
6. Condition code instructions (e.g., set carry, clear overflow flag)
7. Stack operations (e.g. push, pull)
8. Subroutine-related instructions (e.g. jump to subroutine, return from subroutine)
9. Interrupt-related instructions (e.g. software interrupt, return from interrupt)
Addressing Modes
Move instructions (1)
1. memory register
LDA [A, B]LD [D, X, Y, S]
2. register memory
STA [A, B]ST [D, X, Y, S]
3. register register
TAB, TBA
4. memory memory
IMM, DIR, EXT, IND
DIR, EXT, IND
INH
N Z V C
0 –
0 –
0 –
Move instructions (2)
1. register register
XGD [X, Y]
N Z V C
– – – –INH
Addressing modes of the LDAA instruction
Immediate mode
LDAA #$5C
Direct mode
LDAA $1B
Extended mode
LDAA $6D00
Indexed mode
LDAA $56, XLDAA $56, Y
$5C A
($001B) A
($6D00) A
(IX+$56) A (IY+$56) A
Instruction Table
Addressing modes of MC68HC11 (1)
1. Inherent: Opcode contains reference.
2. Immediate: Data follows opcode.
3. “Direct”: Base page, Page 0;Low byte of address follows opcode.High byte of address set to zero.
4. Extended: Direct;Complete address of the operand follows the opcode.
5. Indexed Contents of X or Y index registeradded to the unsigned offset in thebyte following the opcode to formeffective address
6. Relative signed byte following the opcodeadded to the pre-incrementedprogram counter PC to form effective address
Addressing modes of MC68HC11 (2)
Arithmetic Instructions
Arithmetic instructions (1)
1. addition Acc + M Acc
ADD [A, B, D]ADC [A, B]
2. subtraction Acc – M Acc
SUB [A, B, D]SBC [A, B]
IMM, DIR, EXT, IND
N Z V C
IMM, DIR, EXT, IND
EXT, IND
INH
3. negation -X
NEG [A, B]NEG
B = b7 b6 b5 b4 b3 b2 b1 b0
Unsigned vs. signed numbers
Unsigned number
Signed number
B = b7 b6 b5 b4 b3 b2 b1 b0
B = b7 b6 b5 b4 b3 b2 b1 b0
128 64 32 16 8 4 2 1weights
weights -128 64 32 16 8 4 2 1
B = b020 + b121 + b222 + b323 + b424 + b525 + b626 + b727 = bi2ii=0
7
B = b020 + b121 + b222 + b323 + b424 + b525 + b626 - b727 = - b727 + bi2ii=0
6
Definition of the Condition Code Register flags (1)
Z = 1 if result = 0 0 otherwise
Zero flag - Z
N = sign bit of the result r7 - for 8-bit operands r15 - for 16-bit operands
Negative flag- N
zero result
negative result
Definition of the Condition Code Register flags (2)
C = 1 if result > MAX_UNSIGNED or result < 0 0 otherwise
where MAX_UNSIGNED = 28-1 for 8-bit operands (registers A, B) 216-1 for 16-bit operands (register D)
V = 1 if result > MAX_SIGNED or result < MIN_SIGNED 0 otherwise
where MAX_SIGNED = 27-1 for 8-bit operands (registers A, B) 215-1 for 16-bit operands (register D)
MIN_SIGNED = -27 for 8-bit operands (registers A, B) -215 for 16-bit operands (register D)
Carry flag - C
Overflow flag - V
out-of-range for unsigned numbers
out-of-range for signed numbers
Overflow for signed numbers (1)
Indication of overflow
Positive+ Positive= Negative
Negative+ Negative= Positive
Formulas
Overflow2’s complement = xk-1 yk-1 sk-1 + xk-1 yk-1 sk-1 =
= ck ck-1
Overflow for signed numbers (2)
xk-1 yk-1 ck-1 ck sk-1 overflow ckck-1
00001111
00110011
01010101
00010111
01101001
01000010
01000010
Condition code instructions
1. set a flag 1 flag
SE [C, V, I]
2. clear a flag 0 flag
CL [C, V, I]
3. change all flags A CC
TAP
4. read all flags CC A
TPA
Arithmetic instructions (2)
1. addition Reg + B Reg
ABAAB [X, Y]
2. subtraction A – B A
SBA
INH
N Z V C
INH
– – – –
Arithmetic instructions (3)
1. unsigned multiplication A x B D
MUL
2. unsigned division D/IX IX D mod IX D
IDIV
3. unsigned fractional division D < IX 216 D/ IX IX 216 D mod IX D
4. decimal adjustment
DAA
INH
N Z V C
INH
INH
– – –
– 0
– FDIV
INH ?
Extending the number of bits of a signed number
xk-1 xk-2 … x1 x0
yk’-1 yk’-2 … yk yk-1 yk-2 … y1 y0
X
Y
two’s complement
xk-1 xk-1 xk-1 . . .xk-1 xk-2 … x1 x0
Other Instructions
Alter data instructions1. 0 register
CLR [A, B]
2. 0 memory
CLR EXT, IND
INH
N Z V C
0 1 0 0
0 1 0 0
3. increment X++INC [A, B]INCIN [X, Y]
4. decrement X--DEC [A, B]DECDE [X, Y]
– INHEXT, IND INH – – –
INHEXT, IND INH
–
– – –
Edit instructions - Shifts
1. logical shift right
LSR [A, B, D]LSR
2. arithmetic shift right
ASR [A, B, D]ASR
3. arithmetic/logical shift left
ASL [A, B, D], LSL [A, B, D]ASL, LSL
INHEXT, IND
INHEXT, IND
INHEXT, IND
00n-1
C. . .
0n-1C. . .
00n-1
C . . .
N Z V C
0
Edit instructions - Rotations
1. rotation right
ROL [A, B]ROL
2. rotation left
ROR [A, B]ROR
INHEXT, IND
INHEXT, IND
07 C. . .
007C
. . .
N Z V C
Logic instructions (1)
1. AND Acc & M Acc
AND [A, B]
2. OR Acc | M Acc
ORA [A, B]
3. XOR Acc M Acc
EOR [A, B]
IMM, DIR, EXT, IND
N Z V C
IMM, DIR, EXT, IND
IMM, DIR, EXT, IND
0 –
0 –
0 –
Logic instructions (2)
1. complement X X
COM [A, B]COM
2. bit set M | mask M
BSET
3. bit clear M & mask M
BCLR
INHEXT, IND
N Z V C
DIR, IND
0 1
0 –
0 –DIR, IND
3. test register
TST [A, B]
4. test memory
TST
0 0
0 0
INH
EXT, IND
IMM, DIR, EXT, IND
1. comparison R - M
CMP [A, B]CP [D, X, Y]
Data test instructions (1)N Z V C
INH
2. comparison A – B
CBA
0 –IMM, DIR, EXT, IND
1. Bit test Acc & memory
BIT [A, B]
Data test instructions (2)N Z V C
Control instructions (1) - BranchesREL N Z V C
– – – –after comparison register vs. memory
unsigned numbers signed numbers
BHI higher >BLO lower <
BHS higher or same BLS lower or same
BGT greater than >BLT less than <
BGE greater than or equal BLE less than or equal
BEQ equal =BNE not equal
Control instructions (2) - Branches
after arithmetic operations (testing for overflow)
unsigned numbers signed numbers
BCS carry setBCC carry clear
BVS overflow setBVC overflow clear
BPL plus 0BMI minus < 0
after testing register or memory
unconditional
BRA alwaysBRN never
Condition code instructions
1. set a flag 1 flag
SE [C, V, I]
2. clear a flag 0 flag
CL [C, V, I]
3. change all flags A CC
TAP
4. read all flags CC A
TPA
3. test register
TST [A, B]
4. test memory
TST
0 0
0 0
INH
EXT, IND
IMM, DIR, EXT, IND
1. comparison R - M
CMP [A, B]CP [D, X, Y]
Data test instructions (1)N Z V C
INH
2. comparison A – B
CBA
0 –IMM, DIR, EXT, IND
1. Bit test Acc & memory
BIT [A, B]
Data test instructions (2)N Z V C
Opcode Map
Interface to External Memory
Write Cycle