1 ECE 465 Introduction to CPLDs and FPGAs Shantanu Dutt ECE Dept. University of Illinois at Chicago Acknowledgement: Extracted from lecture notes of Dr. Mohamed M. Elkhatib, German University of Cairo and Prof. Russell Tessier, Univ. of Massachusetts. Some modfications and additions done by Prof. Dutt. CPLD Families
11
Embed
ECE 465 Introduction to CPLDs and FPGAs - Electrical and
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
1
ECE 465Introduction to CPLDs and FPGAs
Shantanu DuttECE Dept.
University of Illinois at Chicago
Acknowledgement: Extracted from lecture notes of Dr. Mohamed M.Elkhatib, German University of Cairo and Prof. Russell Tessier, Univ. of
Massachusetts. Some modfications and additions done by Prof. Dutt.
CPLD Families
2
CPLD Block Diagram
Function block (~ PLA w/ 1 o/pthat can be FF’ed)
Programmable switch for interconnecting various FBs
FF
FF
FF FF
FF
1
10
0
0
I/Ps
O/Ps
Crossbar Switch
An individual switchIn a crossbar is adiamond switch
CPLD Function Block
PLA-like AND arrayLiteral inputs (e.g., a, b, c)
Extra function (e.g., g,h) i/ps for OR term
Example functionf= ab+bc’+g+h
D-FF
2:1 Mux
3
Field Programmable Gate Arrays (FPGAs)
FPGA Types
(Anti-fuse technology)
4
FPGA Families
PSM: Programmable Switch Matrix (for making connections between interconnects of different channels). The structure shown only allows i-to-i connections
• 5-i/p function implemented using G, F and H LUTs (Look Up Tables) using Shannon’sExpansion: p(a,b,c,d,e) = a p(1, b, c, d, e) + a’ p(0, b, c, d, e) = a q(b,c,d,e) + a’r(b,c,d,e).q( ) impl. using LUT G, r impl. using LUT F and p=ag + a’h impl. using LUT H• The LUT o/ps can go through a FF (for seq. ckt design) or bypass it for a combinational o/p• This is called technology mapping: mapping the logic to CLB logic components
6
Technology Mapping
Programming a CLB (contd)
7
Components of Modern FPGAs
8
Digital System: Implementation Spectrum
–ASIC gives high performance at cost of inflexibility.
–Processor is very flexible but not tuned to the application.
–Reconfigurable hardware is a nice compromise.
Microprocessor ReconfigurableHardware
ASIC
Software Firmware Hardware
Simplified FPGA Logic Element
Look-Up Table (LUT)
State
OutInputs
Clock
Enable
9
High-level Compilers & FPGAs
–Difficult to estimate hardware resources.–Some parts of program more appropriate for
processor (hardware/software codesign).–Compiler must parallelize computation
across many resources. –Engineers like to write in C/VHDL/Verilog
rather than pushing little blocks around.
for (i = 0; i<n, i++){
c[i] = a[i] + b[i]}
Some success stories
Translating a Design to an FPGA
–CAD to translate circuit from text description to physical implementation well understood.
–Most current FPGA designers use register-transfer level specification (allocation and scheduling)
4. Convert all implementation “details” to FPGA programming info (configuration bits): LUT RAM bits, CCM & PSM FF/SRAM bits, etc.
• Can store config bits on disk or ROM and load into FPGA as needed• Can thus use the FPGA to implement multiple digital systems (at different times or sometimes simultaneously in different FPGA partitions)
Technology Mapping: A Simple Example
FA
A B
Co Ci
S
Made of Full AddersA+B = D
Logic synthesis tool reduces circuit toSOP form
Co = ABCi + ABCi + ABCi + ABCi
S = ABCi + ABCi + ABCi + ABCi
LUT CoCiBA
LUT SCiBA
11
Processor + FPGA
1. FPGA serves as coprocessor for data intensive applications – possible project.
Three possibilities
Backplane bus(e.g. PCI)
Proc
chip
daughtercard
FPGA
chipFPGAProc
2. FPGA serves as embedded digital systemfor lower latency processing.“Reconfigurable Functional Unit”