ECE 456 Computer Architecture Lecture #5 – Semiconductor (Internal) Memory Instructor: Honggang Wang Fall 2013.

ECE 456 Computer Architecture

Lecture #5 –

Semiconductor (Internal) Memory

Instructor: Honggang Wang

Fall 2013

Dr. Wang

Administrative Issues (10/23/13, Wednesday)

•Project proposal (File name: Group#_proposal.doc/docx)– due Wednesday, Oct. 28– Proposal guidelines are available from the class website

•This class – L#5 (Semiconductor Memory)

Dr. Wang

Review of Lecture #4

In the last lecture, we covered the …...

• Characteristics of memory systems

– location, capacity, transfer unit, access methods, performance,

physical types, physical characteristics, and organization

• Memory hierarchy

– dilemma, goal: why ? (locality), how?

• Error correction in memory

– error types, definitions & concepts, single-bit & multiple-bit

parity codes, Hamming SEC

Dr. Wang

Schedule for Memory Lectures

CPUCACHE

MAINMEMORY

I/O STORAGE DEVICES

Registers

Internal Memory

ExternalMemory

Next

plus Virtual Memory

Defer to CPU discussion

Dr. Wang

Memory of Interest

• Location– internal memory

• Physical types– semiconductor memory

• Access methods – random access memory

Dr. Wang

Topics

• The basic elements

• Semiconductor memory types

• Memory organizations

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The Basic Elements: Memory Cells

• Memory cell properties

– two stable states for representing binary 1 and 0

– can be written into at least once to set the state

– can be read to sense the state

Dr. Wang

Memory Cell Operations

Dr. Wang

Agenda

The basic element

– The memory cell

• Semiconductor memory types

• Memory organizations

Dr. Wang

Semiconductor Memory Types(Internal and Random Access)

Read-write memory

Read-mostlymemory

Read-only memory

Erasable PROM(EPROM)

Electrically Erasable PROM (EEPROM)

Flash memory

Random-access memory (RAM) Read-only

Memory (ROM)

ProgrammableROM (PROM)

Static RAM(SRAM)

Dynamic RAM(DRAM)

Synchronous DRAM (SDRAM)

Rambus DRAM (RDRAM)

Cache DRAM (CDRAM)

Dr. Wang

Random Access Memory (RAM)

• Can be both read and written• Is volatile• Can be used only as temporary storage• Two forms:

– dynamic• data tend to decay even with power continuously applied

– static • data are held as long as power is supplied

Semiconductor Internal Random Access Memory Types – RAM (1)

Dr. Wang

Agenda (RAM)

• Dynamic RAM (DRAM)• Static RAM (SRAM)• DRAM vs. SRAM• Enhancements to the DRAM

– SDRAM

– CDRAM

Semiconductor Internal Random Access Memory Types – RAM (2)

Dr. Wang

Dynamic RAM (DRAM)

• Data stored as charge on capacitors– presence: 1

– absence: 0

– threshold

• Need charge refreshing to maintain data storage

• A DRAM cell:

Semiconductor Internal Random Access Memory Types – RAM (3)

write

read

Dr. Wang

Static RAM (SRAM)

• Data stored as a combination of transistors’ on-off– T1, T4 off, T2, T3 on: 1

– T1, T4 on, T2, T3 off: 0

• Data are held as long as power is supplied, no refresh is needed

• A SRAM cell:

Semiconductor Internal Random Access Memory Types – RAM (4)

Dr. Wang

DRAM vs. SRAM Volatile, Read-Write

• DRAM cell– Refresh needed

– Smaller and simpler

– More dense

– Less expensive

– For main memory

• SRAM cell– No refresh

– Faster

– For cache memory

Semiconductor Internal Random Access Memory Types – RAM (5)

Dr. Wang

Agenda of RAM

• Dynamic RAM (DRAM)• Static RAM (SRAM)• DRAM vs. SRAM• Example enhancements to the DRAM

– SDRAM

– CDRAM

Semiconductor Internal Random Access Memory Types – RAM (6)

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Why Enhancements to DRAM?

• Critical bottleneck: interface between the DRAM main memory and processor

• Cache solution is expensive and not enough

Semiconductor Internal Random Access Memory Types – RAM (7)

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Synchronous DRAM (SDRAM)

• Traditional DRAM– Asynchronous

– CPU may wait for data/instructions from memory

• SDRAM– access is synchronized to an external clock

– CPU knows when data can be ready (once-per-cycle)

– CPU can do something else while memory is processing request

• DDR-SDRAM: twice-per-cycle

Semiconductor Internal Random Access Memory Types – RAM (8)

Dr. Wang

Cache DRAM (CDRAM)

• Developed by Mitsubishi• Integrates a SRAM cache onto a DRAM chip

– A true cache

– A buffer to support serial access

Semiconductor Internal Random Access Memory Types – RAM (10)

Dr. Wang

CDRAM

• Tokyo, January 15, 2004 - Hitachi Ltd., today announced the high-performance 144-Mbit cache DRAM "HDL5KM series" with world-leading 8ns random access time and 4GB/s data bandwidth. Sample shipments will begin on June 1, 2004.

• http://www.hitachi.com/New/cnews/040115.html

Dr. Wang

Semiconductor Memory Types(Internal and Random Access)

Read-write memory

Read-mostlymemory

Read-only memory

Random-access memory (RAM)

Read-onlyMemory (ROM)

ProgrammableROM (PROM)

Erasable PROM(EPROM)

Electrically Erasable PROM (EEPROM)

Flash memory

Static RAM(SRAM)

Dynamic RAM(DRAM)

Synchronous DRAM (SDRAM)

Rambus DRAM (RDRAM)

Cache DRAM (CDRAM)

Dr. Wang

Read-Only Memory (ROM)

• Written only once during manufacturing

• Can be read, but cannot be written later

• Is nonvolatile, nonerasable

• Applications:– microprogramming, system programs, library subroutines

• Advantage– data/programs are permanently in main memory

• Problems– costly for small runs, but attractive for high-volume runs

– no room for error

Semiconductor Internal Random Access Memory Types – ROM (1)

Dr. Wang

Programmable ROM (PROM)

• Written only once after manufacturing• Can be read, but cannot be written later• Is nonvolatile, non-erasable• Attractive for small production runs

• Advantages:– flexible and convenient– less expensive

Semiconductor Internal Random Access Memory Types – ROM (2)

Dr. Wang

Erasable PROM (EPROM)

• Can be written many times• Erased by ultraviolet radiation before each write

operation at chip level• Erasure (20 mins) can be performed repeatedly• Is nonvolatile• Pros & cons:

– Capable of multiple update

– More expensive than PROM

Semiconductor Internal Random Access Memory Types – Read-Mostly Memory (1)

Dr. Wang

Electrically EPROM (EEPROM)

• Erased and updated at the byte level• Takes much longer to write than read• Is nonvolatile• More expensive and less dense than EPROM

Semiconductor Internal Random Access Memory Types – Read-Mostly Memory (2)

Dr. Wang

Flash Memory

• Intermediate between EPROM and EEPROM in both cost and functionality

• Electrical and fast erasure (a few seconds/memory)• Can be erased at block level

Semiconductor Internal Random Access Memory Types – Read-Mostly Memory (3)

Dr. Wang

Agenda

The basic element

– The memory cell

Semiconductor memory types

– RAM, DRAM, SRAM; SDRAM, RDRAM, CDRAM

– ROM, PROM

– EPROM, EEPROM, flash memory

• Memory organizations

Dr. Wang

Two Extremes In Organization (1)

• Physical arrangement of cells in the array is the same as the logical arrangement of words in memory (one-word-per-chip)– A 256 KByte chip can be organized as 256K 8-bit words

• One-bit-per-chip organization– Each chip provides 1 bit input/output at a time

– A 256 KByte one-bit-per-chip system has 8 lots of 256Kbit chip with bit 1 of each word in chip/lot 1, and so on

Dr. Wang

256-KByte Memory

One-word-per-chip Organization

• 256K rows of 8-bit words• 18 address lines

Two Extremes In Memory Organization (2)

.

.

.

1word = 8bitsbit0bit7

Address Decoder

A0

A1

A17

…

Word 0

Word 256K-1

.

.

.

Dr. Wang

256-KByte Memory

One-bit-per-chip Organization

• 512 x 512 per chip• 18 address lines

– 9 for row

– 9 for column

Two Extremes In Memory Organization (3)

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16-Mbit Memory Organization (1)DRAM

Examples of Memory Organizations (I)

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16-Mbit Memory Organization (2)DRAM

• Organized as a 2048 x 2048 x 4bit array– The physical arrangements is one-word-per-chip

– Reduced number of address pins • Multiplexed row address and column address

• 11 pins, rather than 22 pins

• Adding 1 more pin doubles number of rows and columns and so x4 capacity

– Refresh circuit included on chip• Refreshed by reading out data and writing back

• Cells in the same row are refreshed simultaneously

Examples of Memory Organizations (I)

Dr. Wang

16-Mbit DRAM (3)Chip Packaging

• A0-A10: multiplexed address

• D1-D4: data

• WE: write enable

• OE: output enable

• RAS/CAS: row/column address select

• Vcc: voltage source

• Vss: ground

• NC: no connect, for even #

Examples of Memory Organizations (I)

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8-Mbit Memory Organization (1) Examples of Memory Organizations (II)

Dr. Wang

8-Mbit Memory Organization (2)

• Organized as a 512 x 512 x 32 bit array– The physical arrangements is one-bit-per-chip

– 4 columns of chips, each containing 256K words (512 x 512 x 8 bits)

– Group select logic select one of 4 columns

– 20 address pins • 18 pins for selecting 1 of 512 x 512 bits

• 2 pins for selecting 1 0f 4 columns

– No refresh circuit is needed

Examples of Memory Organizations (II)

Dr. Wang

8-Mbit EPROM (3)Chip Packaging

• A0-A19: address

• D0-D7: data

• CE: chip enable

• Vcc: power supply

• Vss: ground

• Vpp: program voltage, supplied during programming/writing

Examples of Memory Organizations (II)

Dr. Wang

Hands-on Problems

• There are two extreme designs in memory organization: “one-word-per-chip” and “one-bit-per-chip”.   Design a 4-Kbyte memory using each of the two design strategies.

Dr. Wang

Summary of Lecture #5• The basic element

– The memory cell

• Semiconductor memory types– RAM, DRAM, SRAM; SDRAM, RDRAM, CDRAM

– ROM, PROM

– EPROM, EEPROM, flash memory

• Memory organizations– One-word-per-chip

– One-bit-per-chip

– Examples: 16 Mbit, 8 Mbit, 256 KByte

Dr. Wang

CPUCACHE

MAINMEMORY

MAINMEMORY

I/O STORAGE DEVICES

Registers

Internal Memory

ExternalMemory

plus Virtual Memory

Defer to CPU discussion

Next topic: Cache Memory

Dr. Wang

Things To Do

• Project proposal –due Oct. 28, Wednesday

• Check out the class website about–lecture notes–reading assignments–the project

Dr. Wang

Solution

Dr. Wang

SAMSUNG 512MB 800MHZ 184PIN RAMBUS MEMORY

Dr. Wang

KINGSTON 256MB

800MHZ 184PIN

RAMBUS MEMORY