ECE 4510/5530 Microcontroller Applications ECT and PWMbazuinb/ECE4510/Ch08.pdf · ECE 4510/5530 Microcontroller Applications Chapter 8 ECT and PWM Dr. Bradley J. Bazuin ... – TFLG1

ECE 4510/5530Microcontroller Applications

Chapter 8ECT and PWM

Dr. Bradley J. BazuinAssociate Professor

Department of Electrical and Computer EngineeringCollege of Engineering and Applied Sciences

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Chapter 8

• Enhanced Capture Timer– 16-bit main counter with 7-bit prescaler– 8 programmable input capture or output compare channels– Two 8-bit or one 16-bit pulse accumulators

• 8 PWM channels– Programmable period and duty cycle– 8-channel 8-bit or 4-channel 16-bit – Separate control for each pulse width and duty cycle– Center-aligned or left-aligned outputs– Programmable clock select logic with a wide range of frequencies– Fast emergency shutdown input– Usable as interrupt inputs

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Memory Addresses

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Adapt9S12DP512 I/O Pins

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Overview of Timer Functions

• Many applications require a dedicated timer system– Time delay creation and measurement– Period and pulse width measurement– Frequency measurement– Event counting– Arrival time comparison– Time of day tracking– Periodic interrupt generation– Waveform Generation

• The TIM (and ECT also) shares the eight Port T pins (IOC0…IOC7).

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Overview of Timer Functions

• The applications mentioned will be very difficult to implement without a dedicated timer system

• HCS12 implements a very complicated timer system to support the implementation of these applications– HCS12 microcontroller consists of a 16-bit timer counter– The timer can be started or stopped according to the wishes of the

programmer

• Three different timer functions can be implemented in HCS12– Input-capture– Output compare– Timer overflow

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The HCS12 Timer System (1 of 2)

• The HCS12 has a standard timer module (TIM) that consists of: – Eight channels of multiplexed input capture and output compare functions.– 16-bit pulse accumulator A– 16-bit timer counter– The TIM block diagram is shown in Figure 8.1.

• The DP512 devices have implemented an Enhanced Capture Timer module (ECT). The ECT module contains:– All the features contained in the TIM module– One 16-bit buffer register for each of the input capture channels– Four 8-bit pulse accumulator– A 16-bit Modulus Down Counter with 4-bit prescaler– Four user selectable delay counters for increasing input noise immunity

• The TIM (of course ECT also) shares the eight Port T pins (IOC0…IOC7).

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The HCS12 Timer System (2 of 2)

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• Pulse width measurement: need to capture the rising and falling edges

one period

(a) Capture two rising edges

one period

(b) Capture two falling edges

Figure 8.9 Period measurement by capturing two consecutive edges

Pulse width

Rising edge Falling edge

Figure 8.10 Pulse-width measurement using input capture

Applications of Input Capture Function

• Event arrival time recording

• Period measurement: need to capture the main timer values corresponding to two consecutive rising or falling edges

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• Time reference: input-capture used in conjunction with an output compare function

Start ofinterval

End ofinterval

e1 e2 e3 e4 ei ej

Figure 8.11 Using an input-capture function for event counting

... ...

Time t0

Time of reference(set up by signal edge)

Time t0 + delay

Time to activateoutput signal

(set up by output compare)Figure 8.12 A time reference application

Input Capture

• Interrupt generation: Each input capture function can be used as an edge-sensitive interrupt source.

• Event counting: count the number of signal edges arrived during a period

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T

T

duty cycle =T

T* 100%

Figure 8.13 Definition of duty cycle

Duty Cycle Measurement

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T

T

signal S1

signal S2

phase difference =T

T* 360o

Figure 8.14 Phase difference definition for two signals

Phase Difference Measurement

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T Pin Related Registers

• Timer Counter Registers– TIOS = $40– TCFORC = $41– TOC7M = $42– TOC7D = $43

– TCNT = $44 (16-bit)– TSCR1 = $46– TTOV = $47– TCTL1 = $48– TCTL2 = $49– TCTL3 = $4A– TCTL4 = $4B– TIE = $4C– TSCR2 = $4D– TFLG1 = $4E– TFLG2 = $4F

• Timer Counter Registers– TC0 = $50 (16-bit)– TC1 = $52 (16-bit)– TC2 = $54 (16-bit)– TC3 = $56 (16-bit)– TC4 = $58 (16-bit)– TC5 = $5A (16-bit)– TC6 = $5C (16-bit)– TC7 = $5E (16-bit)

– and more through $7F

The HCS12 Timer Elements

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Prescaler

16-bit counter

Input CaptureOutput compare

Channel 0


Channel 1


Channel 2


Channel 3


Channel 4


Channel 5


Channel 6


Channel 7

Registers

16-bit Pulseaccumulator A

IOC0

IOC1

IOC2

IOC3

IOC4

IOC5

IOC6

IOC7

Bus clock

Timer overflowinterrupt

TC0 interrupt

TC1 interrupt

TC2 interrupt

TC3 interrupt

TC4 interrupt

TC5 interrupt

TC6 interrupt

TC7 interrupt

PA overflowinterruptPA inputinterrupt

Figure 8.1 HCS12 Standard Timer (TIM) block diagram

• 16-bit free-running main timer

– Prescalaer• 16-bit modulus

downcounter– Prescalaer– Load

• Control Registers• Interrupt Registers• Capture/Compare Registers

Timer Block Diagram (Latch Mode)

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Prescaler 16-bit free-runningmain timer

pin logic Delaycounter

comparator

TCx capture/compareregister

TCxH hold register

EDG x

Prescalerbus clock÷1, 4, 8, 16

÷1,2,...,128 16-bit load register

16-bit modulusdown counter

ICLAT, LATQ, BUFEN(force latch)

write $0000 tomodulus counter

LATQ(MDC latch enable)

Latc

hFigure 8.35 Enhanced Input capture function block diagram in latch mode

to other IC channels

bus clock

PTxone IC channel

(IC0..IC3)

pin logicPTicomparator

TCx capture/compareregisterMUX

EDG i

EDG jj = 8 - i

one IC channel(IC4..IC7)

Timer Block Diagram (Queue Mode)

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Prescaler 16-bit free-runningmain timer

pin logic Delaycounter

comparator

TCx capture/compareregister

TCxH hold register

EDG x

Prescalerbus clock÷1, 4, 8, 16

÷1,2,...,128 16-bit load register

16-bit modulusdown counter

Figure 8.36 Enhanced Input capture function block diagram in Queue mode (channels IC0..IC3 block diagram)

to other IC channels

bus clock

PTxone IC channel

(IC0..IC3)

pin logicPTicomparator

TCx capture/compareregisterMUX

EDG i

EDG jj = 8 - i

one IC channel(IC4..IC7)

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Timer Counter Register (TCNT)

• Required for input capture and output compare functions. An up counter.

• Must be accessed in one 16-bit operation in order to obtain the correct value

• Three other registers related to the operation of the TCNT: TSCR1, TSCR2, TFLG2.

The 16-bit main timer is an up counter.

A full access for the counter register should take place in one clock cycle. A separate read (any mode)/write (test mode) for high byte and low byte will give a different result than accessing them as a word.

Read anytime.

Write has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1).

The period of the first “count” after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock.

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Running the TCNT Counter

• Timer Counter Register 1 (TSCR1)– Select the mode of operation for the module

• STOP: Timer and modulus counter are off since clocks are stopped.• FREEZE: Timer and modulus counter keep on running, unless TSFRZ in TSCR($06) is set to

one.• WAIT: Counters keep on running, unless TSWAI in TSCR ($06) is set to one.• NORMAL: Timer and modulus counter keep on running, unless TEN in TSCR($06)

respectively MCEN in MCCTL ($26) are cleared.

• Timer Counter Register 2 (TSCR2)– Timer prescale counting factor, timer overflow IE, and timer counter

reset enable

• Timer Interrupt Flag 2 Register (TFLG2)– Bit 7 (TOF) Set when 16-bit free-running timer overflows from

$FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.)

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7 6 5 4 3 2 1 0

TEN TSWAI TSFRZ TFFCA 0 0 0 0valueafter reset 0 0 0 0 0 0 0 0

TEN -- timer enable bit

0 = disable timer; this can be used to save power consumption1 = allows timer to function normally

TSWAI -- timer stops while in wait mode bit0 = allows timer to continue running during wait mode1 = disables timer when MCU is in wait mode

TSFRZ -- timer and modulus counter stop while in freeze mode0 = allows timer and modulus counter to continue running while in freeze mode1 = disables timer and modulus counter when MCU is in freeze mode

TFFCA -- timer fast flag clear all bit0 = allows timer flag clearing to function normally1 = For TFLG1, a read from an input capture or a write to the output compare channel causes the corresponding channel flag, CnF, to be cleared. For TFLG2, any access to the TCNT register clears the TOF flag. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.

Figure 8.2 Timer system control register 1 (TSCR1)

Timer System Control Register 1 (TSCR1)

• Setting and clearing the bit 7 of TSCR1 will start and stop the counting of the TCNT.

• Setting the bit 4 will enable fast timer flag clear function. If this bit is clear, then the user must write a one to a timer flag in order to clear it.

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Timer System Control Register 2 (TSCR2)

• Bit 7 is the TCNT overflow interrupt enable bit.

• The clock input (E-CLK) to TCNT (E-Clock) can be prescaled by a factor selecting by bits 2 to 0 of TSCR2.

• TCNT can be reset to 0 when TCNT equals TC7 by setting bit 3 of TSCR2.

7 6 5 4 3 2 1 0

TOI 0 0 0 TCRE PR2 PR1 PR0valueafter reset 0 0 0 0 0 0 0 0

TOI -- timer overflow interrupt enable bit 0 = interrupt inhibited 1 = interrupt requested when TOF flag is setTCRE -- timer counter reset enable bit 0 = counter reset inhibited and counter free runs 1 = counter reset by a successful output compare 7 If TC7 = $0000 and TCRE = 1, TCNT stays at $0000 continuously. If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT rolls over from $FFFF to $0000.

Figure 8.3 Timer system control register 2 (TSCR2)

PR2 PR1 PR0 Prescale Factor

00001111

00110011

01010101

1248163264

128

Table 8.1 Timer counter prescale factor

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Timer Interrupt Flag 2 Register (TFLG2)

• Only bit 7 (TOF) is implemented. – Bit 7 will be set

whenever TCNT overflows.

TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one.

Read anytime. Write used in clearing mechanism (set bits cause corresponding bits to be cleared).

Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.

TOF — Timer Overflow Flag

Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.)

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Using TCNT Values

• Once the counter is set up, the timer functions can be used to:

• In - Input-Capture:– The TCNT value is

captured when the desired external event occurs

• Out - Output-Compare:– The output occurs when

TCNT equals the preset register value

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Timer Port Pins

• Each port pin can be used as a general I/O pin when timer function is not selected.

• Pin 7 can be used as input capture 7, output compare 7 action, and a pulse accumulator input.– The pulse accumulation function is unique to this pin.

• When a timer port pin is used as a general I/O pin, its direction is configured by the DDRT register.

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INPUT CAPTURE

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or

Figure 8.4 Events represented by signal edges

Input Capture Functions (1 of 2)

• Physical time is often represented by the contents of the main timer.• The time when an event occurs can be recorded by latching the count

of the main timer when a signal edge arrives as illustrated in Figure 8.4.– The occurrence of an event is represented by a signal edge (rising or

falling edge).– The HCS12 has eight input capture channels. Each channel has a 16-bit

capture register, an input pin, edge-detection logic, and interrupt generation logic.

• Input capture channels share most of the circuit with output compare functions. For this reason, they cannot be enabled simultaneously.

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• The selection of input capture and output compare is done by programming the TIOS register.

• The contents of the TIOS register are shown in Figure 8.5. Setting a bit select the output compare function. Otherwise, the input capture function is selected.

• The following instruction will enable the output compare channels 7...4 and input capture channel 3…0:

• movb #$F0,TIOS

7 6 5 4 3 2 1 0

IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0valueafter reset 0 0 0 0 0 0 0 0

Figure 8.5 Timer input capture/output compare select register (TIOS)

IOS[7:0] -- Input capture or output compare channel configuration bits 0 = The corresponding channel acts as an input capture 1 = The corresponding channel acts as an output compare

Input Capture Functions (2 of 2)

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7 6 5 4 3 2 1 0

EDG7 B EDG7 A EDG6 B EDG6 A EDG5 B EDG5 A EDG4 B EDG4 Avalueafte r re se t 0 0 0 0 0 0 0 0

Figure 8 .5 Tim er co ntro l regis te r 3 and 4

7 6 5 4 3 2 1 0

EDG3 B EDG3 A EDG2 B EDG2 A EDG1 B EDG1 A EDG0 B EDG0 A

0 0 0 0 0 0 0 0

(a) Tim er co ntro l regis te r 3 (TCTL3 )

(b) Tim er co ntro l regis te r 4 (TCTL4 )

EDGnB EDGnA -- Edge co nfiguratio n

0 0 : Capture disabled0 1 : Capture o n ris ing edges o nly1 0 : Capture o n falling edges o nly1 1 : Capture o n bo th edges

Timer Control Register 3 and 4

• The signal edge to be captured is selected by TCTL3 and TCTL4.

• The edge to be captured is selected by two bits. The user can choose to capture the rising edge, falling edge, or both edges.

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7 6 5 4 3 2 1 0

C7I C6I C5I C4I C3I C2I C1I C0I

reset: 0 0 0 0 0 0 0 0

Figure 8.7 Timer interrupt enable register (TIE)

C7I-C0I: input capture/output compare interrupt enable bits 0 = interrupt disabled 1 = interrupt enabled

Timer Interrupt Enable Register (TIE)

• The arrival of a signal edge may optionally generate an interrupt to the CPU.

• The enabling of the interrupt is controlled by the Timer Interrupt Enable Register.

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7 6 5 4 3 2 1 0

C7F C6F C5F C4F C3F C2F C1F C0Freset: 0 0 0 0 0 0 0 0

Figure 8.8 Timer interrupt flag register 1 (TFLG1)

CnF: input capture/output compare interrupt flag bits 0 = interrupt condition has not occurred 1 = interrupt condition has occurred

Timer Interrupt Flag 1 Register (TFLG1)

• Whenever a signal edge arrives, the associated timer interrupt flag will be set to 1.

• Read anytime. Write used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit.

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How to Clear a Timer Flag Bit

• In normal mode, write a 1 to the flag bit to be cleared.• Method 1

– BSET TFLG1, $01 ;will clear the C0F flag. • Method 2

– movb #$01,TFLG1 ;will clear the C0F flag.

• C-code– TFLG1 |= C0F; //clear the C0F Flag

• When the fast timer flag clear function is enabled (TFFCA bit in the TSCR register is set), a read from an input capture or a write into an output compare channel ($10–$1F) will cause the corresponding channel flag CnF to be cleared. See Figure 8.1.

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Example 8.2: Period Measurement (1 of 2)

• Use the IC0 to measure the period of an unknown signal. The period is known to be shorter than 128 ms. Assume that the E clock frequency is 24 MHz. Use the number of clock cycles as the unit of the period.

Solution: • Since the input-capture register is 16-bit, the longest period of the

signal that can be measured with the prescaler to TCNT set to 1 is: – 2^16 ÷ 24 MHz = 2.73 ms.

• To measure a period that is equal to 128 ms, we have two options: – Set the prescale factor to 1 and keep track of the number of times the timer

counter overflows.– Set the prescale factor to 64 and do not keep track of the number of times

the timer counter overflows. • We will set the prescale factor to TCNT to 64

(2^16 ÷ 24 MHz /64 = 174.76 ms or 2 2/3 usec time steps). The logic flow for measuring the signal period is shown in Figure 8.16.

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Start

Choose to capture the rising edgeSet the timer counter prescale factor to 16Enable the timer counter

Clear the C0F flag

C0F = 1?

yes

no

Saved the captured first edgeClear the C0F flag

C0F = 1?no

yes

Take the difference of the second and thefirst captured edges

Stop

Figure 8.16 Logic flow of period measurement program

Example 8.2: Period Measurement (2 of 2)

one period

(a) Capture two rising edges

one period

(b) Capture two falling edges

Figure 8.9 Period measurement by capturing two consecutive edges

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#include "c:\miniide\hcs12.inc".org $1000edge1: .byte 2 ; memory to hold the first edgeperiod: .byte 2 ; memory to store the period.text_main::

movb #$90,TSCR1 ; enable timer counter and enable fast timer flags clearbclr TIOS,IOS0 ; enable input-capture 0movb #$06,TSCR2 ; disable TCNT overflow interrupt, set prescaler to 64movb #$01,TCTL4 ; capture the rising edge of PT0 signalmovb #C0F,TFLG1 ; clear the C0F flag

L1: brclr TFLG1,C0F,L1 ; wait for the arrival of the first rising edgeldd TC0 ; save the first edge and clear the C0F flagstd edge1

L2: brclr TFLG1,C0F,L2 ; wait for the arrival of the second edgeldd TC0subd edge1 ; compute the periodstd periodswi

Example 8.2: Assembly Program for Period Measurement

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#include "c:\egnu091\include\hcs12.h"void main(void){

unsigned int edge1, period;TSCR1 = 0x90; /* enable timer counter, enable fast flag clear*/TIOS &= ~IOS0; /* enable input-capture 0 /TSCR2 = 0x06; /* disable TCNT overflow interrupt, set prescaler to 64 */TCTL4 = 0x01; /* capture the rising edge of the PT0 pin */TFLG1 = C0F; /* clear the C0F flag */while (!(TFLG1 & C0F)); /* wait for the arrival of the first rising edge */edge1 = TC0; /* save the first captured edge and clear C0F flag */while (!(TFLG1 & C0F)); /* wait for the arrival of the second rising edge */period = TC0 - edge1;asm ("swi");

}

Example 8.2: C Program for Period Measurement

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Case 1: edge2 edge1pulse width = ovcnt × 216 + diff

Case 2: edge2 < edge 1pulse width = (ovcnt – 1) × 216 + diff

Example 8.3: Measure the Pulse Width

• Write a program to measure the pulse width of a signal connected to the PT0 pin. The E clock frequency is 24 MHz.

• Solution:– Set the prescale factor to TCNT to 32. Use clock cycle as the unit of

measurement. (1 1/3 usec time steps)– The pulse width may be longer than 2^16 clock cycles (87.4 msec). We need

to keep track of the number of times that the TCNT timer overflows. Let• ovcnt = TCNT counter overflow count• diff = the difference of two consecutive edges• edge1 = the captured time of the first edge• edge2 = the captured time of the second edge

– The pulse width can be calculated by the following equations:

Pulse width


Figure 8.10 Pulse-width measurement using input capture

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Example 8.3 Flow Diagram

Note: an interrupt is used

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#include "c:\miniide\hcs12.inc".org $1000edge1: .byte 2overflow: .byte 2 ; overflow and pulse-width form a 32-bitpulse_width: .byte 2 ; long word for the solution.text_main::

movw #tov_isr,UserTimerOvf ; set up TCNT overflow interrupt vectorlds #$3C00 ; set up stack pointermovw #0, overflowmovb #$90, TSCR1 ; enable TCNT and fast timer flag clearmovb #$05, TSCR2 ; disable TCNT interrupt, set prescaler to 32bclr TIOS, IOS0 ; select IC0movb #$01, TCTL4 ; capture rising edgemovb #C0F, TFLG1 ; clear C0F flag

wait1: brclr TFLG1,C0F,wait1 ; wait for the first rising edgemovw TC0,edge1 ; save the first edge & clear the C0F flagmovb #TOF,TFLG2 ; clear TOF flagbset TSCR2,$80 ; enable TCNT overflow interruptcli ; "movb #$02,TCTL4 ; capture the falling edge on PT0 pin

wait2: brclr TFLG1,C0F,wait2 ; wait for the arrival of the falling edge

Example 8.3: Code (1)

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ldd TC0subd edge1std pulse_widthbcc next ; is the second edge smaller?ldx overflow ; second edge is smaller, so decrementdex ; overflow count by 1stx overflow ; "

next swi

tov_isr movb #TOF, TFLG2 ; clear TOF flagldx overflowinxstx overflowrti

Example 8.3: Code (2)

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#include <hcs12.h>#include <vectors12.h>#define INTERRUPT __attribute__((interrupt)) unsigned diff, edge1, overflow;unsigned long pulse_width;void INTERRUPT tovisr(void);void main(void){

UserTimerOvf = (unsigned short)&tovisr;overflow = 0;TSCR1 = 0x90; /* enable timer and fast flag clear */TSCR2 = 0x05; /* set prescaler to 32, no timer overflow interrupt */TIOS &= ~IOS0; /* select input-capture 0 */TCTL4 = 0x01; /* prepare to capture the rising edge */TFLG1 = C0F; /* clear C0F flag */while(!(TFLG1 & C0F)); /* wait for the arrival of the rising edge */TFLG2 = TOF; /* clear TOF flag */

Example 8.3: C Program for Pulse Width Measurement (1 of 2)

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TSCR2 |= 0x80; /* enable TCNT overflow interrupt */asm("cli");edge1 = TC0; /* save the first edge */TCTL4 = 0x02; /* prepare to capture the falling edge */while (!(TFLG1 & C0F)); /* wait for the arrival of the falling edge */diff = TC0 - edge1;if (TC0 < edge1)

overflow -= 1;pulse_width = overflow * 65536u + diff;asm ("swi");

}

void INTERRUPT tovisr(void){

TFLG2 = TOF; /* clear TOF flag */overflow = overflow + 1;

}

Example 8.3: C Code (2 of 2)

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Output Compare Function

• The HCS12 has eight output compare functions.• Each output compare channel consists of

– A 16-bit comparator– A 16-bit compare register TCx (also used as input capture register)– An output action pin (PTx, can be pulled high, pulled low, or

toggled)– An interrupt request circuit– A forced-compare function (CFOCx)– Control logic

OUTPUT COMPARE

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ECE 2510

Output Compare Function

• The HCS12 has eight output compare functions.• Each output compare channel consists of

– A 16-bit comparator– A 16-bit compare register TCx (also used as input capture register)– An output action pin (PTx, can be pulled high, pulled low, or

toggled)– An interrupt request circuit– A forced-compare function (CFOCx)– Control logic

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Operation of the Output-Compare

• One of the applications of the output-compare function is to trigger an action at a specific time in the future.

• To use an output-compare function, the user– Makes a copy of the current contents of the TCNT register– Adds to this copy a value equal to the desired delay– Stores the sum into an output-compare register (TCx, x = 0..7)

• A successful compare will set the corresponding flag bit in the TFLG1 register.

• An interrupt may be optionally requested if the associated interrupt enable bit in the TIE register is set.

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7 6 5 4 3 2 1 0

OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4valueafter reset 0 0 0 0 0 0 0 0

read: anytimewrite: anytime

Figure 8.18 Timer control register 1 and 2 (TCTL1 & TCTL2)

7 6 5 4 3 2 1 0

OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0

0 0 0 0 0 0 0 0

(a) TCTL1 register

(b) TCTL2 register

valueafter reset

OMn OLn : output level0011

0101

no action (timer disconnected from output pin)toggle OCn pinclear OCn pin to 0set OCn pin to high

Control of the Output-Compare

• The actions that can be activated on an output compare pin include– Pull up to high– Pull down to low– Toggle

• The action is determined by the Timer Control Register 1 & 2 (TCTL1 & TCTL2):

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300 s

700 s

Figure 8.19 1 KHz 30 percent duty cycle waveform

Example 8.4 Output-Compare

• Example 8.4 Generate an active high 1 KHz digital waveform with 30 percent duty cycle from the PT0 pin. – Use the polling method to check the success of the output compare

operation. The frequency of the E clock is 24 MHz.

• Solution: An active high 1 KHz waveform with 30 percent duty cycle is shown in Figure 8.19. The logic flow of this problem is illustrated in Figure 8.20.– Setting the prescaler to the TCNT to 8, then the period of the clock

signal to the TCNT will be 1/3 ms. The numbers of clock cycles that the signal is high and low are 900 and 2100, respectively.

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Start

Select pull high as pin action

Clear C0F flag

Start OC0 output comparewith a delay of 700 s

C0F = 1?

Select pull low as pin actionClear C0F flagStart OC0 output comparewith a delay of 300 s

C0F = 1?

no

no

yes

yes

Figure 8.20 The program logic flow for digital waveform generation

Example 8.4 Flow Diagram

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#include "c:\miniide\hcs12.inc"hi_time = 900lo_time = 2100.text_main::

movb #$90,TSCR1 ; enable TCNT with fast timer flag clearmovb #$03,TSCR2 ; disable TCNT interrupt, set prescaler to 8bset TIOS,OC0 ; enable OC0movb #$03,TCTL2 ; select pull high as pin actionldd TCNT ; start an OC0 operation with 700 us as delay

repeat: addd #lo_time ; "std TC0 ; "

low: brclr TFLG1,C0F,low ; wait until OC0 pin go highmovb #$02,TCTL2 ; select pull low as pin actionldd TC0 ; start an OC operation with 300 us as delayaddd #hi_time ; "std TC0 ; "

high: brclr TFLG1,C0F,high ; wait until OC0 pin go lowmovb #$03,TCTL2 ; select pull high as pin actionldd TC0bra repeat

Example 8.4 Assembly Code

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#include "c:\egnu091\include\hcs12.h"#define hi_time 900#define lo_time 2100void main (void){

TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */TIOS |= OC0; /* enable OC0 function */TSCR2 = 0x03; /* disable TCNT interrupt, set prescaler to 8 */TCTL2 = 0x03; /* set OC0 action to be pull high */TC0 = TCNT + lo_time; /* start an OC0 operation */while(1) {

while(!(TFLG1 & C0F)); /* wait for PT0 to go high */TCTL2 = 0x02; /* set OC0 pin action to pull low */TC0 += hi_time; /* start a new OC0 operation */while(!(TFLG1 & C0F)); /* wait for PT0 pin to go low */TCTL2 = 0x03; /* set OC0 pin action to pull high */TC0 += lo_time; /* start a new OC0 operation */

}}

Example 8.4 C Code

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Example 8.5: 1 msec Time Delay

• Write a function to generate a time delay which is a multiple of 1 ms. – Assume that the E clock frequency is 24 MHz. The number of

milliseconds is passed in Y. Also write an instruction sequence to test this function.

Solution: • One method to create 1 ms delay is as follows:

– Set the prescaler to TCNT to 64– Perform the number of output-compare operations (given in Y)

with each operation creating a 1-ms time delay.– The number to be added to the copy of TCNT is 375. (375 64

24000000 = 1 ms)

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delayby1ms: pshdmovb #$90,TSCR1 ; enable TCNT & fast flags clearmovb #$06,TSCR2 ; configure prescaler to 64bset TIOS,OC0 ; enable OC0ldd TCNT

again0: addd #375 ; start an output-compare operationstd TC0 ; with 1 ms time delay

wait_lp0: brclr TFLG1,OC0,wait_lp0ldd TC0dbne y,again0puldrts

Example 8.5: Y x 1 msec Time Delay Subroutine

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void delayby1ms(int k){

int ix;TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */TSCR2 = 0x06; /* disable timer interrupt, set prescaler to 64 */TIOS |= OC0; /* enable OC0 */TC0 = TCNT + 375;for (ix = 0; ix < k; ix++) {

while(!(TFLG1 & C0F));TC0 += 375;

}TIOS &= ~OC0; /* disable OC0 */

}

Example 8.5: C Code

See Textbook CD: Utilities/delay.cThe above is from the old textbook CD

Textbook Delay Code

• Delay.asm– delayby50us ; multiple passed in Y reg– delayby1ms ; multiple passed in Y reg– delayby10ms ; multiple passed in Y reg– delayby100ms ; multiple passed in Y reg

• Delay.c– void delayby10us(int k);– void delayby50us(int k); /* time delay based on */– void delayby1ms(int k); /* 24 MHz E-clock. */– void delayby10ms(int k);– void delayby100ms(int k);

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Example 8.6: Estimate Frequency

• Use an input-capture and an output-compare functions to measure the frequency of the signal connected to the PT0 pin.

• Solution: To measure the frequency, we will– Use one of the output-compare function to create a one-second

time base.– Keep track of the number of rising (or falling) edges that arrived at

the PT0 pin within one second.

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#include "c:\MiniIDE\hcs12.inc"CR = $0DLF = $0A.org $1000oc_cnt .blkb 1frequency .blkb 2msg: .byte CR,LF

.ascii “The frequency is %d“

.byte CR,LF,0

.org $3E6E ; set up interrupt vector number.word TC0_isr ; for TC0

.text_main::

movb #$90,TSCR1 ; enable TCNT and fast timer flags clearmovb #$02,TSCR2 ; set prescale factor to 4movb #$02,TIOS ; enable OC1 and IC0movb #100,oc_cnt ; prepare to perform 100 OC1 operation, each

; creates 10 ms delay and total 1 secondmovw #0,frequency ; initialize frequency count to 0movb #$01,TCTL4 ; prepare to capture the rising edges of PT0movb #C0F,TFLG1 ; clear the C0F flagbset TIE,IC0 ; enable IC0 interruptcli ; "

Example 8.6: Estimate Frequency (1 of 2)

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ldd TCNT ; start an OC1 operation with 10 ms delaycontinue: addd #60000 ; "

std TC1 ; "w_lp: brclr TFLG1,C1F, w_lp; wait for 10 ms

ldd TC1dec oc_cntbne continuesei ; set I, disabling all interrupts ldd frequencypshdldd #msgldx #00jsr [printf, X]leas 2,spswi

TC0_isr: ldd TC0 ; clear C0F flagldx frequency ; increment frequency count by 1inx ; "stx frequency ; rti

Example 8.6: Code (2 of 2)

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#include <hcs12.h>#include <vectors12.h>#include <convert.c>#include <stdio.c>#define INTERRUPT __attribute__((interrupt))unsigned int frequency;void INTERRUPT TC0_isr(void);void main(void){

char arr[7];char *msg = "Signal frequency is ";int i, oc_cnt;unsigned frequency;UserTimerCh0 = (unsigned short)&TC0_isr;TSCR1 = 0x90; /* enable TCNT and fast flag clear */TSCR2 = 0x02; /* set prescale factor to 4 */TIOS = 0x02; /* select OC1 and IC0 */oc_cnt = 100; /* prepare to perform 100 OC1 operations */frequency = 0;


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TCTL4 = 0x01; /* prepare to capture PT0 rising edge */TFLG1 = C0F; /* clear C0F flag */TIE |= IC0; /* enable IC0 interrupt */asm("cli");TC1 = TCNT + 60000;while (oc_cnt) {

while(!(TFLG1 & C1F));TC1 = TC1 + 60000;oc_cnt = oc_cnt - 1;

}asm(“sei");int2alpha(frequency, arr);puts(msg);puts(&arr[0]);asm("swi");

}void INTERRUPT TC0_isr(void){

TFLG1 = C0F; /* clear C0F flag */frequency ++;

}


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HCS12DP256

PT5

3.3 F

Buzzer

Figure 8.21 Circuit connection for a buzzer

Making Sound Using the Output-Compare Function

• A sound can be generated by creating a digital waveform with appropriate frequency and using it to drive a speaker or a buzzer.

• The simplest song is a two-tone siren.

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Example 8.7: Algorithm for Generating a Siren

• Step 1– Enable an output compare channel to drive the buzzer (or speaker).

• Step 2– Start an output compare operation with a delay count equal to half the period of the

siren and enable the OC interrupt.• Step 3

– Wait for the duration of the siren tone (say half a second). During the waiting period, interrupts will be requested many times by the output compare function. The interrupt service routine simply restart the output compare operation.

• Step 4– At the end of the siren tone duration, choose a different delay count for the output

compare operation so that the siren sound may have a different frequency.• Step 5

– Wait for the same duration as in Step 3. During this period, many interrupts will be requested by the output compare operation.

• Step 6– Go to Step 2.

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Example 8.7 Siren Generation

• Write a program to generate a two-tone siren that oscillates between 300 Hz and 1200 Hz.

• Solution:– Set the prescaler to TCNT to 1:8.– The delay count for the low frequency tone is (24000000 8)

300 2 = 5000.– The delay count for the high frequency tone is (24000000 8)

1200 2 = 1250.

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#include "c:\miniide\hcs12.inc"hi_freq = 1250 ; delay count for 1200 Hz (with 1:8 prescaler)lo_freq = 5000 ; delay count for 300 Hz (with 1:8 prescaler)toggle = $04 ; value to toggle the TC5 pin.org $1000delay: .blkw 1 ; store the delay for output-compare operation

.text_main::

lds #$3C00movw #oc5_isr,UserTimerCh5 ; initialize the interrupt vector entrymovb #$90,TSCR1 ; enable TCNT, fast timer flag clearmovb #$03,TSCR2 ; set main timer prescaler to 8bset TIOS,OC5 ; enable OC5movb #toggle,TCTL1 ; select toggle for OC5 pin actionmovw #hi_freq,delay ; use high frequency delay count firstldd TCNT ; start the low frequency soundaddd delay ; "std TC5 ; "bset TIE,OC5 ; enable OC5 interruptcli

Example 8.7 Siren Generation (1 of 2)

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forever: ldy #5 ; wait for half a secondjsr delayby100ms ; "movw #lo_freq, delay ; switch to low frequency delay countldy #5jsr delayby100msmovw #hi_freq, delay ; switch to high frequency delay countbra forever

oc5_isr: ldd TC5 ; half period of frequencyaddd delaystd TC5rti

#include c:\miniide\delay.asm”

Code (2 of 2)

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#include "c:\egnu091\include\hcs12.h"#include "c:\egnu091\include\delay.c"#define HiFreq 1250#define LoFreq 5000

int delay; /* delay count for OC5 operation */

int main(void){

asm("cli");TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */TSCR2 = 0x03; /* set prescaler to TCNT to 1:8 */TIOS |= BIT5; /* enable OC5 */TCTL1 = 0x04; /* select toggle for OC5 pin action */delay = HiFreq; /* use high frequency delay count first */TC5 = TCNT + delay; /* start an OC5 operation */TIE |= BIT5; /* enable TC5 interrupt */asm("cli");

C Program for Siren Generation (1 of 2)

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while(1) {delayby100ms(5); /* wait for half a second */delay = LoFreq; /* switch to low frequency tone */delayby100ms(5); /* wait for half a second */delay = HiFreq; /* switch to high frequency tone */

}return 0;

}

#pragma interrupt_handler oc5_ISRvoid oc5_ISR(void){

TC5 += delay;}

#pragma abs_address:vtimch5 // Initialize the Interrupt Vector addressvoid (*interrupt_vectors[]) (void) = {oc5_ISR}; // Assign the function pointer #pragma end_abs_address // to the ISR

C Program for Siren Generation (2 of 2)

Preferred Initialization

void init_TimerCh5(void){

TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */TSCR2 = 0x03; /* set prescaler to TCNT to 1:8 */TIOS |= BIT5; /* enable OC5 */TCTL1 = 0x04; /* select toggle for OC5 pin action */TIE |= BIT5; /* enable TC5 interrupt */

}

Then we have ….

int main(void){

asm(“sei");init_TimerCh5(); /* initialize channel 5*/delay = HiFreq; /* use high frequency delay count first */TC5 = TCNT + delay; /* start an OC5 operation */asm("cli");

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More Timing Capabilities

• Play “The Star-Spangled Banner”• More digital waveform generation• Pulse accumulator operations• N pulse event detector• Alternate frequency measurement technique• Gate time method for measuring a pulse duration• Modulus down-counter to generate periodic interrupts

– See delay.asm from textbook CD

PWM

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Overview of PWM Functions

• Many applications require the generation of digital waveform.– Output compare function can be used to generate digital waveform

but incur too much overhead.– Pulse width modulation requires only the initial setup of period and

duty cycle for generating the digital waveform.

• PWM Applications– Motor Drive Systems– Waveform Generation– Periodic Clock Outputs– Low Cost Digital to Analog Converter (PWM and a Filter)

• The PWM shares the eight Port P pins (PWM0…PWM7).

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Pulse Width Modulation (PWM)

• Each PWM channel has a period register, a duty cycle register, a control register, and a dedicated counter.

• The clock input to PWM is programmable through a two-stage circuitry.

• There are four possible clock sources for the PWM module: clock A, clock SA, clock B, and clock SB.– Clock A and clock B are derived by dividing the E clock by a

power of 2. The power can range from 0 to 7.– Clock SA is derived by dividing the clock A by an even number

ranging from 2 to 512.– Clock SB is derived by dividing the clock B by an even number

ranging from 2 to 512.

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• Many applications require the generation of digital waveform.

• Output compare function can be used to generate digital waveform but incur too much overhead.

• Pulse width modulation requires only the initial setup of period and duty cycle for generating the digital waveform.

• The MC9S12DP512 has an 8-channel PWM module.

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• Each PWM channel has a period register, a duty cycle register, a control register, and a dedicated counter.

• The clock input to PWM is programmable through a two-stage circuitry.

• There are four possible clock sources for the PWM module: clock A, clock SA, clock B, and clock SB.– Clock SA is derived by dividing the clock A by an even number

ranging from 2 to 512.– Clock SB is derived by dividing the clock B by an even number

ranging from 2 to 512.– Clock A and clock B are derived by dividing the E clock by a

power of 2. The power can range from 0 to 7.

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Channel 7

Period and duty Counter

PWM Channels

Channel 6


Channel 5


Channel 4


Channel 3


Channel 2


Channel 1


Channel 0


Clock select

Control

PWMclock

PWM Module

Enable

Polarity

Alignment

Bus clock

PWM7

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

PWM0

Figure 8.38 HCS12 PWM block diagram

PWM Block Diagram

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7 6 5 4 3 2 1 0

0 PCKB2 PCKB1 PCKB0 0 PCKA2 PCKA1 PCKA0

reset: 0 00 0 0 0 0 0

Table 8.3 Clock B prescaler selects

PCKB2 PCKB1 PCKB0 value of clockB

00001111

00110011

01010101

E clockE clock/2E clock/4E clock/8E clock/16E clock/32E clock/64E clock/128

Table 8.4 Clock A prescaler selects

PCKA2 PCKA1 PCKA0 value of clockA

00001111

00110011

01010101

E clockE clock/2E clock/4E clock/8E clock/16E clock/32E clock/64E clock/128

Figure 8.41 PWM prescale clock select register (PWMPRCLK)

PWM Clock Generation

• The prescale factors for clock A and clock B are determined by the PCKA2…PCKA0 and PCKB2…PCKB0 bits of the PWMPRCLK register.

– Clock SA is derived by dividing clock A by the value of the PWMSCLA register and then dividing by 2.

– Clock SB is derived by dividing clock B by the value of the PWMSCLB register and then dividing by 2.

• The clock source selection is controlled by the PWMCLK register.

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7 6 5 4 3 2 1 0

PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0

reset: 0 00 0 0 0 0 0

Figure 8.42 PWM clock select register (PWMCLK)

PCLKx: PWM channel x clock select (x = 7, 6, 3, 2) 0 = clock B as the clock source 1 = clock SB as the clock sourcePCLKy: PWM channel y clock select (y = 5, 4, 1, 0) 0 = clock A as the clock source 1 = clock SA as the clock source

PWM Clock Source Selection

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PWM Channel Timers

• The main part of each PWM channel x consists of an 8-bit counter (PWMCNTx), an 8-bit period register (PWMPERx), and an 8-bit duty cycle register (PWMDTYx).– The waveform output period is controlled by the match between

the PWMPERx register and PWMCNTx register.– The waveform output duty cycle is controlled by the match of the

PWMDTYx register and the PWMCNTx register.

• The starting polarity of the output is selectable on a per channel basis by programming the PWMPOL register.

• A PWM channel must be enabled by setting the proper bit of the PWME register.

• The overall operation of the PWM module is shown in Figure 8.44.

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7 6 5 4 3 2 1 0

PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0

reset: 0 00 0 0 0 0 0

Figure 8.43 PWM polarity register (PWMPOL)

PPOLx: PWM channel x polarity 0 = PWM channel x output is low at the start of a period, then goes high when the duty count is reached. 1 = PWM channel x output is high at the start of a period, then goes low when the duty count is reached.

7 6 5 4 3 2 1 0

PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0

reset: 0 00 0 0 0 0 0

Figure 8.45 PWM enable register (PWME)

PWMEx: PWM channel x enable 0 = PWM channel x disabled. 1 = PWM channel x enabled.

PWMPOL and PWME

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GATE8-bit counter

PWMCNTx

8-bit compare=

PWMDTYx

clocksource

8-bit compare=

PWMPERx

T Q

QR

MUX

T

R

CAExQ

Q

MUX

to pindriver

PPOLx

From port PTPdata register(clock edge sync)

PWMEx

up/down re

set

Figure 8.44 PWM channel block diagram

PWM Channel Block Diagram

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7 6 5 4 3 2 1 0

CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0

reset: 0 00 0 0 0 0 0

Figure 8.46 PWM center align enable register (PWMCAE)

CAEx: Center aligned enable bit for channel x 0 = PWM channel x output is left aligned 1 = PWM channel x output is center alighed

PWM Waveform Alignment

• PWM output waveform can be left-aligned or center-aligned.

• The choice of alignment is controlled by the PWMCAE register.

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Left-Aligned Output

• The PWMCNTx counter is configured as a count-up counter.– PWMx frequency = Clock(A, B, SA, SB frequency) PWMPERx– Polarity = 0– PWMx duty cycle = [(PWMPERx – PWMDTYx) PWMPERx] 100%– Polarity = 1– PWMx duty cycle = [PWMDTYx PWMPERx] 100%

PWMDTYxPeriod = PWMPERx

PPOLx = 0

PPOLx = 1

Figure 8.47 PWM left-aligned output waveform

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Center-Aligned Mode

• PWM counter operates as an up/down counter and is set to count up whenever the counter is equal to $00.

• When the counter matches the duty register the output flip-flop changes state causing the PWM output to also change state.

• A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count.

• When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the PWM output to also change state.

• When the PWM counter decrements to 0, the counter direction changes from a down-count back to an up-count and the period and duty registers are reloaded from their buffers.

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PWMx frequency = Clock (A, B, SA, or SB) frequency (2 PWMPERx)

When polarity = 0,PWMx duty cycle = [(PWMPERx – PWMDTYx) PWMPERx] 100%

When polarity = 1,PWMx duty cycle = [PWMDTYx PWMPERx] 100%

PPOLx = 0

PPOLx = 1PWMDTYx PWMDTYx

PWMPERx PWMPERx

Period = PWMPERx * 2Figure 8.48 PWM center aligned output waveform

In Aligned Mode

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PWM 16-bit Mode (1 of 2)

• Two adjacent PWM channels can be concatenated into a 16-bit PWM channel.

• The concatenation of PWM channels are controlled by the PWMCTL register.

• The 16-bit PWM system is illustrated in Figure 8.49. • When channel k and k+1 are concatenated, channel k is the

high-order channel, whereas channel k+1 is the lower channel. (k is even number). A 16-bit channel outputs from the lower-order channel pin and is also enabled by the lower-order channel.

• Both left-aligned and center-aligned mode apply to the 16-bit mode.

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7 6 5 4 3 2 1 0

CON67 CON45 CON23 CON01 PSWAI PFRZ 0 0

reset: 0 00 0 0 0 0 0

Figure 8.40 PWM control register (PWMCTL)

CONjk: concatenate channels j and k (j = 0, 2, 4, or 6; k = j+1) 0 = channel j and k are separate 8-bit PWMs 1 = Channels j and k are concatenated to create one 16-bit PWM channel. Channel j becomes the high order byte and channel k becomes the low order byte. Channel k output pin is used as the output for this 16-bit PWM. Channel k clock select bit determines the clock source, channel k polarity bit determines the polarity, channel k enable bit enables the output and channel k center aligned enable bit determines the output mode.PSWAI: PWM stops in wait mode 0 = allow the clock to the prescaler to continue while in wait mode 1 = stop the input clock to the prescaler whenever the MCU is in wait modePFRZ: PWM counters stop in freeze mode 0 = allow PWM to continue while in freeze mode 1 = disable PWM input clock to the prescaler whenever the part is in freeze mode.

PWM 16-bit Mode (2 of 2)

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PWMCNT6 PWMCNT7

Period/Duty compare PWM7

Clock source 7

PWMCNT4 PWMCNT5


Clock source 5

PWMCNT2 PWMCNT3


Clock source 3

PWMCNT0 PWMCNT1


Clock source 1

high

high

high

high

low

low

low

low

Figure 8.49 PWM 16-bit mode

PWM 16-bit Block Diagram

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#include “c:\miniide\hcs12.inc”…movb #0,PWMCLK ; select clock A as the clock source for PWM0movb #1,PWMPRCLK ; set clock A prescaler to 2movb #1,PWMPOL ; channel 0 output high at the start of the periodmovb #0,PWMCAE ; select left-aligned modemovb #$0C,PWMCTL ; 8-bit mode, stop PWM in wait and freeze modemovb #120,PWMPER0 ; set period valuemovb #60,PWMDTY0 ; set duty valuemovb #0,PWMCNT0 ; reset the PWM0 counterbset PWMEN,PWME0 ; enable PWM channel 0

• Write an instruction sequence to generate a 100KHz waveform with 50% duty cycle from the PWM0 pin (PP0). Assume that the E clock frequency is 24 MHz.

• Solution: Use the following setting:– Select clock A as the clock source to PWM0 and set its prescaler to 2.– Select left-aligned mode.– Load the value 120 into the PWMPER0 register (= 24000000 100000 2)– Load the value 60 into the PWMDTY0 register (= 120 50%)

Example 8.21

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movb #0,PWMCLK ; select clock A as the clock sourcemovb #1,PWMPOL ; set PWM0 output to start with high levelmovb #1,PWMPRCLK ; set the PWM0 prescaler to clock A to 2movb #1,PWMCAE ; select PWM0 center-aligned modemovb #$0C,PWMCTL ; select 8-bit mode, stop PWM in wait modemovb #120,PWMPER0 ; set period valuemovb #72,PWMDTY0 ; set duty valuebset PWME,PWME0 ; enable PWM channel 0

• Write an instruction sequence to generate a square wave with 20 ms period and 60% duty cycle from PWM0 and use center-aligned mode.

• Solution: – Select clock A as the clock source and set its prescaler to 2.– Load the value 120 into PWMPER0 register.– PWMPER0 = (20 24,000,000 1000,000) 2 2 = 120– PWMDTY0 = PWMPER0 60% = 72.

Example 8.22

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movb #0,PWMCLK ; select clock A as the clock sourcemovb #2,PWMPOL ; set PWM0:PWM1 output to start with high levelmovb #4,PWMPRCLK ; set prescaler to 16movb #$1C,PWMCTL ; concatenate PWM0:PWM1, stop PWM in wait modemovb #0,PWMCAE ; select left align modemovw #30000,PWMPER0 ; set period to 30000movw #24000,PWMDTY0 ; set duty to 24000bset PWME,PWME1 ; enable PWM0:PWM1

• Write an instruction sequence to generate a 50 Hz digital waveform with 80% duty cycle using the 16-bit mode from the PWM1 output pin.

• Solution: Using the following setting:– Select clock A as the clock source and set its prescaler to 16.– Select left aligned mode and select polarity 1.– Load the value 30000 into the PWMPER0:PWMPER1 register.– Load the value 24000 into the PWMDTY0:PWMDTY1 register.

Example 8.23

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#include “c:\egnu091\include\hcs12.h”#include “c:\egnu091\include\delay.c”

• Use PWM to dim the light bulb. Assume that we use the PWM0 output to control the brightness of a light bulb. Write a C program to dim the light to 10% brightness gradually in five seconds.

• The E clock frequency is 24 MHz.• Solution:

– Set duty cycle to 100% at the beginning.– Dim the brightness by 10% in the first second and then 20% per second in the following

four seconds.– Load 100 into the PWMPER0 register at the beginning. – Decrement PWMPER0 by 1 every 100 ms during the first second and decrement

PWMPER0 by 2 every 100 ms in the following four seconds.

Example 8.24

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void main (){

int dim_cnt;PWMCLK = 0; /* select clock A as the clock source */PWMPOL = 1; /* make waveform to start with high level

*/PWMCTL = 0x0C; /* select 8-bit mode */PWMPRCLK = 2; /* set clock A prescaler to 4 */PWMCAE = 0; /* select left-aligned mode */PWMPER0 = 100; /* set period of PWM0 to 0.1 ms */PWMDTY0 = 100; /* set duty cycle to 100% */PWME |= 0x01; /* enable PWM0 channel */

/* reduce duty cycle 1 % per 100 ms in the first second */for (dim_cnt = 0; dim_cnt < 10 ; dim_cnt ++) {delayby100ms(1);

PWMDTY0--;}

/* reduce duty cycle 2% per 100 ms in the next 4 seconds */for (dim_cnt = 0; dim_cnt < 40; dim_cnt ++) {

delayby100ms(1);PWMDTY0 -= 2;

}asm ("swi");

}

C Code

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DC Motor Control (1 of 4)

• The DC motor has a permanent magnetic field and its armature is a coil.

• When a voltage and a subsequent current flow are applied to the armature, the motor begins to spin.

• The voltage level applied across the armature determines the speed of rotation.

• Changing the speed requires varying the effective voltage level of the input to the motor. (Use PWM duty cycles)

• Almost every application that uses a DC motor requires it to reverse its direction of rotation or vary its speed.

• Reversing the direction is done by changing the polarity of voltage applied to the motor.

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• Changing the voltage level can be achieved by varying the pulse width of a digital signal input to the DC motor.

• The HCS12 can interface with a DC motor through a driver as shown in Figure 8.52.

• A suitable driver must be selected to take control signals from the HCS12 and deliver the necessary voltage and current to the motor.

• An example of DC motor driver is shown in Figure 8.53.• The L293 has two supply voltages: VSS and VS. VSS is

logic supply and can be from 4.5 to 36V. VS is analog and can be as high as 36 V.

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HCS12

PP7

PP3

PT0feedback

direction

speedon/off

Driver DC motor

Figure 8.52 Simplified circuit for DC motor control


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12

34

5678 9

101112

1314

1516CE1

IN1

OUT1GND

GNDOUT2

IN2VS CE2

IN3

OUT3

GND

GND

IN4

OUT4

VSS

(a) Pin Assignment

M

M

M10

1010

10

0101 1

2

3

45

6

7

8

1615

141312

11

109

VSS

VS(b) Motor connection

Figure 8.53 Motor driver L293 pin assignment and motor connection

L293L293

1

2

3

4


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DC Motor Feedback (1 of 2)

• The DC motor speed must be fed back to the microcontroller so that it can be controlled. – The motor speed can be fed back by using an optical encoder, infrared

detector, or a Hall-effect sensor.– Basing on the speed feedback, the microcontroller can make adjustment to

increase or decrease the speed, reverse the direction, or stop the motor.• Assume two magnets are attached to the shaft (rotor) of a DC motor

and a Hall-effect transistor is mounted on the armature (stator). – As shown in Figure 8.54, every time the Hall-effect transistor passes

through the magnetic field, it generates a pulse. • The input capture function of the HCS12 can capture the passing time

of the pulse. The time between two captures is half of a revolution. Thus the motor speed can be calculated.

ECE 4510/5530

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t

T/2T is the time for one revolution

Magnets

Hall-effecttransistor

Figure 8.54 The output waveform of the Hall effect transistor

DC Motor Feedback (2 of 2)

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A DC Motor Control System (1 of 4)

• Schematic is shown in 8.55.• The PWM output from the PP3 pin is connected to one end

of the motor whereas the PP7 pin is connected to the other end of the motor.

• The circuit is connected so that the motor will rotate clockwise when the voltage of the PP7 pin is 0 while the PWM output is nonzero (positive).

• The direction of motor rotation is illustrated in Figure 8.56. • By applying appropriate voltages on PP7 and PP3

(PWM3), the motor can rotate clockwise, counterclockwise, or even stop.

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• Input capture channel 0 is used to capture the feedback from the Hall-effect transistor.

• When a DC motor is first powered, it takes time for the motor to reach its final speed.

• When a load is added to the motor, it will be slowed down and hence the duty cycle of the PWM3 should be increased to keep the speed constant.

• When the load is reduced, the speed of the motor will be increased and hence the duty cycle of the PWM3 should be decreased.

• A DC motor does not respond to the change of the duty cycle instantaneously. Several cycles must be allowed for the microcontroller to determine if the change of the duty cycle has achieved its effect.

ECE 4510/5530

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VCC

PWM3PP7

4591011NC

10K

VCC

1827

VCC

163

6.8F

614

151312

0.33 F

6.8F

M

VCC

301373 2

1

Hall-effectswitch

All diodes are the same and could be any one of the 1N4000 series

Figure 8.55 Schematic of a HCS12-based motor-control system

PT0

HCS12

L293

A Motor Control System (3 of 4)

ECE 4510/5530

101

Motor

L293

A

B

PWM (PP3)

Port Pin (PP7)

clockwise

off off

counterclockwise

A

B

When A = B, torqueapplied to motor = 0

When A B, motor runs

Figure 8.56 The L293 motor driver


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Example 8.25

• Write a subroutine in C language to measure the motor speed (in rpm) assuming E clock is 16 MHz.

• Solution: – Two consecutive rising edges on the PT0 pin must be captured in

order to measure the motor speed.– Let diff be the difference of two captured edges and the period is

set to 1 ms, then • Speed = 60 × 106 ÷ (2 × diff)

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#include “c:\egnu091\include\hcs12.h”

unsigned int motor_speed (void){

unsigned int edge1, diff, rpm;long int temp;

TSCR1 = 0x90; /* enable TCNT and fast flag clear */TIOS &= IOS0; /* select IC0 function */TSCR2 = 4; /* set TCNT prescale factor to 16 */TCTL4 = 0x01; /* select to capture the rising edge of PT0 */ TFLG1 = C0F; /* cleared C0F flag */while (!(TFLG1 & C0F)); /* wait for the first edge */edge1 = TC0;while (!(TFLG1 & C0F)); /* wait for the second edge */diff = TC0 - edge1;temp = 1000000l / (long)(2 * diff);rpm = temp * 60;return rpm;

}

C Code

ECE 4510/5530 Microcontroller Applications ECT and PWMbazuinb/ECE4510/Ch08.pdf · ECE 4510/5530 Microcontroller Applications Chapter 8 ECT and PWM Dr. Bradley J. Bazuin ... – TFLG1

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