ECE 448: Lab 5 DSP and FPGA Embedded Resources (Signal Filtering and Display)

ECE 448: Lab 5

DSP and FPGA Embedded Resources(Signal Filtering and Display)

Finite Impulse Response (FIR) Filters

• FIR: Given an impulse input, the filter output goes to zero in a finite number of clocks because there is no feedback of the output to the input

• Filter: manipulate the frequency response• Examples: low-pass, high-pass, band pass, notch,

arbitrary• Equation:

1

0

][][][N

n

nhnmxmy y : outputx : inputh : filter tapsN : number of taps

Low Pass Filter

0 10 20 30 40 50 600

0.2

0.4

0.6

0.8

1

Single-sided Frequency Response

Frequency [kHz]

Mag

nitu

de

Parallel Approach

• Output every clock• One multiplier per tap• N-input adder• x[n]: shift register• h[n]: stored constants

• Note the bit growth

REG

x[n]

L

REG

L

L

REG

L

h[1]

M

h[2]

M

M

h[N-1]

M

X

+

X

X

X

L+M

L+M

L+M

L+M

X

L+M

ML

h[0]

L+M+ceil(log2(N))

REGL+M+ceil(log2(N))

Serial Approach

• Output every N clocks• One multiplier• Two input Adder• Multiply-Accumulate

(MAC)

• Note the bit growth

REG

x[n]

L

REG

L

L

REG

L

h[1]

M

h[2]

M

M

h[N-1]

M

+

X

L+M

ML

h[0]

L+M+ceil(log2(N))

REG

L+M+ceil(log2(N))

L M

Parallel-Serial Approach

• K multipliers• Output every N/K clocks• K+1 input Adder• Multiply-Accumulate

(MAC)

• Note the bit growth

REG

x[n]

L

REG

L

L

REG

L

h[1]

M

h[2]

M

M

h[N-1]

M

+

ML

h[0]

L+M+ceil(log2(N))

REG

L+M+ceil(log2(N))

X

L+M

L M

X

L+M

L M

Lab 4 Top Level

NCO FilterMagnitude

ScaleAverage

VGA Sync

Generator

sw[5:0]

Seven SegmentDisplayDriver

Shape and

ColorGenerator

vsync

redgreenblue

an[3:0]

DACDriver

pmoda

seg[7:0]

hsync

valid

out in

step6

18 44 16

valid valid

in

valid

out avg

4

8

8

8

x

y

blank

freq

h_count

v_count

blank

seg

mag

filter

nco

btn[0] led[2:0]3

an

ca

hsync

vsync

out

ledsel

magnitude

sel

sw[7:6]2

avg colors

pmodb4

4

44

Task 1: Numerically Controlled Oscillator (NCO)(1pt single person, 0.75pts teams)

• 6-bit Frequency Control Word (FCW) or step size• 10-bit accumulator: sum[n] = sum[n-1] + step*8• 1024 18-bit signed sine values in a Lookup Table (LUT)• Accumulator addresses the LUT• Sine values stored in 1 inferred Block RAM• Update every 195 clocks, valid pulse (on for one clock)

NCOsw[5:0]

valid

out

step6

18

Task 1: Simulating Analog Signals

• Change the signal property in the simulation application to:• Show the waveform in analog form• Change the height of the analog waveform• Change the radix of the signal to signed or unsigned

Task 2: Filter(2pts single person, 1.5pts teams)

• 256-tap FIR Filter using Parallel-Serial approach• 2 Multipliers by instantiating the Multiplier Primitive• 256 samples stored in circular buffer used as a shift register• Sample Buffers are inferred dual-port distributed RAM • Taps stored in dual port Block ROM using CORE Generator• Starts processing when valid input is high• Generates a valid output pulse (on for one clock)

Filter

in18 44

valid valid

out

Task 2: Multiplier Primitive MULT18X18SIO_inst : MULT18X18SIO generic map ( AREG => 1, -- Enable the input registers on the A port (1=on, 0=off) BREG => 1, -- Enable the input registers on the B port (1=on, 0=off) B_INPUT => "DIRECT", -- B cascade input "DIRECT" or "CASCADE" PREG => 1) -- Enable the input registers on the P port (1=on, 0=off) port map ( BCOUT => BCOUT, -- 18-bit cascade output P => P, -- 36-bit multiplier output A => A, -- 18-bit multiplier input B => B, -- 18-bit multiplier input BCIN => BCIN, -- 18-bit cascade input CEA => CEA, -- Clock enable input for the A port CEB => CEB, -- Clock enable input for the B port CEP => CEP, -- Clock enable input for the P port CLK => CLK, -- Clock input RSTA => RSTA, -- Synchronous reset input for the A port RSTB => RSTB, -- Synchronous reset input for the B port RSTP => RSTP, -- Synchronous reset input for the P port );

Task 2: Inferred Distributed RAM

-- Ensure that the <ram_name> is correctly defined. -- Please refer to the RAM Type Declaration template for more info.

process (<clock>)begin if (<clock>'event and <clock> = '1') then if (<write_enable> = '1') then <ram_name>(conv_integer(<address>)) <= <input_data>; end if; end if;end process;

<ram_output> <= <ram_name>(conv_integer(<address>));

Task 3: Magnitude, Scale, Moving Average(1pt single person, 0.75pts teams)

• Calculates when valid is high• Magnitude: magnitude = abs(in)• Scale: scale = magnitude / 2^20• Moving Average:

• Store 1024 of the most recent scaled values in circular buffer acting as a shift-register.

• Implement circular buffer using a 1024x18 Block RAM using CORE Generator

• sum[n] = sum[n-1] + scale[n] - scale[n-1024]• Don’t forget to account for the accumulator bit growth• avg = sum / 2^10

MagnitudeScale

Average44 16

valid

in avg

magnitude

44

1024

][][

1023

0

n

nmscalemavg

Task 4: Seven Segment Display(1pt single person, 0.75pts teams)

NCO FilterMagnitude

ScaleAverage

sw[5:0]

Seven SegmentDisplayDriver

an[3:0]

seg[7:0]

valid

out in

step6

18 44 16

valid valid

in

valid

out avg

4

8seg

an

ca

Task 5: Filter Select(1pts single person, 0.75pts teams)

NCO FilterMagnitude

ScaleAverage

sw[5:0]

Seven SegmentDisplayDriver

an[3:0]

seg[7:0]

valid

out in

step6

18 44 16

valid valid

in

valid

out avg

4

8seg

an

ca

sel

sw[7:6]2

• Switch[7:6] selects one of four filters in the Tap Buffer• Sketch the frequency response of each filter

Task 5: Tap Buffer Memory Map

Task 6: VGA Display(1pt bonus single person, 0.75pts teams)

NCO FilterMagnitude

ScaleAverage

VGA Sync

Generator

sw[5:0]

Seven SegmentDisplayDriver

Shape and

ColorGenerator

vsync

redgreenblue

an[3:0]

seg[7:0]

hsync

valid

out in

step6

18 44 16

valid valid

in

valid

out avg

4

8

8

x

y

blank

freq

h_count

v_count

blank

seg

an

ca

hsync

vsync

sel

sw[7:6]2

avg colors

Task 6: VGA Display(2pts bonus single person, 1.5pts teams)

• X-axis: Frequency• Y-axis: Average Magnitude• 10 pixels wide• height = avg / 2^6

0 639

479

0

(639,479)

Task 7: Digital-to-Analog Converter(1pts bonus single person, 0.75pts teams)

• Generates analog signal to show on oscilloscope• Convert signed to biased unsigned (ex: [-128:127] to [0:255])• Button[0] cycles between the NCO, Filter, and Magnitude• NCO selected: out = nco / 2^10 and LED[0]

on• Filter selected: out = filter / 2^29 and LED[1]

on• Magnitude selected: out = mag / 2^29 and LED[2]

on

DACDriver

pmoda8

mag

filter

nco

led[2:0]3

out

ledsel

pmodb4

4

btn[0]

44

44

18

8-Bit Parallel Digital-to-Analog Converter (DAC)

• PMOD-R2R• http://www.digilentinc.com

PMOD Pins on BoardNET “PMODA<0>" LOC = “B2" | IOSTANDARD = LVTTL ;NET “PMODA<1>" LOC = “A3" | IOSTANDARD = LVTTL ;NET “PMODA<2>" LOC = “J3" | IOSTANDARD = LVTTL ;NET “PMODA<3>" LOC = “B5" | IOSTANDARD = LVTTL ;

NET “PMODB<0>" LOC = “C6" | IOSTANDARD = LVTTL ;NET “PMODB<1>" LOC = “B6" | IOSTANDARD = LVTTL ;NET “PMODB<2>" LOC = “C5" | IOSTANDARD = LVTTL ;NET “PMODB<3>" LOC = “B7" | IOSTANDARD = LVTTL ;

Switch and Buttons Functions• Switch[5:0] NCO Frequency Control Word (step)

– Used in NCO and Shape Generator

• Switch[7:6] Filter Select

• Button[0] DAC Select– NCO– Filter– Magnitude

CORE Generator Demonstration